4.

2 PRINTED CIRCUITS HANDBOOK

the package will continue to play an increasingly role in determining performance and cost of
the IC. As a result, packaging technologies must continue to improve on the protection pro-
vided for the IC, the handling of thermal dissipation, and the routing of more and more signal
interconnections, as well as power and ground distribution, through smaller and smaller
spaces.4 Many packages include passive devices in the form of integral passives. The advent of
micro-electro-mechanical systems (MEMS), micro-opto-electro-mechanical systems (MOEMS),
and even biological packages and applications has further added to the already high demands
on packaging. Optoelectronic packages contain not only semiconductor devices but also opti-
cal components, such as optical fibers, lens assemblies, and, depending on the application, ele-
ments, such as optical multiplexers/demultiplexers. MEMS and MOEMS both include tiny
moving parts inside the package. In view of the increased scope, advanced packaging is prob-
ably a more appropriate terminology than simply electronic packaging.
Over the past decade or two, semiconductor technology has evolved to the point where
packaging cannot be considered as an afterthought in device design and manufacturing. The
package plays an increasingly more integral, sometimes decisive role in the performance of the
semiconductor device or devices it contains. The International Technology Roadmap for Semi-
conductors (ITRS) addresses this fact,5 stating the following in its assembly and packaging sec-
tion:“There is an increased awareness in the industry that assembly and packaging is becoming
a differentiator in product development. Package design and fabrication are increasingly
important to system applications. It is no longer just a means of protecting the integrated cir-
cuit (IC), but also a way for the systems designer to ensure form fit and function for today’s
product—spanning consumer products to high-end workstations.” Although the definition of
high-density packaging varies across the interconnect pitch to a package that has to be code-
signed with the chip, it is understood that high-density packaging is and will continue to be a
requirement for high-performance ICs and systems.5 Figure 4.1 shows the evolution of what
have been termed advanced packaging technologies for the past few years in terms of system-
level packaging efficiency. It is anticipated that system-on-a-chip (SOC) and system-on-a-package
(SOP) technologies will dominate advanced packaging for the next several years.
System Level Packaging Efficiency

100
SOC

80

SOP
60
MCM
40

P
CSSP
C
20

1980s 1990s 2000s

FIGURE 4.1 Evolution of system-level packaging efficiency.

4.2 LEAD-FREE

A new requirement on packages—that of lead-free solder—has initiated a tremendous

amount of developmental effort in the past few years. This effort stems from the requirement
of packages exported to the European Union (EU) market, to pass Restriction of Hazardous
Substances (RoHS) compliance requirements set forth in the Directive 2002/95/EC of the
 ADVANCED COMPONENT PACKAGING 4.3

European Parliament.6 Origins of the RoHS requirements stem from the need to restrict the
use of specific materials found in electrical and electronic products due to their hazardous
nature, the risk posed to the environment, their ability to pollute landfills, and the risk posed
during its use in component manufacturing and recycling.
The substances banned under RoHS requirements and its maximum allowable trace val-
ues are as follows:
● Lead: 0.1 percent by weight (1,000 ppm)
● Cadmium: 0.01 percent by weight (100 ppm)
● Mercury: 0.1 percent by weight (1,000 ppm)
● Hexavalent chromium: 0.1 percent by weight (1,000 ppm)
● Polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE): 0.1 percent
by weight (1,000 ppm) combined

Two other related but different terms sometimes used in this context are the “lead-free”
and “green.” RoHS is clearly more than “lead-free,” but “green” includes absence of antimony
(Sb) and halogens (chlorine, bromine, and iodine). However, the eutectic tin-lead solder
(Sn63%–Pb37%, or SnPb for short) cannot be used in any of the preceding. This single
requirement is bringing about a paradigm shift to the world of advanced packaging. The SnPb
solder has been in use in the electronics and related industry for about three decades now.
During this time, the entire infrastructure related to package manufacture—beginning from
the assembly materials such as substrates, flux, and underfill, and in case of flip-chip, wafer
bumping—equipment such as substrate bake and solder reflow ovens and the package relia-
bility requirements such as the JEDEC standards have been centered around the SnPb solder.
Changing the requirement to now eliminate Pb from electronic packages translates to a
change in all of the preceding. This change stems from an inherent difference in the physical
and metallurgical properties—and hence, the processibility and reliability of the two solder
materials. SnPb is an eutectic composition of its two parent elements, and has a melting temper-
ature of 183°C. Lead-free solder alloys, almost regardless of their type and composition, have a
higher melting point. Further, most of the lead-free compositions are not eutectic in nature, mean-
ing that they do not melt at one temperature. Instead, such compositions have a softening range
of temperature. Additionally, the higher melting/softening temperature imposes additional
requirements on the assembly materials and on the assembly process. For example, because of
the higher solder reflow temperatures for Pb-free solders, the substrates must be able to main-
tain their integrity and withstand a higher temperature. The flux used in the flip-chip assembly
process now needs to be more aggressive in order to be effective on Pb-free solders and must
not burn off at higher temperatures that correspond to the higher melting temperatures of Pb-
free solders, while simultaneously leaving behind a residue that is not corrosive. The underfill
also needs to be suitably selected so that its chemistry is compatible with the flux residue.
Additional challenges are due to the fact that it is difficult to change all components on a sys-
tem, all at a time, to lead-free. Consequently, the industry must cope with a scenario where a sys-
tem has mixed metallurgy—partly SnPb based and the others Pb-free—on the system boards.

4.3 SYSTEM-ON-A-CHIP (SOC) VERSUS

SYSTEM-ON-A-PACKAGE (SOP)

For decades, the most efficient way to add more functions to an electronic system has been
to integrate more functions on a chip either by reducing minimum line width, increasing the
size of the chip, or both. Recently, however, it is beginning to be recognized that on-chip inte-
gration poses several practical challenges as the die size grows to increasing proportions. With
increasing die size, the die-per-wafer yield at the wafer fabrication starts going down, partly due
to the increased complexity, but also due the challenges in the wafer manufacturing processes.
4.4 PRINTED CIRCUITS HANDBOOK

To complicate the problem further, off-chip interconnects are beginning to contribute to the
challenge of SOC integration. What this means is that interconnects, and not the ICs, are domi-
nating, and often limiting, the system performance and increasing its cost.7 Consequently, there
is mounting support for moving interconnects off the chip and onto the package.8

4.3.1 System-on-a-Chip (SOC)

There are many reasons why semiconductor manufacturers continue to push on-chip integration
of a system.9 The reason most often cited is that on-chip integration allows faster interconnection
between circuit components simply because of the shorter distances involved. However, it has
been pointed out that this may not be the case for all designs. For example, on a large digital IC
running at a high clock frequency, a signal traveling on a global interconnection trace may take
dozens of clock cycles to reach its destination. In such a case, dividing the device into smaller dice
and using high-density interconnects on a package substrate can actually be faster.10
Another reason for continuing with on-chip system integration is to avoid the configuration
of a multichip package (MCP) because, historically, packages containing a system composed of
a multiple number of chips have been larger than those containing a single-chip system.
Although designers will continue to be pressured to integrate as much functionality onto a
single chip as possible, there are many factors that must be considered when deciding if SOC
is the right approach to the design of an electronic system. Furthermore, as minimum geome-
tries continue to shrink and chip sizes continue to increase due to the incorporation of addi-
tional functionality, a point may be reached where it becomes economically impractical, if not
impossible, to fabricate SOC. At this point, SOP may provide the only practical alternative to
SOC. Now that chip and package are starting to be codesigned, an opportunity exists to
develop capabilities for designing the SOP solutions that would cost less and perform better
than SOP solutions.11 Figure 4.2 provides a list of some of the challenges that must be
addressed if SOC is to become the standard approach to electronic system integration.

SOC Challenges SOP Challenges

Fundamental: latency, SiO2 insulation
Process complexity
SOC design and test
Wafer fab costs and yields
Intellectual property for integrated functions
Design: High speed digital, optical analog, RF
Large-area intelligent manufacturing, cost/yield
Thermal management
Testing and reliability
High performance for low cost fab

FIGURE 4.2 Issues that must be addressed prior to full-scale implementation of SOC and SOP.

4.3.2 System-on-a-Package (SOP)

The definition of SOP depends on what is considered to be a system. In fact, much of what is
referred to today as an electronic system is in reality a subsystem, meaning that it does not
perform an autonomous electronic function. Consequently, SOP has multiple definitions. For
example, some consider a multiple number of logic and memory ICs in a single package as an
SOP. On the other hand, if the SOP does not contain analog peripheral device drivers, one
might argue that the package really doesn’t contain a system. Additionally, complete systems
usually contain passive devices in addition to the ICs. Passive devices are required to make
systems work, and if an entire system is to be placed in a package, then the required passives
must go in as well,3, 11 making it what is often referred to an MCM.
Area array packaging is becoming an enabling technology for addressing the needs of cus-
tomized SOP solutions in order to reduce size, weight, and pincount at the second level of
interconnection.12 This type of packaging technology includes pin grid array (PGA), ball grid
array (BGA), and chip-scale packages (CSP), with BGA playing the largest role, primarily
 ADVANCED COMPONENT PACKAGING 4.5

System Trends
System Portability
Wireless / Bluetooth
High Performance
Low Cost
Diverse Functionality

ute
Ro

SO
al

C
ion
Concurrent

Ro
dit
Engineering

u
Tra

te
SOP
Optimization

Packaging Trends IC Trends

Low Cost Fine Lithography
High Performance Large Die
High Integration Expensive Fab Infrastructure
Lower Yield / Higher Cost
Complex Performance Challenges
Reliability Challenges
FIGURE 4.3 Future trends of IC, packaging, and system technologies as envi-
sioned by personnel of the Packaging Research Center at The Georgia Institute of
Technology. (Drawing provided courtesy of the Packaging Research Center, the Geor-
gia Institute of Technology.)

because of its versatility. Compared to conventional leaded packages, BGA packages exhibit
improved electrical performance due to a shorter distance between the IC and the solder
balls, improved thermal performance by the use of thermal vias or heat dissipation through
power and ground planes, reduced handling related lead damage, and increased manufactur-
ing yields due to their self-alignment feature.13 In fact, BGA has been one of the biggest con-
tributing factors to the proliferation of mobile phones and other wireless communication
systems. However, even with the advantages created by area-array packaging, performance,
reliability, and cost requirements are challenging currently available area-array electronic
package design, primarily by because of materials issues14 Fig. 4.3 provides an overview of IC,
packaging, and system trends that are anticipated for the year 2007 and beyond.

4.4 MULTICHIP MODULES

Just as the name implies, MCM technology mounts multiple, unpackaged ICs (bare die), along
with signal conditioning or support circuitry such as capacitors and resistors, to form a system,
or a subsystem on a single substrate.1 In fact, in the late 1980s and early 1990s, MCMs were
considered to be the ultimate interconnect and packaging solution, capable of meeting every
challenge of the electronics industry. This technology placed ICs in close proximity to each
other, thereby enhancing system performance by reducing interconnect delay.15
Size is often the primary driver for MCM-based systems. The typical multicomponent dis-
crete assembly provides a silicon-to-board efficiency of <10 percent (actual total die area versus
the total printed circuit board area). MCM technology can often increase the silicon-to-board
efficiency to 35 or 40 percent with chip and wire assembly processes, and to 50 percent or higher
with some of the higher-density processes.16 Thus, with reduced size and weight, MCMs offer a
practical approach to reducing overall system size while providing enhanced performance due
to a reduction in the interconnect distance between chips.1 Multichip modules typically use
three to five times less board area than their equivalent discrete solution.16