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INPUT
I/O CPU MEMORY
(RAM/
Port ROM)
OUTPUT
ADDRESS BUS
CONTROL
BUS
Block diagram of a Microcomputer.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
reliability. Also, by changing the control program in ROM, new control functions can be added
or modified without any rewiring. One of the fastest growing applications of microcontrollers is
in the automotive industry.
Peripheral Control microprocessors are attached to main microprocessors. So they are also
referred as 'Attach/ Slave microprocessors/Coprocessors'. These are used in many computer
systems for video graphics, data communication, sound synthesis, floating-point math, and direct
memory accesses (DMA). Their main objective is to offload the main microprocessor, thus
saving time and improving speeds. As a result, the main processor is able to concentrate on
higher-level tasks resulting in improved system performance. The concept of 'Distributed
Computing or Processing' is evolving, and future microcomputers systems will be designed with
separate processors for each I/O device in the system. Distributed processing is the organization
of processing in such away that a number of machines (microprocessors) can cooperate in
exchanging data over a network. Local processing is carried out locally and the exchanged data
affects the system as a whole.
CLASSIFICATION OF COMPUTER SYSTEMS: -
The real power of a computer is the titanic speed with which it performs calculations. A
computer sequentially performs one operation at a time. The time required to perform
operations is called the 'Processing Speed' of the computer. This rate is expressed in millions of
instruction per second (MIPS). Computers are classified according to their processing speed. It
depends not only on the hardware characteristics of the system but also on the efficiency of its
software components. Some hardware characteristics of importance in achieving high
processing speed are as follows:
Word Length/Size: is the number of bits treated by the computer as a unit. It can be 4-, 8-, 16-,
32-bits and so on e .g., a 16-bit word will be able to hold numbers in the range from -215 through
+215-1. The number of different types of instructions is directly related to the word length/size.
So it can be concluded that larger the word length, the greater the processing speed.
Data Path Size: depends on the width of the internal CPU buses. Wider data paths speed up
CPU operations, since more information is transmitted in a single transfer.
Other important hardware functions are the logic family, overlapping of CPU instructions,
memory bandwidth, I/O bandwidth etc.
THE Intel 8088/86 MICROPROCESSOR FAMILY: -
The width of the data bus in bits is usually used to categorize the microprocessors. On this basis
of word length they are categorized into:
1. 8-bit microprocessor.
2. 16-bit microprocessor.
3. 32-bit microprocessor and so on.
The width of data bus determines how much data the microprocessor can read or write in one
memory or I/O cycle. The term 16-bit means that its ALU, its internal registers, and most of its
instructions are designed to work with 16-bits (also called 'word'). Some microprocessors have
an internal data bus wider than the external one, e.g. in the Intel 8088 the widths of the external
and internal data buses are 8- and 16-bits respectively, for which it is also referred to as “8/16-
bit microprocessor”. Another example of 8/16-bit microprocessor is Motorola’s 68008. Anyhow,
it is the external data bus that determines the bits transferred during a memory or I/O machine
cycle. Consequently, a device like the 8088 is still considered an 8-bit microprocessor.
The 8088 is one of the pioneer members of the third generation microprocessors, a direct
descendent of the 4004, the world’s first CPU and the heart of the earliest personal computers.
VLSI techniques have given it a lot of muscle- the ability to manipulate 16-bit data, directly
address a MB of memory, a hefty operating speed and a versatile 16-bit instruction set.
FUNDAMENTAL STEPS OF A MICROPROCESSOR CYCLE: -
Execution of an instruction starts from the program counter (PC), which contains the address of
the instruction and ends with the placement of the result in the appropriate location. The
sequence of steps during execution of instructions is:
1. Fetch Instruction: Every instruction cycle begins with an op-code fetch bus cycle i.e., a
memory read of the op-code.
2. Determine Operand: The operand is required to execute the instructions.
3. Execute Instruction: Control signal from the control unit activates the operation, so the
instructions are executed.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
4. Store the Result: The memory stores the result in the specified location, and the
execution/microprocessor cycle ends.
After completing one instruction, the CPU moves on to the next one. This fetch and execute
process is repeated until all of the instruction s in a specific program have been executed. The
CPU’s lifeblood, its heartbeat is the system clock, which synchronizes all activities within the
computer. Each step in the microprocessor cycle takes at least one tick of the system clock called
a 'Clock Cycle or T Cycle' e.g., one T cycle for 8088 5MHz is 200 nanoseconds. We measure the
speed of an instruction by the number of clock cycles required to execute it. A clock cycle is the
microprocessor's smallest unit of time measurement. Each instruction takes a determined
number of clock cycles to execute, depending on the types of operands. The manufacturer and
the computer designer determine the speed of the clock itself.
8088/8086 CPU ARCHITECTURE: -
The term architecture in relation to microprocessor refers to the internal design and
organization of the device. Every microprocessor does two basic things over and over again-
fetching instructions and then executing them. The older microprocessors could only do one
thing at a time, if it is busy fetching an instruction it could not execute one. Whenever CPU
finished executing one instruction, it had to wait for the next one to be gotten from system
memory. This waiting meant a lot of lost and potentially usable microprocessor time. One of the
features introduced with the 8088 is the idea of instruction queue. This feature is a regular part
of mainframes, but had never appeared in a single chip CPU unit until it was designed into the
8088.
The entire process of reading memory, incrementing the IP, and decoding the instruction is
known as the 'Fetch and Execute principle' of the stored program computer. A stored program
computer that works mainly instructions held in store (ROM/RAM) and these can be altered.
One way of increasing the processing speed of a microprocessor is to clock at a higher
frequency. Another way is to employ the 'Pipelining Technique'.
A computer performs sequentially one operation at a time i.e., CPU performs all the tasks
involved in processing an instruction such as fetching, decoding, determining operands, and
executing instructions serially on a one-at-a-time basis. It is termed as 'Serial or Sequential
Fetch/Execute Cycle'. On the other hand, 8088/8086 incorporates 'Overlap Fetch/Execute Cycle',
which is also known as 'Pipelining Technique'. This technique is based on the overlapping of the
execution of several instructions simultaneously. Each instruction is executed as a number of
cycles that must be performed in sequentially. Thus we enable several instructions to be done by
the execution of different cycles on different instructions concurrently.
Fig shows that a model of 8088/86 CPU, which consists of two separate processors, called the
Bus Interface Unit (BIU) and the Execution Unit (EU). Since these tow units are entirely
independent of each other, the 8088 can do two things at the same time. Together they form a
two-stage pipeline. Each unit performs certain tasks associated with the instruction processing
simultaneously and this allows the 8088/86 to achieve a higher execution rate.
1.Bus Interface Unit (BIU): fetches instructions, calculates addresses, fetches operands and
writes results in memory as requested by the EU. However, if no such requests are outstanding
and the bus is free, the BIU proceeds to fill any vacancies created in the Instruction Queue (IQ).
2. Execution Unit (EU): receives program instructions and data from the BIU, executes these
instructions, and stores the result in the general registers. When the EU completes the execution
of an instruction, it passes to the BIU any results (destined for memory or I/O) and proceeds to
the next instruction. The BIU, of course, very likely to be already waiting in the IQ. So the EU is
completely isolated inside the 8088 and is totally dependent on the BIU for communicating with
the real world.
This technique makes recent microprocessors different from previous ones as in it the BIU does
not have to wait to pass the EU a fetched instruction before reading from memory another one.
Instead, it builds a reserve of 4-6 bytes into First-in-First-Out (FIFO) buffer called an
'Instruction Queue or Pre-fetch Queue' (IQ). FIFO is the processing of items in a list such that
the earliest arrival is processed first and the latest arrival is processed last.
The main advantage of the Pipelining is that the EU can execute instructions almost continually
instead of having to wait for the BIU to fetch a new instruction. The IQ has increased the
processing speed also called “Throughput” (productivity of any machine, system or procedure
measured in some term meaningful to the process under consideration) by storing four pre-
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
fetched instructions (six in the 8086). This is obvious from the model of 8088/86. Another subtle
advantage to the Pipelined Architecture is that as the next several instructions are in the IQ, the
BIU can access memory at a 'leisurely' pace. This means that slow-memory parts such as
printers can be used without affecting overall system performance. There are three conditions
that will cause the EU to enter in a 'wait' mode.
1. Firstly when an instruction requires access to a memory location not in the queue.
2. The second condition occurs when the instruction to be executed is a “Branch/Jump”
instruction. In this case control is to be transferred to a new (non-sequential) address.
3. The last condition occurs during execution of instructions that are slow to execute. This can
cause the BIU to suspend fetching instructions.
CONSTRUCTION OF BIU AND EU: -
Firstly, the main parts of the Bus Interface Unit (BIU) are:
1. The instruction Queue
2. The register array
3. An adder
4. A control section
Secondly, the main parts of the Execution Unit (EU) are:
1. The register array
2. The main ALU
3. A flag register
4. A control section
The register array serves addressing purposes. For BIU it includes four segment registers and
instruction pointer, all of which are 16-bits long. This particular adder is used only for address
calculations. It does not possess the full arithmetic/logic capabilities of ALU of the EU. Each
unit of the 8088 has its own independent control section. The control sections generate the basic
timing pulses to control the activities of the circuits operating within the system to ensure that
each instruction occupies a predetermined period, referred to as “Instruction Time”. Here the
control section of the BIU is responsible for all data transfers over the external CPU bus. The
flag register shows the status of the CPU or the results of microoperations.
CPU ORGANIZATION: -
The basic principles of operation of a microprocessor are similar to those of minicomputer and
mainframe central processors. Although many microprocessors are equipped with advanced
features, their basic organization still consists of three main sections.
1. Arithmetic Logic Unit (ALU)
2. Control Unit (CU)
3. Registers
1. Arithmetic Logic Unit (ALU): An ALU is a multioperation, combinational logic digital
function. To perform a microoperation, the control routes the source information from registers
into the inputs of the ALU. The ALU receives the information from the registers and performs a
given operation as specified by the control. The result is then transferred to destination register.
By definition, the ALU is a combinational circuit; thus the inter-register operation can be
performed during one clock cycle. In some microprocessors the result is placed in a specific
register called an 'Accumulator or Accumulator register', abbreviated AC or A register. The
accumulator register in a processor unit is a multipurpose register capable of performing many
microoperations. The operations performed on the data stored in registers are called
'Microoperations'. A microoperation is an elementary operation that can be performed in
parallel during one clock pulse period. Examples of microoperations are shift, count, add, clear,
and load etc. In fact, the gates associated with an accumulator register provide all the digital
functions found in an ALU.
2. Control unit (CU): The CU generates prefetched signal sequences timed by pulses derived
from a clock. The type of the signal sequence depends on the op-code (operation code) and
inputs fed from source external to the CPU. Such external inputs may be a request to interrupt
the program (an interrupt request) or a request to surrender the external bus (bus request). The
CU generates two types of signals:
A: Internal activation of the ALU and the opening/closing of data paths between registers.
B: External control signals for the memory and the I/O. These are sent either for activation of
data transfer or as response to interrupt or bus requests.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
AH AL
Instructions may address either 16-bit or 8-bit registers from the following list.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
AX BX CX DX
AH AL BH BL CH CL DH DL
Although all the data registers can be used interchangeably for many operations, each of the
registers is used for specific purposes.
1. Accumulator (AX): AX register is also called the Accumulator. It possesses some
features that the other data registers don't have. Many operations are also slightly more efficient
when performed with AX.
2. Base Register (BX): Like other data registers, the BX register can perform logical,
arithmetic, data movement, and it has special addressing abilities. Like SI, DI, and BP it can
hold memory address that points to another variable.
3. Counter Register (CX): acts as a counter for repeating or looping instructions. These
instructions automatically repeat and decrement CX and quit when it equals 0.
4. Data Register (DX): has a special role in multiply and divide operations e.g., when
multiplying, DX holds the high 16-bits of the product.
Index Registers: -
The Index register SI, DI are 16-bit registers (you cannot access the low or high bytes alone)
which can be used for temporary storage just like the general registers. However, their main
purpose is to hold the 'offset' of variables. The offset refers to the distance of a variable, label, or
instruction. These registers are used as 'Memory Pointers'. Each instruction must refer to an
index register when addressing locations in storage areas. Both the index registers can be used
for general storage but their real strength shows up when they are used during powerful string
handling functions.
1. Source Index (SI): is named after the 8088's string movement instructions, where the SI
register points to source string. SI usually contains an offset value from the DS register, but it
can address any variable.
2. Destination Index (DI): acts as the destination for 8088's string movement instructions. DI
usually contains an offset value from the ES register, but it can address any variable.
Pointer Registers: -
Any location used to hold the address of another locations said to act as a pointer to that
location. Pointer Registers are 16-bit registers as follows:
1. Base Pointer (BP): contains the offset from the SS register. It is used to access data
in the stack segment.
2. Stack Pointer (SP): The 'Stack' is a set of contiguous memory locations where items are
added or removed such that the latest arrival is processed first and the earliest arrival is
processed last, for which it is called a Last-In-First-Out (LIFO) stack. A stack is different from
any other memory location in that data are put on and taken from the top of the stack and is
reserved to store operand and instructions. The SP points to the top of the stack. In other words,
it holds the address of the item currently occupying the top. So the SP contains the offset address
of the top of the stack. The SS and SP registers combine to form the complete top-of-stack (actual)
address. 8088 can handle an unlimited number of stacks. Each one can be upto 64K in size and
located anywhere in the 8088’s one mega address space. The only restriction is that their 64K-
size limit and they must start at an address boundary that is an even multiple of 16 bytes.
3. Instruction Pointer (IP): essentially plays the role of a PC and its only one function is
containing the address of the next instruction to be executed. When an instruction is executed,
the IP is automatically incremented the number of times needed to point the next instruction.
However, its contents don't specify a physical memory address but an offset. CS and IP combine
to form the address of the next instruction to be executed. IP is physically part of the BIU and
not under direct control of the programmer as are the other pointer registers.
Flag Register: -
is a special 16-bit register in which individual bit positions are used as flags (a bit used to mark
the occurrence of a specific event) to show the status of the CPU or the results of
microoperations. Each relative bit position is labeled; other positions are undefined. A flag or
bit is set when it equals 1; it is clear/reset when it equals 0. There are two basic types of flags:
1. Control Flags
2. Status Flags
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
Control Flags can be set or reset directly by the programmer and are used to control the
operation of the processor. These are Trap (TF), Interrupt-enable (IF), and Direction (DF) flags.
While Status flags are the status indicators that reflect the outcome of microoperations
performed by the CPU. These are the Overflow (OF), Sign (SF), Zero (ZF), Auxiliary (AF),
Parity (PF), and Carry (CF) flags. The instruction set of a computer includes instructions, which
test these flags.
Bit Positions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - O D I T S Z - A - P - C
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
to the CPU. When MEMORY WRITE or I/O WRITE is active, data is output by the CPU i.e., the
control bus signals are defined from the CPU's point of view.
In a nutshell, the CPU manages the flow of data between itself, memory, and the I/O ports via
the address, data, and control buses. The control and address buses are output lines only (uni-
directional), but the data bus is bi-directional. This “Three-bus Architecture” is commonly
present in all microcomputer systems.
SEGMENTED ADDRESSING METHOD: -
Now we will see how the 8088/86 microprocessors manage to address up to 1MB of memory. An
“Address” is a part of instruction that specifies the location of an operand. Each stored
word/byte is allocated a number. By specifying this number of the particular word as a part of
instruction access is obtained to the operand stored within the word.
When the EU decodes an instruction, it determines the applicable addressing modes. Then it
manipulates each operand field. Since internal data bus is 16-bits wide, the EU handles
quantities up to 16-bits long. A 16-bit address allows unique identification of 216=65,536 or
64K-bytes locations so 4-digit hexadecimal number in the range 0000H can represent the 16-bit
address to FFFFH. An address within a segment is called a 'Segment/Base address'. So a
segment address, located within one of the segment registers (a unique feature of 8088), defines
the base address of any 64K-byte memory segment. The offset address selects a location within
the 64K-byte memory segment.
But since the 8088/86 can address 1MB of memory, the 16-bit must be augmented somehow to
make possible unique identification of 1million=106 byte locations. Here the BIU plays its role
in address computations. The BIU takes the relative/offset address derived by the EU and adds it
to the segment address. Before the addition, the contents of a segment register are shifted four
positions in the direction of the Most Significant Bit (MSB) i.e., to left (adding four zeros on the
right). Then the adder adds this new number to the second number (offset) to give a 20-bit
address, which is termed as the "Absolute/Real/Physical Address". This is the actual address of
location expressed in terms of machine code numbering system, and it is obtained by adding the
segment/base address to the offset/relative address. Addresses presented over the external buses
are always physical addresses.
The lowest possible physical address corresponds to an all-zero offset and thus coincides with
the segment address itself. Note that due to the 4-bit shift, segment addresses are always multiple
of 16. The highest possible physical address corresponds to the maximum possible value of the
offset i.e., segment address+64K. By loading different offset addresses in the segment registers,
any location in the 1MB address space may be accessed. Such an approach to administering a
large address space is known as "Relative Addressing or Segmented Addressing". In this
technique instruction are written so that they do not refer directly to absolute addresses in
memory; instead a base address is added to the address component (Offset address) of each
instruction when the program is loaded in order to create numbers of absolute locations. The
advantages of segmented addressing are as follows:
1. The greatest advantage is that reference offset/logical address only can be loaded and run
anywhere in memory i.e., it allows programs and data to be relocated in memory without
changing. A “relocatable program/data” coded in such a way that it can be stored and executed
in any part of the memory. This is because the segment addresses always range from 0000H to
FFFFH, independent of the offset addresses. Similarly a program can access large data
structures by setting the current segment address to a new block of memory. This enables a
programmer to write a program in several independent segments without having to consider the
absolute addresses required.
2. Secondly, one program can work on several sets of data. In a time-sharing system, several
users share a CPU. Because segmentation keeps data and programs separate from one another,
so it is easy to switch from one user's program to another user's program i.e., the program
segments can be written independently by different programmers each using relative addresses.
3. This scheme requires only a 16-bit number to represent the contents of a segment
register and only a 16-bit offset to access any memory location. This means that the CPU has to
handle and store only 16-bit numbers instead of 20-bit numbers.
COMPARISON OF iAPX 8088 & iAPX8086: -
The Intel 8008 is considered as the first microprocessor, which had an address space of
16Kbytes and only two addressing modes. 8080, 8085, 8088, and 8086 microprocessors followed
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
it. In 1978, Intel released the 8086 and a year later, the 8088. Both can address a 1-M bytes (8-
bit wide) or a 512-K word (16-bit wide) memory. The 8086 is more powerful than 8088, with
exactly the same 16-bit instruction set and memory addressing, but with greater processing
speed. However, the differences between 8088 and 8086 are:
1. Firstly in 8088, the BIU data bus path size is 8-bit data bus versus the 16-bit of 8086. So the
8088 requires two memory read cycles to input the same information that the 8086 inputs in
one memory read cycle. A 'Memory Cycle' is defined, as the time required accessing the
memory read or writing a byte. These additional cycles slow down 8088 (as they consume a
huge amount of processing time), making it less efficient than 8086.
2. Because of its wider external data bus 8086 (16-bit microprocessor) has higher processing
speed than the corresponding 8088 (8/16-bit microprocessor). Although the cost difference
between two devices is not very large.
3. One more difference is that the 8088-instruction queue (IQ) is 4-bytes long while 8086-
instruction queue is 6-bytes long.
4. Another difference is that as 8086 was introduced after 8088 so both are not pin compatible.
Their pin assignments are not the same.
The important point to note, however, is that programs written for the 8086 can be run on the
8088 without any changes. Because the EU is the same for each processor, the instruction sets
are exactly the same for each. More advanced microprocessors seem to appear each year, but
the manufacturers such as Motorola and Intel have made a conscious effort to make the new
chips downwardly compatible. This makes the new CPU’s much more attractive to the system
designers. This means that programs written for the older processors (such as 8088/86) will run
on the newer ones, such as 80286, 80386, 80486, and so on but not necessarily the other way
around.
COMPUTER INSTRUCTIONS: -
Computer instructions are made up of two parts. The first part is called the “Operation Code or
op-code” for short, which specifies the operation to be performed. The second part called the
“Operand” is the item in an operation from which the result is obtained by means of defined
actions i.e., it indicates the source and/or destination of the data acted on by the op-code. As an
example, the instruction INC AX is made up of the op-code INC (increment) and the operand AX
(accumulator register). In this case AX is the source and destination of the data. These are the
limitations on the types of operands:
1. CS and IP may never be destination operands.
2. Immediate data and segment registers may not be moved to segment registers.
3. The source and destination operands must be the same size.
4. If the source is immediate data, it must not exceed 255 (FFH) for an 8-bit destination or
65,535 (FFFFH) for a 16-bit destination. The list of the all op-codes the computer can
execute is called “Instruction Set or Order Code”. Generally it is the set of symbols and
characters forming the rules of a particular computer code or programming language.
The instruction set of a particular microprocessor specifies the register-transfer operations and
control decisions that are available in the microcomputer system. When an instruction is stored
in memory it is the binary code representing (that instruction) that is actually stored. For the
instruction INC AX the single byte (8-bits) 01000000 (40H or 64D) is stored. Anyhow, most 8086
instructions require more than one byte. Some instructions will require as many as seven bytes.
The best way to appreciate the instruction set is to write programs that perform meaningful data
processing tasks. The power of an instruction set is usually judged from the number of
instructions needed to perform a specific complex task. Fewer instructions mean generally less
memory space for the program and shorter task execution times. Hence, the instruction set is
considered more powerful. Instruction sets may not only differ on the type of operations, but also
the data types on which instruction are performed. Generally, the instruction sets are different
for different microprocessors, but there are certain basic instructions that are included in all
microprocessors.
SOFTWARE: THE Intel 8086/88 INSTRUCTIONS SET: -
Writing software means telling the CPU what operations to perform as well as specifying the
order of execution. Even though external data bus of 8088 is only 8-bits wide but it is only for
wiring support chips and laying out the PC board. But the instruction set of the 8088 has all the
features of the older 8-bit CPU’s as well as whole collection of powerful new 16-bits instructions.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
The 8088 can understand over 95 separate instructions and have 24 ways to generate an address.
Generally microprocessor instructions may be classified into three distinct types.
1. Data Transfer Instructions are concerned with operations which entail the movement of data
between registers in the processor and between registers and memory locations (words)
without changing the binary information content.
2. Data Manipulation Instructions perform arithmetic, logical, and shift operations on data
stored in registers or memory locations. They also set, clear, or complement status or flag
bits.
3. Control Instructions provide means for controlling the program and the state of the CPU.
These instructions provide decision-making capabilities and change the path taken by the
program while execution.
Last two types may be classified further into categories as follows:
1. Data Manipulation Instructions.
A: Arithmetic Instructions. B: Logical Instructions.
C: Shift/Rotate Instructions. D: Bit manipulation Instructions.
E: String processing Instructions.
2. Control Instructions.
A: Program control Instructions. B: Processor/Machine control Instructions.
1. Data Transfer Instructions:-
Microprocessors spend most of their time accessing memory locations and moving data from
place to place. So these instructions transfer one byte/word of data from one location to another.
e.g., MOV LOC1, LOC2 move data form LOC2 to LOC1
Data transfer instructions include XCHG, XLAT, PUSH, POP, IN, OUT, LDS, LES, LEA,
PUSHF, POPF, LAHF, SAHF etc.
2. Data Manipulation Instructions:-
A: Arithmetic Instructions: give the 8088 its computational capabilities. The 8088 can directly
do ASCII arithmetic. Decimal data can be coded into hex in two ways-either as packed (standard
BCD) or unpacked (ASCII) numbers. Secondly 8088 can do multiplication and division of 8- or
16-bit numbers with a single instruction. And can handle signed or unsigned numbers. Unsigned
numbers are scalar quantities. An 8-bit unsigned number can be as large as 255 and a 16-bit
unsigned number can go upto 65,535. These numbers only represent magnitudes; they are not
positive or negative. While signed numbers (also called integers) are vector quantities. Because
in these MSB is used to indicate the sign (direction). If the sign bit is clear (0) the number is
positive and if it is set (1) the number is negative. So for 8-bit numbers range is –128 to +127
and for 16-bit numbers range is –32,768 to +32767.Examples are
ADD LOC2, LOC1 add contents of LOC1 and LOC2
INC LOC increment the contents of location LOC by 1
Other arithmetic instructions are ADC, AAA, DAA, SUB, SBB, DEC, NEG, CMP, AAS, DAS,
MUL, IMUL, AAM, DIV, IDIV, AAD, CBW, CWD etc.
B: Logical Instructions: are used for doing logical operations e.g.,
AND LOC2, LOC1 AND each bit in both bytes/words
NOT LOC Invert each bit of a byte/word
There are five logic instructions available with the 8086/88 microprocessor; NOT, AND, OR,
XOR, TEST. TEST is the most useful instruction. Each function is performed bit by bit between
the source and destination operands. These instructions are all performed in the ALU and affect
all the flags.
C: Shift and Rotate Instructions: shifts or rotate the bits of an operand in either direction. The
rotated quantity can be an 8/16-bit CPU register or memory location. The main difference
between a shift and rotate is that the shifted bits 'fall off' the end of the register, whereas the
rotated bits 'wrap around' i.e., in rotate instructions, bits shifted are not lost, instead, they
reenter from the other side. Within the shift group of instructions there are both arithmetic (SAL
and SAR) and logical (SHL and SHR) shift instructions. In shift right operations, there are two
types:
1. Logical, where 0s enter from the left.
2. Arithmetic, where the sign bit preserves it by reentering.
In all these instructions the carry flag is involved. These are also used in doing multiplication
and division. Fig shows ROL, ROR, RCL, RCR are the rotate instructions.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
D: Bit Manipulation Instructions: are used for testing, setting, or clearing a bit within a byte/
word). Such instructions specify both the addresses of the location and the desired bit position.
Logical, shift and rotate instructions are sometimes referred to as “Bit manipulation
instructions”.
E: String Processing Instructions: 8086/88 has several instructions for moving large blocks of
data or strings (a set of consecutive characters or digits). These instructions have a special
addressing mode of their own, for all these instructions the source is DS: SI and the destination
is ES: DI. Nothing like these instructions had ever been available before e.g.,
MOVS LOC2, LOC1 move string form LOC1 to LOC2.
MOVSB/MOVSW move byte or word from one string to another.
CMPS, LODS, STOS, SCAS, REP, REPE, PEPZ, REPNE, REPNZ are important string
instructions.
3. Control Instructions: -
The stored program computer repeatedly follows the sequence: fetches the instruction whose
address is in IP, increments IP, and executes the instruction i.e., all programs are executed
sequentially. However, sometimes it is necessary to transfer control to an address that is not the
next instruction in sequence.
Examples are instructions that must be executed repeatedly, groups of instructions that are
shared through out a program, conditional transfer based on the state of the flags, and software
interrupts. Control instructions may be conditional or unconditional. A 'Conditional Control
Instruction' causes a jump/branch out if normal program sequence only when a specified
condition is detected. Whereas, an 'Unconditional control Instruction' causes a branch
unconditionally. In short, these instructions allow program control to be transferred to a new
non-sequential address.
A: Program Control Instructions: The branch out of normal program sequence is
accomplished by changing the program counter (PC) since it contains the address of the next
instruction to be executed. Therefore, program control instructions change the contents of the
PC which in turn transfers control to another part of a program e.g.,
JMP LOC Go to specified address
The 8088 has a wide range of JUMP commands based on various conditional tests e.g.,
Jcond LOC Jump if condition is satisfied
One common programming problem is to setup a group of instructions that must be executed
several times. One of the CPU registers is loaded with the loop count and this register is
decremented by 1 at the end of each loop. A JNZ (jump if not zero) instruction transfers control
back to the start of the loop if the counter register is not zero. The 8088 instructions are
designed exactly for this application e.g.,
LOOP LOC Loop until CX=0
JCXZ LOC Jump to LOC if CX=0
Important instructions are CALL, RET, LOOP, LOOPE/LOOPZ, LOOPNE/LOOPNZ etc. All
loop instructions repeat until CX = 0. This means that the loop will be repeated 65,536 times if
CX= 0 initially.
B: Processor/Machine Control Instructions: affect the operation of the processor itself and
include instructions concerned with setting and clearing flags that are used during normal
program operations. e.g., STC set the carry flag.
WAIT wait until TEST pin active.
NOP do absolutely nothing (no operation).
Other significant instructions are CMC, CLI, STI, CLD, STD, CLC, INT, INTR, INTO, ESC,
LOCK, HLT etc. The instructions HLT, WAIT, LOCK, ESC are specifically designed to use with
external devices like coprocessors.
ADDRESSING MODES: -
Computer instructions are made up of an op-code and zero, one, or two operands. Sometimes
instructions with no operands are called 'zero-address instructions'. Those with one operand are
called 'one-address instructions', and so on. Usually, microprocessors specify one or two
operands. The valid operands depend on the internal organization of the microprocessor and the
different ways in which the microprocessor generates these operand addresses are called the
'Addressing Modes' which may be one of three basic types: register, immediate, or memory. The
8086 has nine different addressing modes.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
Intel addressing modes, in fact, are some of the most complex available in any assembly
language. However, these modes give the experienced programmer flexibility for writing
programs that are more efficient with respect to the number of instructions and execution time.
The data addressing modes are:
N.B: Because MOV instruction is common and flexible, it provides a basis for explanation of the
data addressing modes.
Immediate Addressing Mode: Instructions that use this mode get their data as part of the
instruction and it is commonly used to load a register or memory location with some initial data.
In this mode the operand is specified in the instruction itself as the term 'immediate' implies that
the data immediately follow the hexadecimal op-code in the memory. An immediate operand is a
constant expression, such as a number, a character, or an arithmetic expression. It transfers the
source-immediate byte/word into the destination register or memory location e.g.,
MOV AX, 1000H
Register Addressing Mode: In this mode the operands are the CPU registers which reside within
the CPU. In general, this mode is the most efficient because register are part of the CPU and no
memory access is required. The microprocessor contains the following 16-bit registers; AX, BX,
CX, DX, SP, BP, SP, and DI and 8-bit registers AH, AL, BH, BL, CH, CL, DH, and DL. Any
registers may be used as source operand, and any registers except CS and IP may be used
destination operands. For example,
MOV AX, BX
Another point must be again remembered that registers being used must be of the same size.
Because mixing is not allowed by the microprocessor and results in an error when assembled.
These instructions are wrong:
MOV BL, DX Not allowed (mixed sizes)
MOV ES, DS Not allowed (segment to segment)
MOV CS, AX Not allowed (CS cannot be the destination register)
Direct Addressing Mode: In this mode the memory address is supplied directly as part of the
instruction. A direct operand refers to the contents of memory at an address implied by the name
of a variable. In 8-bit microprocessors as 8088 with 16-bit addresses, a direct instruction
consists of 3 bytes. e.g.,
MOV AH, MEMBDS copies the 8-bits of data segment location MEMBDS into AH
MOV AX, NUMBER copies the 16-bits of data segment location NUMBER into AX
Register Indirect Addressing Mode: allows data to be addressed at any memory location
through an offset address held in any of the following registers: BP, BX, SI, DI. In this mode
memory address (EA) is supplied in a pointer or index register e.g.,
MOV AX,[SI]
MOV AX,[BX]
Indirect Memory Access Addressing Modes: -
The direct addressing mode is useful for infrequent memory accesses. Anyhow, when a memory
location must be read/written to several times, the repeated fetching of the two- byte logical
addresses makes this mode inefficient.
The Relative/Indirect Memory Access Addressing Modes solve this problem by storing the
memory addresses in a pointer or index registers. A relative-mode instruction is a 2-byte
instruction, with the second byte specifying a signed number in the range between –128 and
+127. It is accomplished by representing the number in sign-2's complement form. This 2's
complement displacement can be added to the pointer or index registers to offset the location
pointed at.
Hence indirect addressing is a technique in which the address part of an instruction refers to
another location which contains another address. This further address may specify an operand
or yet another address. This technique is also called “Multi-level Addressing”
Indexed Addressing Mode: In it memory address (EA) is the sum of the index register plus a
displacement within instruction e.g., MOV AX,[SI+6]
In general, a displacement can be added to a base register and the result added to an index
register. The resulting address is often referred to as the 'Direct/Effective Address' (EA). This
address is computed by the information provided in the instruction i.e., the computation has to
take place before the instruction can be executed. It is the address of the operand or the address
where control branches in response to a control instruction. In a direct-mode instruction the
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
effective address is equal to the address part of the instruction. The displacement is limited to a
single byte, allowing the EA to be varied +127 bytes (7FH) to –128 (80H) from the base pointer.
Based Addressing Mode: In it memory address (EA) is the sum of the BX or BP registers plus a
displacement within instruction e.g., MOV AX, [BP+6]
Based and Indexed Mode: In it memory address (EA) is the sum of the index register and a base
register e.g., MOV DX, [BX+SI]
Based and Indexed with displacement Mode: In it memory address (EA) is the sum of an index
register, a base register, and displacement within instruction e.g., MOV AX, [BX+SI+6]
String Addressing Mode: Because of their importance, 8086/88 has several instructions
designed specifically for handling strings of characters. These instructions have a special
addressing mode of their own, for all these instructions the memory source is DS: SI and the
memory destination is ES: DI. For example
MOVSB/MOVSW move byte or word from one string to another.
Remember that two base registers or index registers cannot be combined. Finally, note that the
default memory segments for all the indirect addressing modes are the stack segment when BP is
involved, and the data segment when register BX, SI, or DI is involved. The most powerful
feature of the indirect addressing modes is that the memory address can be changed based on
program conditions.
8088 CPU PIN DESCRIPTION: -
The 8088 microprocessor is a VLSI (Very Large Scale Integration) device that contains
thousands of gates in a single chip. It is housed in a 600-mil wide, 40-pin dual-in-line package
(abbreviated DIP, an IC packaged so that external connections can be made through two
parallel rows at right angles to the edges of the package). Many of these pins are time
multiplexed, providing two separate processor functions. Some pins are devoted to support
coprocessors. It was difficult to provide access to all the functions of the microprocessor with in
a single chip. Actually the 8088 microprocessor has a 20-bit address bus, an 8-bit data bus,
three power pins, and seventeen pins devoted to miscellaneous control and timing functions.
The Intel (the leading microprocessor manufacturer) employed a design technique called “Time
Division/Sharing Multiplexing”, a system whereby a number of terminal devices are connected
to the same communication channel and each occupying the channel for the data transmission
for short periods at regular intervals. Each unit transmits data by the use of timesharing
techniques such that all units appear to transmit simultaneously over one channel. In this way
one circuit pin has more than one function e.g., the 8088’s pins, labeled A16/S3 to A19/S6 are
the address lines during the state T1 clock state, and become status indicators during the T2-T4
states. A special de-multiplexing circuit (circuit used to separate the signals that were combined
for transmission by a compatible multi-plexer) is required to separate these lines.
Another attractive feature of the 8088 is its ability to operate in two modes, named the
“Minimum Mode” and the “Maximum Mode. The minimum mode is designed for simple single
processor systems on one printed circuit board (PCB). Whereas the maximum mode is designed
for more complex systems with separate I/O (short for input/output) and memory boards. This
mode also supports coprocessors such as the 8087 NDP (Numeric Data Processor) and 8089
IOP (Input Output Processor).
ADDRESS BUS (AD0-AD7, A8-A15, A16/S3-A19/S6:-)
These 20 pins correspond to the microprocessor’s 20-bit address bus and allow accessing
220=1,048,576 unique memory locations. Because the 8088 have an 8-bit external data bus,
there is no need to multiplex the A8-A15 address lines. Thus these pins carry information
throughout the bus cycle and need not be latched.
The address pins on the 8088 are functionally divided into three groups; AD0-AD7, A8-A15,
A16-A19. The reason for this breaking is that not all of them carry the address all the time.
The first group, AD0-AD7, is the most versatile. During the first part of an instruction cycle, the
8088 puts the lower 8-bits on these pins. During the second part of the instruction cycle, CPU
removes the address from these lines and floats them (tri-stated) to get them ready for their next
job. When the 8088 reaches the third part of its instruction cycle, it uses these pins as the data
lines. During this stage of the instruction cycle these pins become bi-directional.
The second group of the address pins, A8-A15, area set of plain vanilla address pins and the
potion of the address they carry stays valid for the entire instruction cycle.
The final address pins, A16-A19 make the 8088 a 16-bit CPU since they are the addresses from
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
10000H (65,536D), to FFFFFH (1,048,575D). These lines carry valid address data at the same
time as the first group of address lines. Then carry status signals which indicate the address
segment currently in use (S3 & S4), the state of the interrupt enable flag (S5), and a flag to
indicate that the 8088 has control of the bus, (S6).
DATA BUS (AD0-AD7): -
These eight pins form the microprocessor’s bi-directional data buses. So these pins and A16/S3-
A19/S6 only need to be multiplexed. Data is transferred only on the AD0-AD7 address/data lines.
ADDRESS LATCH ENABLE (ALE): -
This output signal separates the low order address and data. Since these signals are multiplexed
on the same pins, an external signal is required to determine what kind of information is
currently on the pins. When ALE becomes active (goes HIGH), the 8088 is telling you that the
entire 20-bit address is on the bus. So this output is used to de-multiplex the address, data, and
status lines on AD0-AD7 and A16/S-A19/S6.
INPUT/OUTPUT MEMORY (IO/M): -
The 8086 microprocessor’s M/IO becomes IO/M on the 8088. The 8088/86 does not output
separate memory and I/O read and write signals. Instead, this pin indicates that the address bus
contains either a memory or an I/O port address. This line goes to HIGH to indicate that the
CPU is talking to an I/O port and LOW when the CPU wants to deal with system memory.
READ (RD): -
Read is to obtain data from one form of store (e.g., magnetic disk) and transfer it to another (e.g.,
memory of the microprocessor). It is an active low output that indicates the 8088 wants to read
data either from memory or an I/O port. It can be combined with IO/M to form MEMR and IOR
control signals. RD will remain high until the address is removed from the bus. AD0-AD7 first
carry the address, then float, and then function as the data bus. So the RD does not become
active until the bus floats. Consequently, when the RD is active, data appears on the bus.
WRITE (WR): -
Write is to transcribe (retype) data on to a form of store from another form of store (e.g.,
transcribing data on to a magnetic disk from the microprocessor’s main memory). This signal is
the counterpart of RD and indicates that data is to flow from the microprocessor to memory or
to an I/O device.
CLOCK (CLK): -
The CPU’s heartbeat is the system clock and it is fed to the CLK input. Clock provides
accurately timed pulses at fixed intervals to monitor, measure, or synchronize other units
operating within the system. It supervises operations to detect looping and similar error
conditions, and also provides time in hours and minutes for maintaining an operation log (a
record of series of events). Without the clock signal, there would be chaos.
Secondly internal registers are made from dynamic memory cells (regenerative storage units in
which signals representing data has to be constantly regenerated so that information can be
retained as long as required) that require periodic refreshing or they will lose data. The clock
signal provides this refresh. Thus the clock must never be stopped. This means the minimum
clock speed for any 8088 is 2 MHz but the maximum rate depends on the version of the 8088
being used. The signal clock must be asymmetrical (33% duty cycle), with steep rise and fall
times. Intel makes the 8284; a clock generator circuit that generates clock pulses perfectly
tailored to the 8088. It also provides fully synchronized startup and manual reset as well.
STATUS (A16/S3-A19/S6): -
These five status signals designed primarily for diagnostic testing purposes, as their definitions
in the table given below indicate. It is possible to decode S3 and S4 to provide four separate
1MB-address spaces for the extra, data, code, and stack memory segments.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
CPU CONTENT
FLAGS Clear
IP 0000H
CS FFFFH
DS 0000H
SS 0000H
ES 0000H
IQ Empty
Hence whenever the 8086/88 is reset, it begins executing instructions at memory locations
FFFF0H and disables interrupts by clearing the IF flag/bit. RESET is normally used when first
starting a computer or after a system crash (failure). It is also very handy when you are trying
out new code, since software in the development stage produces crashes more often than results.
TEST: -
The TEST input is a way of stopping the 8088 until it is started up again by some external event.
This input is used together with the WAIT instruction. If the TEST input is HIGH when the WAIT
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
instruction is encountered, this WAIT instruction functions as NOP instruction; execution of the
program is suspended and the computer enters an “Idle Mode”, the mode during which the
system remains inactive even though switched on and otherwise in an operable condition. Only
when the TEST returns LOW will execution resume (with the instruction following WAIT
instruction). Normally, this input is driven by 8087 coprocessor. This prevents the CPU from
accessing a memory result before the coprocessor has finished its calculations.
READY: -
The READY input signal is used by either memory or I/O to let the 8088 know when the
requested data operation is finished. When the data transfer is completed, the external device
can let the 8088 know it is done by putting a high on the READY line. The most common use for
the READY line is to slow the 8088 down when it is dealing with slow-memory external devices
that can not handle data at CPU speed. It is employed to insert wait states into the machine
cycle. If it is found LOW (not ready), the microprocessor enters a wait state and remains idle.
INTERRUPTS (INTR, NMI, INTA): -
The INTR pin, the Interrupt Request input gives you way to the 8088’s powerful external
interrupt servicing routines. The 8088 can handle 256 vectored, prioritized levels of interrupt
and it looks at INTR at the end of each instruction cycle. If the CPU sees that the line has been
made active (HIGH) by an external device it will jump/vector to the subroutine whose address
has been stored in memory in a lookup table.
INTR and NMI are hard-wired interrupt requests, which function exactly as software interrupts.
The INTR input can be masked (Masking is the technique of devising a bit pattern called a Mask
to alter or isolate specific bit positions present in another bit pattern) by resetting the IF control
flag (CLI) i.e., clearing this bit blocks all interrupts on INTR effectively masking this input.
The INTA (Interrupt Acknowledge) line is an output that becomes active (LOW) when an
external device makes an interrupt request by putting a HIGH on the INTR pin. Whenever the
8088 receives this request, it waits until the current instruction cycle is ended and then puts a
LOW pulse on the INTA line for two consecutive cycles referred to as “interrupt acknowledge
cycles”.
NMI is the “Non-Maskable Interrupt” also known as the “disaster Line” that will always be
serviced. It is called this because, since there is no way for it to be disabled by software, most
systems reserve it to indicate that some sort of catastrophic events such as power failure or
memory errors, is going to happen. To make the input more responsive, the NMI input is edge,
rather than level-triggered. This means that the 8088 will react during the low to high transition
of the NMI line instead of waiting for it to reach a high. Once the line has been activated, the
8088 will finish executing the current instruction and then jump to the NMI handling routine
whose address has been stored in the appropriate place in the lookup table.
HOLD, HOLD ACKNOWLEDGE (HOLD, HLDA): -
HOLD is useful for multiprocessor systems since it is a perfect signal for avoiding bus
contention. The most common use for HOLD is doing DMA, (Direct Memory Access). DMA is a
powerful way to get things done without having to involve the 8088. One of the best examples of
DMA is dynamic refresh. If we let the 8088 handle it, the processor’s built-in overhead (due to
instruction fetch and execute times) will really stretch out the operation. HOLD is an active high
input that causes the microprocessor to open circuit all of its bus lines. This effectively
disconnects the CPU from its memory and I/O, allowing a second processor to access these units.
HLDA is the output used by the 8088 to let external devices that it has removed itself from the
bus and has floated all the lines. If a device like Intel’s 8237 DMA Controller is used, then
HLDA acknowledges the DMA request to the DMA Controller.
POWER & GROUND (VCC & GND): -
A 5MHz 8088 microprocessor requires +5.0-V +/-10% and draws 340-mA maximum and its
power dissipation are a 1.7-W. The 8088/86 require a single +5.0-V power supply and have two
ground pins (#1 & #20). The GND connection is the return for the power supply (VCC ). Both
GND pins must be connected to ground for proper operation. Remember both GND pins are not
electrically connected in the IC. Making the assumption that they are tied together and letting
one float will guarantee flakey (erroneous) operation at best and foul smelling smoke at worst.
STATUS SIGNAL OUTPUT (SSO): -
This is the only new signal on the 8088, which takes place of BHE/S7 on the 8086. This signal
will give an up to minute report of what the 8088 is currently doing on the bus. This signal can
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#02 Microprocessor Architecture Compiled by Sajid Iqbal (B.Sc. Elect)
be combined with DT/R and IO/M to encode the current bus cycle. As fig below shows this
information can be used for diagnostic testing purposes.
January 2001 It is not whether you win or lose, it is how you play the game.
Chap#03 Microprocessor Programming Compiled By Sajid Iqbal (B.Sc. Elect)
PROGRAM: -
All computers must be programmed to perform even the most elementary tasks. A set of
instructions (statements) given to the computer to perform a certain job is called a
“Computer Program”. These computer programs guide the computer, through orderly
set of actions specified by the people called “Computer Programmers”.
Since a computer cannot reason, but is entirely dependent on instructions supplied to it
by its all too users. So it cannot perform any task adequately unless the problem it is
required to solve has been specified correctly in every detail and the instructions it is
asked to obey define in complete detail each step of the solution.
PROGRAM STATEMENT: -
Program statement is a single complete meaningful instruction containing some
constants, operators, variables, and keywords (informative words which have special
meanings to a compiler and cannot be used as data names).
PROGRAMMING LANGUAGES: -
In order to communicate with each other, men use language; in the same way, languages
are used to communicate instructions and commands to a computer i.e., languages are
the medium by which man communicates problems to the computer. So language is a set
of words, symbols, characters etc., for communication. Languages used for writing
computer programs are called ”Programming Languages”.
The choice of programming languages will depend upon the complexity of the problem,
and the capacity and resources of the computer to be used.
There are three levels of programming languages:
1. Low-level Languages (Machine Languages).
2. Symbolic Languages (Assembly Languages).
3. High-level Languages.
1. LOW-LEVEL LANGUAGES (MACHINE LANGUAGES): -
Low-level languages (Machine languages) are the only languages that a computer can
understand. These instructions are written in the form of binary strings of 1’s and 0’s
which can be immediately obeyed by a computer without translation. In a strict sense, in
a low-level language each instruction has a single corresponding machine code
equivalent.
The programs written in these languages are fast in execution. On the other hand it is
difficult to learn machine languages because it requires detailed knowledge of hardware
(all the electronic and mechanical units which together form a computer system).
Machine language programming is very tedious because you must determine the hex
code for each instruction used. With over 100 mnemonics and 3800 different forms of the
8086 instructions, this process is time consuming and error prone. There is no single
machine language because each computer can understand only its own machine
language. So machine languages are machine (computer) dependent i.e., a particular
machine language can be used only on one type of computer.
2. SYMBOLIC LANGUAGES (ASSEMBLY LANGUAGES): -
Assembly language is a set of instructions for a particular microprocessor. It was
developed in 1950s. It provides a direct correspondence between symbolic operation
codes and machine language, for which it is termed “Symbolic language”. Like machine
languages each microprocessor or microprocessor family has a different Assembly
language, because the design of the microprocessor influences the instructions it can
execute.
Assembly language uses two-, three-, or four letters “mnemonics” to represent each
instruction type. A mnemonic is a short alphabetic code that helps us to remember a CPU
instruction. The letters in mnemonics are usually initials or shortened forms of the
English words for the operation performed by the instruction, e.g., the mnemonics for
subtract is SUB, the mnemonic for multiply is MUL etc.
Assembly language statements are usually written in standard form consisting of four
fields as shown below:
Label field is the first in each Assembly language statement (i.e., the left-hand column of
the statement) and it is not essential to have an entry in this field for each instruction.
Labels are followed by a colon (:). An entry here is treated as a name, which can used to
identify the specific line of the program and hence its memory address. Usually labels are
used as addresses within program control instructions (JUMP, BRANCH etc.) to cause
control to pass to an instruction bearing a specific label.
Op-code field contains the mnemonics for the instructions to be performed. Op-code is an
acronym for “Operation Code”.
The Operand field contains data, memory address (A binary numeric code given to a
memory location in order that location can be selected for reading or writing under
program control), port address, or the registers (special storage locations of the
microprocessor concerned) on which operations are to be performed. An instruction may
contain zero, one, or two operands. The choice of the operand is usually determined by
the “Addressing Mode”. The addressing mode tells the Assembler where to find the data
in each operand e.g.,
PUSH AX ; one register
MOV AX, BX ; two registers
ADD BX, 1000H ; register, immediate value
The final field the Comment field starts with a semicolon (;). Comments, annotation or
narrative are written notes which are included in the coding of a program in order to
clarify operations but have no effect on the program itself, i.e., are not translated into
machine language.
3. HIGH-LEVEL LANGUAGES: -
In contrast to a low-level language in a high-level language each instruction has several
corresponding machine code instructions. These languages are very close to human
languages, i.e.; these languages provide us more familiar notation rather than machine
codes of the computer e.g., mathematical notation in FORTRAN and English in COBOL
etc. Each language has its own rules (which govern the structure of the language
statements) for writing source programs/codes. These rules are called “Syntax” of the
language.
Features which high-level languages have in common are the fact that they are
“problem-oriented” rather than “machine-oriented” and also myriad of compilers are
available for converting the high-level language programs into the machine codes of
different types of computers. Programs can be written faster in high-level languages than
their counterparts (either low-level languages or Assembly languages), because they
work with larger building blocks. Whereas these program always almost execute more
slowly and require more memory than programs written in their counterparts. Unlike
Assembly and machine languages high-level languages are designed to keep them as
much computer independent as possible. A high-level language program is generally
“portable”, i.e.; it may be executed on any computer with some minor amendment to
cater for any differences of configuration or idiosyncrasies of translators. Obviously
high-level languages are more desirable from programmer’s standpoint than either
machine languages or Assembly languages. The important high-level languages are:
FORTRAN: is an acronym for FORmula TRANslation. It is a high-level language for
scientific and mathematical use; introduced in 1957.
COBOL: is an acronym for COmmon Business Oriented Language was developed in
1959. It is primarily used for commercial applications that require precise and efficient
manipulations of large amount of data. Today more than half of all business software (in
contrast to hardware, software are programs which can be used on a particular
computer) is still programmed in COBOL.
BASIC: is an abbreviation for Beginners All-purpose Symbolic Instruction Code. It was
introduced in 1965 and originally designed for developing programs in
This MOV instruction will copy the contents (data) of 16-bit AX register to the 16-bit BX
register.
ASSEMBLY LANGUAGE STATEMENTS: -
Adding integer 5 to integer 2.
MOV AH, O5H
ADD AH, O2H
INSTRUCTION CLASSIFICATION: -
As we have discussed major types of instructions in Chapter#02 (Microprocessor
Architecture), so now will confine our discussion only to classify the instructions
mentioned in our curriculum (course):
DATA TRANSFER INSTRUCTIONS: - MOV, XCHG, PUSH, POP
ARITHMETIC INSTRUCTIONS: - ADD, SUB, INC, DEC, CMP
LOGICAL INSTRUCTIONS: - NOT, AND, OR, XOR, TEST
SHIFT/ROTATE INSTRUCTIONS: - ROL, SAL
PROGRAM CONTROL INSTRUCTIONS: - JMP, JNC
STRING INSTRUCTIONS: - REP
PROCESSOR/MACHINE CONTROL INSTRUCTIONS: - ESC, HLT, STD, CLC
PROGRAMMING: -
Programming is the process by which a set of instructions (program) is produced for a
computer to make it perform a specified activity. Before writing a program for a
particular problem, it is essential to have a thorough understanding of the problem and a
carefully planned approach to solving the problem. It is of paramount importance to
clearly isolate every single step and every single condition that can possibly occur during
the solving the problem. For writing a program the main steps are:
1_ Understand the problem, and plan the solution.
2_ Prepare a flowchart, Pseudocode, or Decision Table of the problem.
3_ Prepare the instructions in coded form.
4_ Test the program until it is performing
5_ Prepare detailed documentation of the program and instructions on its operation.
Understanding the problem is of fundamental importance. Mostly the programmer works
from a detailed program specification (algorithm). This algorithm includes descriptions
of all input to the program, the processing required, and details of all output from the
program. i.e., once a problem is properly analyzed, the next step is to write a sequence of
actions involved in the solution of the problem, called an “Algorithm”.
Therefore an algorithm is a procedure for solving a problem in terms of the actions to be
executed, and the order in which these actions are to be executed. Specifying the order in
which statements are to be executed in a program is called “Program Control”.
“Pseudocode” is an artificial and informal language that helps programmers develops
algorithms. Pseudocode is similar to everyday English language; it is convenient and
user-friendly although it is not an actual programming language. Pseudocode helps the
programmer think out a program before writing it in a programming language.
Pseudocode instruction consists purely of characters arranged in symbolic form. Then a
carefully prepared pseudocode program may be easily converted to a corresponding
programming language simply by replacing pseudocode instructions with their source
language equivalents.
The next step is “Flowcharting” the problem A “Flowchart” or “Flow-diagram or Logic
diagram“ is a graphical representation of an algorithm and “Flowcharting” is the
technique of drawing the flowcharts.
The object of flowcharting is to show the logical relationship between the various parts
of the program. The flowchart is very useful in understanding the flow of logic (program
control). It is particularly important to maintain an overall flowchart when
“Segmentation” (programming technique in which a lengthy and complex problem is
divided into a series of shorter units called “Segments, or Chapters”) takes place to
ensure that all parts of the problem are taken careof.
In a nutshell, a flowchart is very useful in planning and designing a complex problem. A
flowchart is then used as the basis for writing a program. A flowchart is normally
of using a computer to operate on the data and code of a different computer is called
“Emulation”. An emulator is a mixture of hardware and software. It is not just a simple
debugger but it takes a snapshot (image) of the contents of registers, address/data buses
and status flags/bits as the program runs. The emulator stores this “Trace Data” as it is
termed, in memory (RAM). Another powerful feature is its ability to use either system
memory or the memory on the prototype for the program you are debugging.
BASIC LOGIC STRUCTURES: -
Normally, statements in a program are executed one after the other in the order in which
they are written i.e., computer executes a series of instructions stored in successive
locations of memory. This is called “Sequential Execution”. There are many instructions
called “Branch or Jump or Control Transfer instructions” e.g., the famous goto
instruction, which enable the programmer to specify that the next statement to be
executed may be other than the next one in sequence. This is termed as “Program
Control Transfer”. During the 1960s, it became evident that the indiscriminate use of
transfer of control (using goto instruction) was the root of much difficulty experienced by
the programmers. The goto statement was blamed that allows the programmer to specify
a transfer of control to one of very wide range of possible destinations in a program. So
the notion of “goto elimination” became synonymous with “Structured Programming”.
Structured programming is also called “Modular Programming”. The basis for modular
programming methodology is to divide each program at the planning stage into a number
of logical parts called “Modules”, each described in increasing detail until the final
stage of coding is reached. Each module corresponds to a particular program function
and can be treated as a separate entity. Each module is relatively simple to specify, write
and test. Changing requirements can be met by simply changing existing modules or
adding new modules.
This technique eliminates the use of two many branch/jump instructions, thus simplifies
the task of developing and maintaining large programs. Consequently it reduced
development time, more frequent on-time delivery of systems, and more frequent within
budget completion of software projects. The golden key to these successes is that
structured programs are clearer, easier to debug and modify, and more likely to be bug
free in the first place. It is also known as “Top Down programming”.
The real power of a computer lies in its ability to choose between two or more sequences
of operations depending upon some condition (Selection Structures, e.g., if-then
operation), or repeat a sequence of instructions as long as some condition remains valid
(Repetition Structures, e.g., repeat-until operation).
In standard IBM-PC Assembly language there are no pet IF-ELSE, WHILE, DO, or FOR
statements. All these statements can be combined to create any logical structures. In fact,
we can optimize logic structures to make them execute more efficiently in comparison to
high-level languages. Anyhow, usually the logic structures given below are universal to
all structured programming languages.
IF STRUCTURES: -
An IF-THEN structure is called a “Single-selection structure” because it selects or
rejects a single action. The IF-THEN structure either performs an action if a condition is
true or skips the action if a condition is false. Its format is
IF condition THEN
statement(s)
An IF-THEN-ELSE structure is called a “Double-selection structure” because it selects
or rejects between two different actions. The IF-THEN-ELSE structure either performs
an action if a condition is true and performs another action if a different condition is
false. Its format is
IF condition THEN
statement(s)1
ELSE
statement(s)2
An IF-THEN-ELSE structure is called a “Multiple-selection structure” because it can be
linked to choose one of three or more alternative courses of actions. Its format is
IF condition THEN
statement(s)1
ELSE IF condition THEN
statement(s)2
ELSE
statement(s)3
WHILE-DO STRUCTURE: -
WHILE-DO structure is a repetition structure that tests a condition first before
performing a block of statements and as long as the test remains true, the statements are
repeated.
WHILE condition DO
statement(s)
In industrial control applications of microprocessors, there are many instances where we
use it.
REPEAT-UNTIL STRUCTURE: -
REPEAT-UNTIL structure executes one or more statements at least once and performs a
test at the bottom of the loop. This is different from the WHILE-DO structure where the
condition is evaluated before any action(s). Syntax is given as
REPEAT
statement(s)
UNTIL condition
N.B: For additional exercise, consult the class lectures in which flowcharts for various
programs had been developed. Then give these simple programs a try.
1. Write a program to find the sum, product, and mean of two positive integers.
2. Write a program to find the area and hypotenuse of a right-angled triangle when the
lengths
3. of its base and altitude are given as b and h respectively.
HINT: Area = ½ bh Hypotenuse = (b 2 + h 2 ) ½
4. Temperature of city in Farenheit degrees is input through the keyboard. Write a
program to convert this temperature into Centigrade degrees.
HINT: C =5(F-32)/9
5. Marks obtained by a student in five different subjects are given. Find the average and
percentage marks obtained by he student. Write a program assuming that marks obtained
by a student in each subject are 100.
6. Write a program to compute the sum, sum of squares, and the averages of n integers.
7. Write a program to find the factorial of an input integer.
8. Write a program to print the ASCII values and their equivalent characters. The ASCII
values vary from 0 to 255.
9. Two numbers x and y are entered. Write a program to calculate the xy.
10. Write a program to find the inductive XL and capacitive impedance XC . The
frequency is in Hertz, L is Henrys and C is in Farads.
11. Take a sample temperature data every hour for 24 hours and add 10 to each sample
and put each value in memory locations.
INTERFACING: -
Interfacing is the process of making two or more devices or systems operationally compatible
with each other so that they function together as required. The term “Interface” is used to
describe a hardware system that provides standard logic circuits and input/output channels for
the connection of peripheral units to a central processor (CPU). Each peripheral unit is coupled
to the processor via a standard multiway plug, which carries all wiring for the control signals
and data flowing between the processor and the peripheral unit. The I/O devices are connected
to the microprocessor through a special device called 'Interface or Port' (port is usually any
socket in a computer into which an I/O device may be plugged) and technique used for this
purpose is called “Interfacing”. This port is the pathway for data transfer between the
microprocessor and its peripherals (I/O devices). The CPU communicates with I/O devices via
I/O ports. The peripheral units/devices are machines that can be operated under computer
control e.g., input devices, output devices, and storage devices.
An interface chip is a LSI (Large-scale Integration Circuit that contains well over 100
interconnected individual devices, such as logic gates and transistors) component that provides
the communication link between a microprocessor and an I/O device. An interface consists of a
number of registers, selection logic, and control circuits that implement the required data
transfers. Manufacturers supplement their microprocessors with a set of interface chips suitable
for communication between microprocessor and a variety of standard I/O devices.
Port can be strictly for input, strictly for output or bi-directional for input and output. An I/O
port provides an interface between the microprocessor and the outside world of peripheral
equipment.
There are many interfacing methods that can be observed in the designs made for computers or
devices such as those used in telecommunication and office automation. Communication often
takes place with one device placing information on to a communication channel or on the
internal data highway of a computer for reception by another device. In order that computer
products made by different manufacturers may work together, standard authorities have
produced recommended methods for interfacing which cover mechanical, electrical, and
functional characteristics required in the interface between devices.
TYPES OF PORTS: -
At the most basic level there are two types of I/0 ports:
1. Parallel I/O ports
2. Serial I/O ports
Because the microprocessor naturally works with data in bytes and words the parallel interface/
port is easiest to implement. All the bits are transferred simultaneously. On the other hand a
serial I/O port is quite different. The data bits are lined up and transmitted in single file fashion
one bit at a time. It is apparent that this technique will be slower than the parallel port design
but it does have certain advantages.
Firstly, “Duplex Communication” (simultaneous transmission and reception) can occur with
only a three conductor cable, one wire for transmission, another for reception and the other to
establish a common ground between the microprocessor and peripheral. Secondly, the serial
data can also be transmitted using modem over the telephone network. Modem (an acronym for
MOdulator/DEModulator) also known as “Data Set” is a combination of modulator and
demodulator at each end of a telephone line to convert binary digital signals to audio tones
(analog signals) for transmitting over long distance lines without error and vice versa. Modem is
an example of transceiver (terminal units which can both transmit and receive data). Finally it
should be noted that serial and parallel transfers could occur together, e.g., a series of words
might be transferred serially, although each bit within the word is transferred in parallel.
I/O ports in the 8088/86 can be either byte-wide or word-wide. The I/O port is selected by the
I/O address. This address is specified as part of the instruction that performs the I/O operation.
I/O addresses are 16-bits long and are output by the 8088 to the isolated I/O interface over bus
lines AD0 to AD7 and A8 to A15. AD0 represents the LSB and A15 the MSB. Since 16 address
lines are used to address I/O ports, the 8088’s I/O address space consists of 64K byte-wide I/O
ports. Data transfers between the8088 and I/O devices are performed over the data bus. Data
transfers to byte-wide I/O ports always require one bus cycle.
an odd-addressed boundary) two memory read or write cycles are performed. Actually,
the 8088 pays a performance penalty with every word access. Fortunately for the
programmer, except for the slightly slower speed of the 8088, there is no difference
between the 8088 and the 8086.
The BIU performs the proper number of memory accesses, one if the word operand is an
even byte and two if it is an odd byte because it is said to be unaligned. So it is possible
to read words stored in bytes 5 and 6. The BIU must perform two memory read cycles,
one to fetch a low-order byte and second to fetch the high-order byte. This slows down
the microprocessor but is `transparent to the programmer.
MEMORY MAP: -
The addressing of memory can be established by means of a table that specifies the
memory addresses assigned to chip. The table called a “Memory Address Map ” is a
pictorial representation of assigned address space for each chip in the system as shown
in figure. And the process by which records are assigned to memory locations is called
“Address Mapping”. There are sixteen 64K-bytes blocks beginning at 00000H and
ending at address FFFFFH. This arbitrary division in to 64K-bytes blocks is a
convenient choice because in it the address 20000H is 65,536 bytes higher in memory
then address 10000H. Also note that five hexadecimal digits are required to represent a
memory address.
This diagram is called a “memory map” because like a road map it is a guide showing
how the memory is allocated. For example, it might show RAM from 00000H to 3FFFFH,
ROM from FF000H to FFFFFH and the remainder of the memory space unused. This
information is critical, because we must know where our programs can be safely loaded.
RAM: -
The resident portion of DOS is located at address 00600H, and free memory begins
immediately above DOS. The size of DOS has increased steadily over the past several
years, so its size will also vary between 23K and 40K.
Video Display Memory: -
The video display memory is memory-mapped. Rather than sending each video character
out through a port to the video display IBM decided that it would be more efficient to
give each screen position a separate memory address. When DOS writes a character to
the display, it calls a subroutine in the ROM-BIOS, which in turn writes the character
directly to a video memory address.
Video RAM memory (128K) extends from A0000H to BFFFFH, depending upon the type
of display used. Many programs write characters directly to the video display area. A
character written to the monochrome display area will not appear in the color display
area because they are at different memory addresses. Programs that write directly to
video memory must check the display type first.
ROM: -
IBM reserves locations C0000H to FFFFFH for specialized ROM uses, including the
hard disk controller. Finally the ROM-BIOS resides in locations F0000H to FFFFFH,
the highest area of memory. The BIOS contains low-level subroutines used by DOS for
I/O and other basic functions. Programs coded in ROM are often called “Firmware”,
because they are software stored in a hardware medium. They can not be changed
without redesign of the system.
1024KB
ROM-BIOS
Reserved ROM
Reserved for Video
User RAM
Disk Operating System
Interrupt Vector Table
0 KB
IBM-PC Memory Map
timing diagram apply to this microprocessor as well. A timing diagram illustrates the
timing sequence and other relationship along various control signals in the
microprocessor.
During an active bus cycle the microprocessor may perform a MEMORY READ,
MEMORY WRITE, I/0 READ or I/O WRITE operation. The control and address buses
are used to specify the memory or I/O address and the direction of data flow on the data
bus lines. Consider the sequence of events that occur during a memory read bus cycle.
The “Bus Cycle” of the 8088/86 is used to access memory, I/O devices, or the interrupt
controller. The bus cycle of the 8088/86 microprocessors consists of at least four clock
cycles. These four T-cycles are called T1, T2, T3 and T4.
T1: The microprocessor outputs the 20-bit memory address. Data lines are open-
circuited and all control lines are disable.
T2: The MEMR control lines driven low. The memory unit recognized this bus cycle as
memory read and prepares to place the address data (byte or word) onto the data lines.
T3: The microprocessor configures it data bus lines for input but takes no further action.
T4: The microprocessor now expects the data to be on the data bus lines. Thus it latches
the control of these lines and releases the memory read control signal. This marks the
end of the bus cycle.
Thus for a write memory cycle, data are put on the bus during period T2 and maintained
through T3 and T4. When a read cycle is to be performed, the bus is first put on the high-
impedance state and then data to be read must be put on the bus during T3 and T4.if no
bus cycles are required, the microprocessor performs “Idle States”. During these states,
no bus activity occurs. Each idle state is one T-cycle long, and any number of them can
be inserted between bus cycles. The most significant point to note is that the
microprocessor controls all the bus timing. Another point is about the control bus timing;
Only one control signal can by active at a given time e.g., the microprocessor can not
read from its memory at the same time it is outputting to an I/O device.