Introduction to tapered buffer:-

The tapered buffer design consists of a chain of inverter stages where width of each MOS transistor in a
stage is increased by a constant factor (called tapering factor) than that of the transistors placed on the
previous stage. The constant increase in width of transistors in each stage provides fixed ratio of output
current drive to output capacitance and hence equal rise, fall, and delay times for each stage.

CMOS tapered buffers are frequently used to drive large capacitive loads, which arises from long global,
interconnect lines such as clock distribution networks, high capacitance fan out, and off-chip loads.
Typically, local interconnect Capacitance is assumed to be negligible during the design of these tapered
buffer systems. Since active area of recent research is to reduce power utilization of the CMOS transistors,
hence power efficient buffers are always essential. Static power remains constant in digital designs, but
sub-threshold leakage power tends to increase with scaling of the technology. This power can be reduced
with the increase in threshold voltage or reducing the value of operating voltage VDD. However, the effect
of increasing or decreasing threshold voltage while keeping VDD fixed has very small impact on the delay
of the circuit [16]. The proposed strategy can be helpful to vary threshold voltage of CMOS transistors.
Because varying the threshold voltage of MOSFET by varying the width or tapering factor of the transistor
could affect the PDP of the circuit due to large area utilization. So Buffer designing demands an approach
that could resolve the issues related to PDP. The optimal values of primary factors for implementing Buffer
design also play an important role. In addition, expressions related to Tapering factor and optimum
number of stages used in the implementation of Buffer is mentioned in [6] and are given below using
equation (1).

Here Cg and CL are gate capacitance and load capacitance and F is Tapering factor Using these parameters,
the value of propagation delay of Buffer can be calculated using equation (2):-

Where VDD is applied D.C voltage to buffer circuit its operating value is based on technology node, VDO
and IDO are the saturation drain voltage and saturation drain current at VGS = VDD, is velocity saturation
index and = Vth / VDD.

II. CMOS Tapered Buffer designing parameter:-

The primary designing parameters of tapered Buffer are number of stages of CMOS inverters and
increasing width defining tapering factor. The optimal values of these factors can be calculated or derived
using equation (1) for optimal values of result parameters of Buffer. And conventionally number of stages
needs to be varied for changing the threshold voltage of the circuit. The increase in number of stages
could increase the power dissipation or its cost function. Another approach is the use of FBB for varying
Vth in Buffers.
The threshold voltage refers to the switching voltage of the inverter. This can be defined as the gate
voltage at which a MOS transistor begins to conduct.

The threshold voltage can be given by

Where VTH0 is the threshold voltage at VSB =0V and it can be expressed as

Here γ is body effect coefficient (which is Positive for NMOS and Negative for PMOS), φF is the Fermi
potential with respect to mid gap in the substrate (which is Negative for NMOS and Positive for PMOS).
This equation states the effect on threshold voltage due to source to body bias voltage i.e. by adjusting
the VSB (Voltage between source and body terminals of MOS) we can have control over the threshold
voltage of the device. Otherwise Generally VSB is taken as zero volts for all circuits.

2. CURRENT-MODE LOGIC BUFFERS:-

A current-mode logic (CML) buffer is based on the differential architecture. Fig. 1. (a) shows a basic
differential architecture. The tail current, ISS, provides an input-independent biasing for the circuit. The
differential circuit is easily neutralized using a pair of capacitors, CD,that will diminish the deleterious
effects of input-output coupling through the device overlap capacitance, CGD. Various experimental
simulations of CML circuits reveal that the long-channel transistor model still gives rise to a good
estimation of the dynamic behavior of these circuits. The reason is that a CML circuit is a low-voltage
circuit where the differential voltage swing is around the device threshold voltage. As the differential input
varies from to, each output node of the differential pair varies from to VDD. Fig. 1 (b) shows the voltage
variations of the output nodes in terms of the differential input.

3. TAPPERED CML BUFFER DESIGN:-

 To achieve the best performance in a CML buffer, a complete current switching must take place, and the
current produced by the tail current needs to flow through the ON branch only. In a tapered buffer chain
a CML buffer drives another buffer, which means that output terminals of the driving buffer stage are
connected to the input terminals of the driven stage, as shown in Fig. 3. To satisfy the above performance
requirement, the differential voltage swing of the first CML buffer must exceed of the following stage: