Journal of the Korean Physical Society, Vol. 42, No. 2, February 2003, pp.

200∼205

Design of Bluetooth Baseband Controller Using FPGA

Sunhee Kim and Seungjun Lee∗

CAD and VLSI Lab.,Department of Information Electronics Engineering, Ewha Womans University, Seoul 120-750

(Received 23 April 2002)

This paper presents the design of a Bluetooth baseband controller. Bluetooth, which is intended
to replace the cables connecting portable and/or fixed electronic devices, is a universal short-
range radio link via an ad-hoc network and is specifically designed to provide low-cost and robust
networking by applying fast frequency hopping and a shaped, binary FM modulation. Our baseband
controller is designed in Verilog -hardware description language (HDL) and is implemented into a
field programmable gate array (FPGA). The FPGA implementation integrated with Link Manager
software was tested with Bluetooth spec version 1.1 and was shown to be fully functional. The
controller carried out the baseband protocols and other low-level link routines and supported about
a maximal 700 kbps at a 1 Ms/s symbol rate and about a maximal 5 Mbps at a 4 Ms/s symbol
rate.

PACS numbers: 85.40.Bh

Keywords: Bluetooth baseband

I. INTRODUCTION ity [3].

Figure 1 shows the Bluetooth protocol stack. The ba-
sic protocols that all Bluetooth systems must have are
Recently, the increasing demand on wireless personal a radio, a baseband (BB), a link manager (LM), and a
area networking (WPAN) has resulted in various stan- logical link controller. The radio takes care of sending
dards, such as Home RF, IEEE 802.11 and Bluetooth, and receiving modulated bitstreams. The BB takes care
as well as systems applied to those. Due to the high of the timing, and the framing, as well as packets, flow
demand for 2.4 GHz RF circuits, many CMOS RF solu- control, error detection, and correction. The LM takes
tions with low power consumption are being introduced care of managing states and packets and of controlling
to the market, and the cost for those devices is getting flow on the link. The logical link controller takes care of
lower [1,2]. multiplexing user protocols, as well as segmentation and
Bluetooth is a short-range radio link intended to re- reassembly of larger datagrams into packets, and man-
place the cable(s) connecting portable and/or fixed elec- agement [3]. This paper presents the hardware design of
tronic devices [3]. For instance, Bluetooth built into both a Bluetooth baseband controller which supports an op-
a cellular telephone and a laptop will replace the cum- tional high data-rate mode of 5 Mbps at a 4 Ms/s symbol
bersome cable used today to connect the laptop to a rate, as well as a normal data rate of 700 Kbps at 1 Ms/s
cellular telephone. Printers, personal digital assistants
(PDAs), desktops, fax machines, keyboards, joysticks,
and virtually any other digital device can be part of the
Bluetooth system. In addition, Bluetooth provides a uni-
versal bridge to existing data networks, a peripheral in-
terface, and a mechanism to form small private ad-hoc
groupings of connected devices away from fixed network
infrastructures [4].
Bluetooth establishes ad-hoc voice and data connec-
tions and operates in the 2.4 GHz unlicensed ISM band.
Its specification is open and royalty-free. The symbol
rate is 1 Ms/s to exploit a maximum available channel
bandwidth of 1 MHz. Fast frequency hopping is applied
to combat interference and fading. A shaped, binary FM
modulation is applied to minimize transceiver complex-

∗ E-mail: slee@ewha.ac.kr; Fax: +82-2-3277-2804 Fig. 1. Bluetooth protocol stack.

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Design of Bluetooth Baseband Controller Using FPGA – Sunhee Kim and Seungjun Lee
Fig. 2. Block diagram of the designed baseband controller.
symbol rate, as specified in Bluetooth 1.1 specification.
II. EVOLUTION OF BLUETOOTH
STANDARD
Since the Bluetooth specification version 1.1 was an-
nounced in February, 2001, the medium rate mode
(MED) and the Bluetooth spec 2.0 high rate mode have
been discussed as extensions to the current Bluetooth
spec. MED aims to meet the demand for a higher data
rate for new applications by supporting 2∼3 times higher
data rate than Bluetooth 1.1 while maintaining most of
existing Bluetooth 1.1 functions. Bluetooth 2.0 tries to
support up to an 8 Mbps gross air rate by adopting new
network topology and a simple modulation scheme. It
may also coexist in the Bluetooth 1.1 piconet.
In this paper, we present a high data rate baseband
controller that can support up to an 8 Mbps gross air
rate. A 4-level Gaussian frequency shift keying (GFSK)
modulation/demodulation scheme at a 4 Ms/s symbol
rates is implemented by modifying only the data path
and the modem part of the baseband controller such
that Bluetooth 1.1 PHY can be reused without modi-
fication. The packet length was changed to accommo-
date increased user data, as well as the modulation type.
However, the access code format remains the same as it
is in Bluetooth 1.1.
III. HARDWARE DESIGN
As shown in Figure 2, the designed baseband controller
consists of a register file, a controller, a data path, a
modem, a hop selector, a clock generator and interface
blocks. The register file is used to exchange information
between LM and BB. The controller takes care of timing
and state changing, as well as low-level link control. The
data path composes the packet to be transmitted and
decomposes the received packet. The modem takes care
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Fig. 3. State diagram of the designed baseband controller.
of smoothing the packet in the transmit path and recov-
ering the data and the clock in the receive path. The
hop selector selects the hop frequency for packet trans-
mission, and the clock generator supplies clock signals to
all the other blocks.
1. Register File
The BB controller communicates with the LM proces-
sor through the register file. The register file has local
device information, remote device information, current
status information, transmitted and received packet in-
formation, and interrupt flags. Because most of the infor-
mation requires only a few bits, the data in the register
file can be accessed either as a byte, a half-word, or a
word.
2. Controller
The controller is divided into three parts: a timing
controller, a state controller, and a link controller. The
channel is divided into time slots that are numbered ac-
cording to the Bluetooth clock of the piconet master.
Each slot, 625 µs in length, corresponds to an RF hop fre-
quency. A time-division duplex scheme is used in which
the master and the slave alternately transmit [5]. There-
fore, a piconet must be synchronized to the master Blue-
tooth clock, and each slave must calculate the clock offset
when it receives the packets transmitted by the master
to estimate the master Bluetooth clock. For that rea-
son, we designed the time controller based on a half-slot
time duration, which is the minimum time period needed
for the ID packets, the shortest of all packets. The time
controller counts from 0 to 2499 during a half slot, deter-
mines when both a master and a slave start their trans-
mission, and estimates when the slave receives the packet
transmitted by the master.
Figure 3 shows the state diagram of our controller.
There are seven states: STANDBY, page, page scan,
-202- Journal of the Korean Physical Society, Vol. 42, No. 2, February 2003
Fig. 4. Block diagram of the data path.
master response, slave response, NR, active and HR ac-
tive. The “NR active” state corresponds to the “active
state” specified in Bluetooth spec. 1.1, and the “HR ac-
tive” state stands for “high data rate active.” The HR
active state is added to support the higher data rate of
a 4 Ms/s symbol rate with 4-level GFSK modulation,
which has been implemented as a possible extension of
current Bluetooth specification.
In order to establish new connections, a master and a
slave go through a paging and a page-scan procedure, re-
spectively. Command from LM changes the current state
to either a page or a page-scan state. During the paging
procedure, the state must be changed upon receiving a
packet or at time-out. In those cases, the BB controller
analyzes the received packet or checks out the timers
for each state. Therefore, the BB controller changes the
state to NR active through a page response and carries
out routines for each state.
The link controller takes care of low-level link control,
such as the automatic repeat request (ARQ) scheme and
flow control. These are carried out independently of the
other units. Thus, there is a separate ARQ-FLOW-Flag
register for each AM-ADDR that is used to distinguish
among the active members.
3. Data Path
Each packet consists of three entities: the access code,
the header, and the payload. The packet composer adds
the header error check (HEC) to the header informa-
tion read from the register file and the link controller,
and then scrambles the header with a whitening word
and encodes it at a rate of 1/3 forward error correction
(FEC). The payload information plus the cyclic redun-
dancy check (CRC) is scrambled, encrypted, and coded
at a rate of 2/3 FEC.
The packet decomposer extracts the header and the
payload information from received packet in reverse or-
der from the packet composer. CRC and/or FEC may
be included optionally based on the packet type. Figure
4 shows a block diagram of the data path.
Fig. 5. Verilog simulation result of the modulator.
Fig. 6. Block diagram of the demodulator.
A TX buffer is provided separately for each AM-
ADDR, but a RX buffer is shared. Each buffer consists
of two fifo registers, two switches, and full-flag registers
for each register. The switches determine which register
can be accessed by the LM processor and which register
can be accessed by the BB controller. All the TX and the
RX buffer switches are controlled by the BB controller.
4. Modem
The modulator consists of a symbol mapper and a
gaussian low pass filter (GLPF). Data arrive at the map-
per at the input bit rate and is demultiplexed as encoded
symbols. In the 2-level GFSK mode, the data are directly
passed to the GLPF. For a 4-level GFSK, the symbol rate
is one-half of the bit rate, and each symbol is composed
of two bits. However, the access code is directly passed
to the GLPF because it is used for timing synchroniza-
tion. Figure 5 shows the Verilog -hardware description
language (HDL) simulation results. In the 4-level GFSK
mode, the bit data (b) which corresponds to the access
code is mapped to the 2-level symbol while the access-
code-valid signal (a) is high, and the bit data are mapped
to the 4-level symbol when the access-code-valid signal is
low. The signal (d) shows the Gaussian-filtered output.
As shown in Figure 6, the demodulator consists of the
correlator, the clock recovery, and the symbol demapper.
We assume that the sample rate of the analog to digital
converter (ADC) is four times the symbol rate, and its
output with a resolution of 8 bits is passed to the slicer.
The threshold value of the slicer is updated from the
default value, 127, to the measured value by the clock
recovery after the correlator is triggered. The correlator
has the structure of a matched filter. The clock recovery
Design of Bluetooth Baseband Controller Using FPGA – Sunhee Kim and Seungjun Lee -203-

Fig. 7. General block diagram of the hop selector.

finds the symbol boundary by using the known, regular

pattern of the access code trailer and recovers the symbol
clock.
Fig. 8. Example comparing the spec and the proposed
method of paging hop frequency.
5. Hop Selector

response, CLK1−0 becomes ‘11,’ and the value of N is

The hop selector generates hopping sequences - page
increased at the next half slot. The master transmits an
hopping sequence, page response sequence, inquiry se-
FHS packet a half or one slot after it receives a response
quence, inquiry response sequence, and channel hopping
packet. Therefore, the slave awaits the arrival of an FHS
sequence - for the 79-hop and the 23-hop systems. As
packet when CLK1−0 is either ‘00’ and ‘01.’ If the slave
shown in Figure 7, hopping frequency is selected by us-
receives an FHS packet when CLK1−0 is ‘01,’ it resets
ing control signals - X, Y, A, B, C, D, E, and F- that
CLK1−0 to ‘00.’ Figure 8 shows one case - initially the
are derived from the upper address part (UAP)/ lower
master has CLKN1−0 ‘00’, and the slave has CLKN1−0
address part (LAP) of Bluetooth device address (BD-
‘01’ - to compare the spec. and the proposed method.
ADDR) and the Bluetooth clock. The Bluetooth clock
may appear in two different forms: CLKN, which is a
free-running native clock, and CLK, which is a master
clock and is derived from CLKN by adding an offset. 6. Clock Generator
However, the Bluetooth spec. 1.1 has an obscure de-
scription of the page response sequence. X and Y for the Table 1 shows all the clock signals classified according
slave page response sequence are given by to their functionality, but the target field programmable
∗
gate array (FPGA) only supports four global clock
X = [CLKN16(15)−12 + N ] mod 32(16) (1) buffers. Therefore, externally supplied clocks, CLK-BUS
and CLK-IN, and divided clocks, CLK-MAIN and CLK-
Y = CLKN1 . (2) BIT, are assigned the clock buffers. The frequency of
CLK-BIT is changed according to the operating mode
It is written in the spec. that the value of N is increased
(HR-Active/NR-Active) and the current slot type. CLK-
by one each time CLKN1 is set to zero, which corre-
SYMBOL, CLK-SAMPLE and CLK-FILTER are re-
sponds to the start of a master TX slot [3]. However, the
placed by CLK-IN and enable signals.
master CLKN1 and the slave CLKN1 don’t correspond
because CLKN is never adjusted and is never turned off.
Thus, the hopping frequency of a master may be differ-
ent from that of a slave when the master transmits an 7. Interface Block
frequency hop synchronization (FHS) packet. To resolve
this problem, we modified the equation such that the In our test environment the BB controller acts as an
value of N was increased not by CLKN1 but by CLK1 . advanced high-performance bus (AHB) slave to commu-
When the slave receives an ID packet in the page scan nicate with the LM processor. Therefore, the Interface
state, it can infer that the master CLKN1−0 is either block has the AHB decoder to generate bus response sig-
‘00’ or ‘01’, so it sets CLK1−0 to ‘01’. For a returning nals.
-204- Journal of the Korean Physical Society, Vol. 42, No. 2, February 2003

Table 1. Clock signals classified functionally.

CLK-BUS AHB bus clock 20 MHz

CLK-MAIN Timing controller clock 8 MHz
Normal rate High rate
TX bit processing clock 1 MHz 8 MHz
CLK-BIT
RX bit processing clock 1 MHz 8 MHz
TX mapping clock 1 MHz 4 MHz
CLK-SYMBOL
RX demapping clock 1 MHz 4 MHz
CLK-SAMPLE RX sampling clock 4 MHz 16 MHz
CLK-FILTER Gaussian filter clock 8 MHz 32 MHz

Table 2. Implementation results using a Xilinx Virtex a XCV2000E FPGA board for our design, the BB con-
XCV2000EFG FPGA. troller. In our test set-up, we connected data and fre-
quency value pins between two boards with cables to
Number of Slices 6,099
isolate the BB from the RF channel noise. The LM com-
Number of Slice Flip Flops 2,996 mands one to start paging and the other to start page
Total Number of 4 input LUTs 9,825 scan, so a connection is established between them under
Number of bonded IOBs 136 the management of the state controller and the hop se-
Number of Block RAMS 52 lector. To test the link controller, we inserted regularly
Number of GCLKs 4 an error bit to a received packet, we checked the aver-
Total equivalent gate count for design 947,288 age data rate decrease and the packet error rate differ-
ence between the data-medium rate (DM) packet coded
with 2/3 FEC and the data-high rate (DH) packet not
coded. Also, we intentionally kept RX buffer full in or-
der to check the flow control. As a result, we get about
a maximum 700 kbps in the NR-active state and about
a maximum 5 Mbps in the HR-active state.

VI. CONCLUSIONS

In this paper, we present the design of a Bluetooth

Fig. 9. Test environment.
IV. IMPLEMENTATION RESULTS
The baseband controller was designed in Verilog-HDL
and was verified using the Verilog-XLT M simulator.
The Verilog description is mapped onto Xilinx Virtex
XCV2000. Table 2 shows the implementation results.
The total number of 4-input LUTs is 9,825, and the num-
ber of bonded IOBs, including test pins, is 136. Fifty-
two block RAMs, each 256-bit, are used for TX and RX
buffers. The operating frequency is 32 MHz, and the
total equivalent gate count for design is 947,288.
V. TEST RESULTS
baseband controller that complies with Bluetooth spec.
version 1.1 and supports an extended data rate. It is
designed in Verilog-HDL and implemented using a Xil-
inx Virtex XCV2000. The implementation is tested with
LM software executed in an ARM7TDMI. The designed
baseband controller was verified to be fully functional to
carry out the baseband protocols and other low-level link
routines. It supports about a maximal 700 Kbps at a 1
Ms/s symbol rate 2-level GFSK and about a maximal 5
Mbps at a 4 Ms/s symbol rate 4-level GFSK.
ACKNOWLEDGMENTS
This work has been supported by the Electronics and
Telecommunications Research Institute and partly by
Brain Korea 21.

As shown in Figure 9, the test board consists of a

ARM7TDMI development board for LM software and REFERENCES
Design of Bluetooth Baseband Controller Using FPGA – Sunhee Kim and Seungjun Lee -205-

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