(b) Explain switch level modeling and simulation with

suitable example. (13)

12. (a) Explain the principle and implementation of ROBDD.
(13)
NH – 67, Karur – Trichy Highways, Puliyur C.F, 639 114 Karur District
(Or)
Examination - III
DEPARTMENT OF ECE (b) What is two level logic synthesis? Explain in detail.
Branch & Section: I ME VLSI Date & Time: 02.12.19 & 3Hours (13)
Semester: I Max.Marks: 100 13. (a) Explain any two scheduling algorithm in detail. (13)
Subject: VL5201 CAD for VLSI Circuits
(Or)
Staff Incharge: M.Kumar, AP/ECE
PART A (10 × 2 = 20) (b) Explain the force directed scheduling algorithm and
ANSWER ALL THE QUESTIONS explain the role of it in high level synthesis. (13)
1. What are the software modules used for simulator? 14. (a) Explain the optimization issues and formulation of
2. How can ROBDD be used in logic verification? assignment problem. (13)
3. Show a chart that performs the transition of a high level (Or)
synthesis. (b) Discuss the different aspects of assignment problems.
4. Draw the data flow graph for the given program fragment (13)
while (a>b) a ← a – b; 15. (a) What is high level synthesis? List and discuss briefly
5. Give the difference between assignment and allocation. the steps involved in it. (13)
6. Compare the performance of even driven simulation (Or)
algorithm with a compiler driven logic simulation (b) What is data flow graph? Explain the types of DFG
algorithm. used in high level synthesis. (13)
7. Define retiming transformation. What is the use of it in PART C (1 × 15 = 15)
high level synthesis? ANSWER ALL THE QUESTIONS
8. State the importance of binary decision diagram. 16. (a) Explain compiler driven simulation with examples.
9. What is the role of logic synthesis in VLSI design? (15)
10. Define high level synthesis. (Or)
PART B (5 × 13 = 65) (b) Describe ASAP scheduling algorithm. Explain its role
ANSWER ALL THE QUESTIONS in high level synthesis. (15)
11. (a) Explain event driven simulation and its applications.
(13)
(Or)