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Date \ '() /2\/\C\ Period _l___

' Activity 2.2.2 NANO Logic Design

Introduction I~
The block diagram shown below represents a voting booth monitoring system. For privacy reasons,
a voting booth can only be used if the booth on either side is unoccupied. The monitoring system
has four inputs and two outputs. When.ever a voting booth is occupied, the corresponding input (A,
B, C, & D) is a (1). The first output, Booth, is a (1) whenever a voting booth is available. The second
output, Alarm, is a (1) whenever the privacy rule is violated.

Booth Booth Booth Booth

A B C D
l
I
1 l ,.
Voting Booth
I,

I
~

Booth ~
Monitoring
System
I ..
Alarm /
In this activity you will implement NAND only combinational logic circuits for the two outputs Booth
and Alarm. These NAND only designs will be compared with the original AOI implementations in
terms of efficiency and gate/IC utilization. In a future activity, these NAND only designs will be
compared to the circuits implemented using only NOR gates.

Equipment
• Paper and pencil
• Circuit Design Software (CDS)
• Digital Logic Board (DLB)
• Integrated Circuits (74LSOO)
• Jumper wire
Procedure
For th ·t or systems have beer
e sake of r1 · booth moni . .
com me, the truth table and K-Maps for the vot ing I don't care co nd 1t1o r,
p 1eted for you. Note, for the output Booth we took advantage of severa

--
CD CD CD
CD

1 1 X 1
A B
AB
C D Booth Alarm

0 0 0 0 1 0
AB 1 0 X X
0 0 0 1 1 0

0 0 1 0 1 0 AB X X X X
.
0 0 1 1 X 1 -
AB 1 0 X 0
0 1 0 0 1 0

0 1 0 1 0 0 - - - -
0 1 1 0 X 1 Booth = A 8 + C D
0 1 1 1 X 1

1 0 0 0 1 0
CD CD CD CD
r
1 0 0 1 0 0 AB 0 0 1 0
1 0 1 0 0 0 ,
' .,
1 0 1 1 X 1 AB 0 0 1 1
1 1 0 0 X 1
AB 1 1 1 ,.
1 1 0 1 X 1 "- 1
1 1 1 0 X 1
AB 0 0
I

1 0
1 1 1 1 X 1 '

Alarm = A B + B C + CD
 1. \n the space provided, draw the AOI circuits that implement the simplified logic expressions
Booth and Alarm. Limit this implementation to only 2-input AND gates (74LS08), 2-input OR
gates (74LS32), and inverters (74LS04).

2. Then, re-implement these circuits assuming that only 2-input NANO gates (74LSOO) are
availab\e. Draw these circuits in the space provided.

Booth-AO\ Booth- NAND

I\ ~--((. ,.,

Alarm- NAND
Alarm-AOI
A t c_ D
w

3
 3. Using the cos, enter and test the two logic circuits that you designed. Use switches for the
inputs A, B, c, and Dand a probe or LED circuit for the outputs Booth and Alarm. Verify that
the circuits are working as expected. Label. print and attach a copy of these circuits to this
document. Note: Even though the two circuits work independently,tt:hey are part of on~
design and should be simulated, tested, and prototyped together.

4. Using the DLB, build and test the NANO logic circuits that you designed and simu/at d V .
that the circuits are working as expected and the results match the results of th • e · ~nfy
e s1mulat1on.
Teacher Verification of working circuit on DLB .{7i:J / J " Z L[
Conclusion

1. For your AOI implementations how ma .

~equired to implement your ci;cuits? No~y .'~s (r;e., 74L~04, 74LS08, and 74LS32 chips) were
ut rather, the number of IC in wh ·, e. ou re not Just counting the number of gat
~<)l ·,,,_ , , oeorpart,thatwererequired. esused,
.. 'r~~IJ-vt ij\:,fl~ q. I . I

'- · Ch\1(1, .

2.For your NAND . I

. imp ementar
your circuits? Again ions, how many ICs ('
'we are countin 1.e., 74LSOO chi )
7\. i 111 • g ICs, not gates. ps were required to . I
t.. N"' \J\') 1 ""' ;i '. ·, . imp ement
.P e lfV\ e' ~ ~t,~ ~\~ i ~ 4 'i c CI '
it\l r l

3. In terms of hard
. ware eff, •
implementation? c1ency, how does th
__ . eNANDi
\h \ mplementation
c..':J V\uc.) -\-V\< "" 0 compare to the AO/
C.\ YV\ ( C:. '\ ~ ' '
\ (.' li' V'\ (
1.
I

L,

4. NANO
gates are available .
these chips have b With three in . !
the design? een used for this de!ut~ (74LS1Q) and t .
T 0 o '-\ . gn, If so, how our Inputs (74
- \ • ,, - )"'- 1 ..,, (. -t Would it have affe~!O). Could either of
"'-e
V\ 1~ \r-ro " \ d 1
. "01;: W\ .
"'~ '-\
...J
C \ \
Ov t}
\...
\;J f' :--.
th
d e efficiency of
_I , (-'
~V (' (" .\) \ ) ' ' \...,\~ ._. , la\...
1 1 --\ , ·o
' ( \\·"'-I

4
 GND

- s.ov
51 52 S3 S4

Key= B Key= C Key= D

Key= A
U1

X1

2.5V

U7 C
NAND2

U4 NAND2

NAND2

U8
E
X2
U12

2.5V

F
NAND2

U10

NAf'4D2 X3
G
G
Ui4
2.5V
U16
NOR2

NOR2 NOR2 H

~ NOR2
U18

U24

U28
NOR2
U20 NOR2 NOR2 X4

2.5V

K
NOR2
NOR2
U22

U26

NOR2

NOR2