8 Report

Secured Money Transaction Using Multi Account Embedded ATM Card
CHAPTER-1
OVERVIEW
1.1 INTRODUCTION
In most modern ATMs, the customer identifies him or herself by inserting a plastic
card with magnetic strip or plastic smart card with a chip that contains his or her account
number. The customer then verifies his or her identity by entering a pass code, i.e. personal
identification number (PIN) of four digits. If the number is entered incorrectly several times
consecutively (usually three), most ATMs will retain the card as a security precaution to
prevent an unauthorized user from discovering the PIN by guesswork and so on. Moreover
there is a limitation in transaction for the other bank customers in using the ATM of some
other bank crossing the limit they have to pay transaction fees.
At present every customer has an individual ATM card for each and every bank in
which he/she maintains account. So handling the cards, their passwords play a major role
here. So to overcome these difficulties we embedded more than one bank account of the user
in a single ATM smart card, so that the user can swipe the card and can select the bank from
which he/she are interested to carry out transaction.
1.2 OBJECTIVES
 Reduces the complexity of managing more than one ATM card and their passwords.
 Each time, the customer can change the password at the beginning of the transaction,
thereby increasing the security.
 Every transaction that takes place will be authorized by the account holder through
SMS.
 Cloud Computing concept for connecting respective bank ATM server.
Dept. of ECE, RLJIT 2013-2014 1

1.3 LITERATURE SURVEY
In this chapter, we briefly explain about the current existing systems, the problems
that are present in them and we also present various solutions to overcome those problems
and how we adopted these solutions into our project.
1.3.1 MULTI ACCOUNT EMBEDDED ATM CARD
In the existing system, every customer has an individual ATM card for each and every
bank in which he/she maintains account. So handling the cards, their passwords play a major
role here. So to overcome these difficulties we propose a system to embed more than one
bank account of the user in a single ATM smart card, so that the user can swipe the card and
will be able to select the bank from which he/she is interested to make a transaction.
Figure 1.3: Current existing system
In the existing ATM system all ATM machines are connected to their respective bank
servers and all bank servers are connected to a single interface i.e. National Finance Switch
(NFS). When the user swipes his ATM card at the respective bank’s ATM machine, then that

ATM machine directly links to its bank server for validation of ATM card. If the ATM card
is of the same bank then transaction proceeds else connects to the respective bank’s server via
NFS for the further transaction.
1.3.2 SECURE PIN ENTRY METHOD
Personal identification number (PIN) is a common method to authenticate a user for

various devices including automatic teller machines (ATMs), mobile phones, and so on.
However, if someone observes the input procedure by using a tiny camera, he can easily get
the PIN. This kind of attack is called ‘shoulder surfing attack (SSA).
We presenting new pin entry method, it contains two parts that is four digit with one
symbol which is given by user of the account. We adopt a completely different approach to
the existing problem, and present a secure and practical PIN entry method. According to our
experiments, the proposed method significantly reduces the error probability. The principal
idea behind this method is each time user can set new password instead of bank and to avoid
the card blocking procedure taken up by the banks if the user enters the wrong password
more than three times.
1.3.3 REAL TIME SMS BASED SECURITY
Existing measures adopted by financial institutions require ATM card holders to

optionally subscribe to financial transactions message alerts through Short Message Services
(SMS) (debit and credit transactions) and the use of posters pasted in banking halls to warn
customers on the need to protect PIN numbers from unauthorized users. These measures are
purely informative and do not adequately deal with the problems in real time. In this project,
we introduce a Real Time Instructive SMS-Based scheme called MophTem (Mobile phone
Text message) scheme which compels all customers to subscribe to SMS alerts as a basis for
initiating transactions on their account.
Every time the user's account is accessed, a message will be sent to the registered
mobile number to authorize the transaction. Only after the user's confirmation is received, the
transaction is processed.

1.3.4 CLOUD BASED ATM ENVIRONMENT
Cloud computing is a key technology to provide security for any advanced systems. In
the scenario we are depicting, we leverage the use of the Cloud technology to reproduce real
world scenarios encompassing distributed systems, e.g., several ATM centres belonging to
the same system and deployed over different cities. we propose the adoption of a Private
Cloud Infrastructure model to build up an advanced ATM system that will replace the
existing systems by overcoming the problems which are there in the current systems and
then to apply proposed methodology, after assessing the vulnerabilities of the system.
We propose a new cloud computing service called Data Protection as a Service. Using
this concept we are concentrating on user authentication, data protection, and security parts.
For the security in storage most system uses data protection mechanisms. They include
graphical password, alphanumeric password and many other used similar ways that will help
us to increase the security of data. In this system using cloud concept we are showing
different banks in ATM system ,it will contains many banks and we considered each bank as
one cloud and it contains many user accounts of that bank.

CHAPTER-2
BLOCK DIAGRAM
In this chapter, the basic design of the project is defined with the help of a proposed
system, a model block diagram and the working principle of the project is explained. The
proposed system, as shown in Figure 2.1, gives a brief idea about our project. The model
block diagram as shown in Figure 2.2 shows the different components used and how they are
connected.
2.1 PROPOSED SYSTEM
The idea behind this universal ATM card is that the customers can use a single ATM card to
operate different bank accounts instead of having individual card for each bank account and
maintaining their pin’s, carrying the cards safely which is a tedious process at present
scenario. The technology behind the product of the service is that adding all the user bank
accounts to a universal ATM card. In this the user swipes his/her smart card in the ATM
machine, then it request for authentication in the server side. After the user is authenticated,
then it displays the list of all banks that the user is having account. Now the user can select
the bank from which he/she is willing to perform transaction. After selecting the bank the
request is sent to the corresponding bank through a network and links it with the banks server
for accessing the database of the user or customer so that the transaction is processed.
Figure 2.1: Proposed System

2.2 MODEL BLOCK DIAGRAM
Figure 2.2: Model block diagram
2.3 WORKING PRINCIPLE
Here for demo purpose we are using RFID cards as ATM cards. When user brings
RFID card near RFID reader then on the touch screen authentication page will display. If
correct user name and password is entered then security password will be sent to user mobile,
then use has to enter the received number on the screen.
After successful login, all bank symbols will be displayed on the screen, and then user
has to select the corresponding bank to perform transaction. Before any transaction again
security number is sent to confirm the transaction.
Whenever ATM user enters the ATM machine he/she will get SMS to their mobile
indicating their transaction is being started. In reply the ATM user needs to reply by entering
their password.

When ATM machine asks for password they have to enter the same password which
they have forwarded from their mobile. If the enter any other password other than that
transaction will be stopped. Advantage of this system will be every time user can change the
password for every transaction they made.
When the user enters the amount he/she will get a SMS again to their mobile asking
whether cash to be withdrawn or not. If they want they can stop the transaction at this point
also. Also, when making purchases, the user will get a notification message saying that a
transaction is being made from his account. Only after the user authorization is received, the
transaction is allowed. Else the transaction is blocked then and there itself.

CHAPTER-3
HARDWARE COMPONENTS
3.1 ARM LPC2148 MICROCONTROLLER
3.1.1 DESCRIPTION
The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit

ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine
microcontroller with embedded high speed flash memory ranging from 32kB to 512kB. A
128-bit wide memory interface and unique accelerator architecture enable 32-bit code
execution at the maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for
applications where miniaturization is a key requirement, such as access control and point-of-
sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple
UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8kB up to 40kB, make these devices
very well suited for communication gateways and protocol converters, soft modems, voice
recognition and low end imaging, providing both large buffer size and high processing
power. Various 32-bit timers, single or dual 10-bit ADC, 10-bit DAC, PWM channels and 45
fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these
microcontrollers suitable for industrial control and medical systems.

3.1.2 PIN DIAGRAM
Figure 3.1: Pin diagram of LPC2148

3.1.3 FEATURES
 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

 8kB to 40kB of on-chip static RAM and 32kB to 512kB of on-chip flash
 Memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation.
 In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
 Loader software. Single flash sector or full chip erase in 400 ms and programming of
256 bytes in 1ms.
 Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip Real Monitor software and high-speed tracing of instruction execution.
 USB 2.0 Full-speed compliant device controller with 2kB of endpoint RAM. In
addition, the LPC2146/48 provides 8kB of on-chip RAM accessible to USB by
DMA.
 One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of
6/14 analog inputs, with conversion times as low as 2.44μs per channel.
 Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
 Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
 Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
 Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus
(400kbit/s), SPI and SSP with buffering and variable data length capabilities.
 Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
 Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package,.
 Up to 21 external interrupt pins available.
 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100μs.
 On-chip integrated oscillator operates with an external crystal from 1 MHz to 25MHz.
 Power saving modes include idle and Power-down.
 Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
 Processor wake-up from Power-down mode via external interrupt or BOD.
 Single power supply chip with POR and BOD circuits:
 CPU operating voltage range of 3.0V to 3.6V (3.3 V ± 10 %) with 5V tolerant I/O pads.

3.1.4 FUNCTIONAL DESCRIPTION
 Architecture Overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on Reduced
Instruction Set Computer (RISC) principles, and the instruction set and related decode
mechanism are much simpler than those of microprogrammed Complex Instruction Set
Computers (CISC). This simplicity results in a high instruction throughput and impressive
real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed, its
successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory restrictions,
or applications where code density is an issue. The key idea behind Thumb is that of a super-
reduced instruction set.
The ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65
% of the code size of ARM, and 160 % of the performance of an equivalent ARM processor
connected to a 16-bit memory system. The particular flash implementation in the
LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended
to program performance critical and short code sections (such as interrupt service routines
and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but
the speed can be increased by 30% over Thumb mode.

 On-chip Flash Memory
The LPC2141/42/44/46/48 incorporates a 32kB, 64kB, 128kB, 256kB and 512kB

flash memory system respectively. This memory may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-
chip boot loader, flash memory available for user’s code on LPC2141/42/44/46/48 is 32 kB,
64kB, 128kB, 256kB and 500kB respectively. The LPC2141/42/44/46/48 flash memory
provides a minimum of 100,000 erase/write cycles and 20 years of data-retention.
 On-Chip Static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide
8kB, 16kB and 32kB of static RAM respectively. In case of LPC2146/48 only, an 8kB
SRAM block intended to be utilized mainly by the USB can also be used as a general purpose
RAM for data storage and code storage and execution.
 Interrupt Controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-
vectored IRQ as defined by programmable settings. The programmable assignment scheme
means that priorities of interrupts from the various peripherals can be dynamically assigned
and adjusted.
Fast interrupt request (FIQ) has the highest priority. If more than one request is
assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request is classified as
FIQ, because then the FIQ service routine does not need to branch into the interrupt service
routine but can run from the interrupt vector location. If more than one request is assigned to
the FIQ class, the FIQ service routine will read a word from the VIC that identifies which
FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be
assigned to this category. Any of the interrupt requests can be assigned to any of the 16
vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller, but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.
3.1.5 PIN CONTROL BLOCK
The pin connect block allows selected pins of the microcontroller to have more than
one function. Configuration registers control the multiplexers to allow connection between
the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The Pin Control Module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment. After reset all pins of Port 0 and 1 are
configured as input with the following exceptions: If debug is enabled, the JTAG pins will
assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace
functionality. The pins associated with the I2C0 and I2C1 interface are open drain.

3.1.6 FAST GENERAL PURPOSE PARALLEL I/O (GPIO)
Device pins that are not connected to a specific peripheral function are controlled by
the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000
 Devices
 GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
 Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
 All GPIO registers are byte addressable.
 Entire port value can be written in one instruction.
 Features
 Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
 Direction control of individual bits.
 Separate control of output set and clear.
 All I/O default to inputs after reset.
3.1.7 10-BIT ADC
The LPC2141/42 contains one and the LPC2144/46/48 contains two analog to digital
converters. These converters are single 10-bit successive approximation analog to digital
converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number
of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
 Features
 10 bit successive approximation analog to digital converter.
 Measurement range of 0 V to VREF (2.0 V ≤ VREF ≤ VDDA).
 Each converter capable of performing more than 400,000 10-bit samples per second.
 Every analog input has a dedicated result register to reduce interrupt overhead.
 Burst conversion mode for single or multiple inputs.

 Optional conversion on transition on input pin or timer match signal.

 Global Start command for both converters (LPC2142/44/46/48 only).
3.1.8 10-BIT DAC
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The
maximum DAC output voltage is the VREF voltage.
 Features
 10-bit DAC.
 Buffered output.
 Power-down mode available.
3.1.9 USB 2.0 DEVICE CONTROLLER
The USB is a 4-wire serial bus that supports communication between a host and a
number (127max) of peripherals. The host controller allocates the USB bandwidth to attached
devices through a token based protocol. The bus supports hot plugging, unplugging, and
dynamic configuration of the devices. All transactions are initiated by the host controller.
The LPC2141/42/44/46/48 is equipped with a USB device controller that enables

12Mbit/s data exchange with a USB host controller. It consists of a register interface, serial
interface engine, endpoint buffer memory and DMA controller. The serial interface engine
decodes the USB data stream and writes data to the appropriate end point buffer memory.
The status of a completed USB transfer or error condition is indicated via status registers. An
interrupt is also generated if enabled.
A DMA controller (available in LPC2146/48 only) can transfer data between an

endpoint buffer and the USB RAM.
 Features
 Fully compliant with USB 2.0 Full-speed specification.
 Supports 32 physical (16 logical) endpoints.
 Supports control, bulk, interrupt and isochronous endpoints.

 Scalable realization of endpoints at run time.

 Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
 RAM message buffer size based on endpoint realization and maximum packet size.
 Supports SoftConnect and GoodLink LED indicator. These two functions are sharing
one pin.
 Supports bus-powered capability with low suspend current.
 Supports DMA transfer on all non-control endpoints (LPC2146/48 only).
 One duplex DMA channel serves all endpoints (LPC2146/48 only).
 Allows dynamic switching between CPU controlled and DMA modes (only in
 LPC2146/48).
 Double buffer implementation for bulk and isochronous endpoints.
3.1.10 UARTS
The LPC2141/42/44/46/48 each contains two UARTs. In addition to standard transmit

and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control
handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in
PC2141/42/44/46/48introduce a fractional baud rate generator for both UARTs, enabling
these microcontrollers to achieve standard baud rates such as 115200 with any crystal
frequency above 2MHz. In addition, auto-CTS/RTS flow-control functions are fully
implemented in hardware (UART1 in LPC2144/46/48 only).
 Features
 16 byte Receive and Transmit FIFOs.
 Register locations conform to ‘550 industry standard.
 Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
 Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
 Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
 LPC2144/46/48 UART1 equipped with standard modem interface signals. This
module also provides full support for hardware flow control (auto-CTS/RTS).

3.1.11 I2C-BUS SERIAL I/O CONTROLLER
The LPC2141/42/44/46/48 each contains two I2C-bus controllers. The I2C-bus is

bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial
data line (SDA). Each device is recognized by a unique address and can operate as either a
receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive
and send information (such as memory)). Transmitters and/or receivers can operate in either
master or slave mode, depending on whether the chip has to initiate a data transfer or is only
addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus
master connected to it.
The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates upto 400 Kbit/s
(Fast I2C-bus).
 Features
 Compliant with standard I2C-bus interface.
 Easy to configure as master, slave, or master/slave.
 Programmable clocks allow versatile rate control.
 Bidirectional data transfer between masters and slaves.
 Multi-master bus (no central master).
 Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
 Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
 Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
3.1.12 SSI SERIAL I/O CONTROLLER
The LPC2141/42/44/46/48 each contains one SPI controller. The SPI is a full duplex
Serial interface, designed to handle multiple masters and slaves connected to a given bus.
Only a single master and a single slave can communicate on the interface during a given.
Data transfer. During a data transfer the master always sends a byte of data to the slave, And
the slave always sends a byte of data to the master.

 Features
 Compliant with Serial Peripheral Interface (SPI) specification.
 Synchronous, Serial, Full Duplex, Communication.
 Combined SPI master and slave.
 Maximum data bit rate of one eighth of the input clock rate.
3.1.13 SSP SERIAL I/O CONTROLLER
The LPC2141/42/44/46/48 each contains one SSP. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. However, only a single master and a single slave can communicate on the
bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4
bits to 16 bits of data flowing from the master to the slave and from the slave to the master.
Often only one of these data flows carries meaningful data.
 Features
 Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s Micro
wire buses.
 Synchronous serial communication.
 Master or slave operation.
 8-frame FIFOs for both transmit and receive.
 Four bits to 16 bits per frame.
3.1.14 GENERAL PURPOSE TIMERS/EXTERNAL EVENT COUNTERS
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs to
trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The
LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum

external pulse is equal or longer than a period of the PCLK. In this configuration, unused
capture lines can be selected as regular timer capture inputs, or used as external interrupts.
 Features
 A 32-bit timer/counter with a programmable 32-bit prescaler.
 External event counter or timer operation.
 Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
 Four 32-bit match registers that allow:
 Continuous operation with optional interrupt generation on match.
 Stop timer on match with optional interrupt generation
 Reset timer on match with optional interrupt generation.
 Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
 Set LOW on match.
 Set HIGH on match.
 Toggle on match.
 Do nothing on match
3.1.15 WATCHDOG TIMER
The purpose of the watchdog is to reset the microcontroller within a reasonable

amount of time if it enters an erroneous state. When enabled, the watchdog will generate a
system reset if the user program fails to ‘feed’ (or reload) the watchdog within a
predetermined amount of time.
 Features
 Internally resets chip if not periodically reloaded.
 Debug mode.
 Enabled by software but requires hardware reset or a watchdog reset/interrupt to be
disabled.
 Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

 Flag to indicate watchdog reset.

 Programmable 32-bit timer with internal pre-scaler.
 Selectable time period from (TPCLK × 256 × 4) to (TPCLK × 232 × 4) in multiples of
TPCLK×4.
3.1.16 REAL-TIME CLOCKS
The RTC is designed to provide a set of counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it suitable
for battery powered systems where the CPU is not running continuously (Idle mode).
 Features
 Measures the passage of time to maintain a calendar and clock.
 Ultra-low power design to support battery powered systems.
 Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
 Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. Programmable reference clock divider
allows fine adjustment of the RTC.
 Dedicated power supply pin can be connected to a battery or the main 3.3 V.
3.1.17 PULSE WIDTH MODULATOR
The PWM is based on the standard timer block and inherits all of its features,
although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is
designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to
be used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output.
One match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge controlled
PWM outputs require only one match register each, since the repetition rate is the same for
all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at
the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be
used to provide a PWM output with both edges controlled. Again, the MR0 match register
controls the PWM cycle rate. The other match registers control the two PWM edge positions.
Additional double edge controlled PWM outputs require only two match registers each, since
the repetition rate is the same for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising
and falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge
occurs prior to the rising edge).
 Features
 Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
 The match registers also allow:
 Continuous operation with optional interrupt generation on match.
 Stop timer on match with optional interrupt generation.
 Reset timer on match with optional interrupt generation.
 Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
 Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs
will occur at the same repetition rate.

 Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
 Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
 May be used as a standard timer if the PWM mode is not enabled.
 A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
3.1.18 SYSTEM CONTROL
 Crystal Oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to

25MHz.The oscillator output frequency is called fosc and the ARM processor clock
frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the
same value unless the PLL is running and connected.
 PLL (Phase Locked Loop)
The PLL accepts an input clock frequency in the range of 10 MHz to 25MHz. The
Input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice,
the multiplier value cannot be higher than 6 on this family of microcontrollers due to the
upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz,
so there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100μs.

 Reset and Wake up Timer
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog
reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion
of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external reset is de-
asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0,
which is the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned off
during Power-down mode, any wake-up of the processor from Power-down mode makes use
of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether
it is safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on many
factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
 Brown out Detector
The LPC2141/42/44/46/48 includes 2-stage monitoring of the voltage on the VDD

pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This
signal can be enabled for interrupt; if not, software can monitor the signal by reading
dedicated register.

The second stage of low voltage detection asserts reset to inactivate

theLPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6V. This reset
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down
below 1V, at which point the POR circuitry maintains the overall reset. Both the 2.9V and
2.6V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9V
detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
 Code Security
This feature of the LPC2141/42/44/46/48 allows an application to control whether it

can be debugged or protected from observation. If after reset on-chip boot loader detects a
valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will
be disabled and thus the code in flash will be protected from observation. Once debugging is
disabled, it can be enabled only by performing a full chip erase using the ISP.
 External Interrupt Inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External

Interrupt Inputs as selectable pin functions. When the pins are combined, external events can
be processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor from Power-down mode. Additionally capture
input pins can also be used as external interrupts without the Option to wake the device up
from Power-down mode.
 Memory Mapping Control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash
memory, or to the on-chip static RAM. This allows code running in different memory spaces
to have control of the interrupts.

 Power Control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and
Power-down mode. In Idle mode, execution of instructions is suspended until either a reset
or interrupt occurs. Peripheral functions continue operation during Idle mode and may
generate interrupts to cause the processor to resume execution. Idle mode eliminates power
used by the processor itself, memory systems and related controllers, and internal buses. In
Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are preserved
throughout Power-down mode and the logic levels of chip output pins remain static. The
Power-down mode can be terminated and normal operation resumed by either a reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Power-down mode reduces chip Power consumption to
nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the
on-chip RTC will enable the microcontroller to have the RTC active during Power-down
mode. Power-down current is increased with RTC active. However, it is significantly lower
than in idle mode.
A Power Control for Peripherals feature allows individual peripherals to be turned off
if they are not needed in the application, resulting in additional power savings during active
and idle mode.
 VPB (VLSI Peripheral Bus)
The VPB divider determines the relationship between the processor clock (CCLK)
and the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The
first is to provide peripherals with the desired PCLK via VPB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be
slowed down to 1⁄2 to 1⁄4 of the processor clock rate. Because the VPB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the VPB
divider control registers reside on the VPB bus), the default condition at reset is for the VPB
bus to run at 1⁄4 of the processor clock rate. The second purpose of the VPB divider is to
allow power savings when an application does not require any peripherals to run at the full
processor rate. Because the VPB divider is connected to the PLL output, the PLL remains
active (if it was running) during Idle mode.

3.1.19 EMULATION AND DEBUGGING
The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port.
A trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interface peripherals residing on Port 0 are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
 Embedded ICE
Standard ARM Embedded ICE logic provides on-chip debug support. The debugging
of the target system requires a host computer running the debugger software and an
Embedded ICE protocol converter. Embedded ICE protocol converter converts the Remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) function built-in. The
DCC allows a program running on the target to communicate with the host debugger or
another separate host without stopping the program flow or even entering the debug state.
The DCC is accessed as a co-processor 14 by the program running on the

ARM7TDMI-Score. The DCC allows the JTAG port to be used for sending and receiving
data without affecting the normal program flow. The DCC data and control registers are
mapped in to addresses in the Embedded ICE logic.
 Embedded Trace
Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the external
pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply
embedded processor cores. It outputs information about processor execution to the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system
bus. It compresses the trace information and exports it through a narrow trace port. An
external trace port analyzer must capture the trace information under software debugger
control. Instruction trace (or PC trace) shows the flow of execution of the processor and
provides a list of all the instructions that were executed. Instruction trace is significantly
compressed by only broadcasting branch addresses as well as a set of status signals that

indicate the pipeline status on a cycle by cycle basis. Trace information generation can be
controlled by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.
 Real Monitor
Real Monitor is a configurable software module, developed by ARM Inc., which

enables real-time debug. It is a lightweight debug monitor that runs in the background while
users debug their foreground application. It communicates with the host using the DCC,
which is present in the Embedded ICE logic. The LPC2141/42/44/46/48 contain a specific
configuration of Real Monitor software programmed into the on-chip flash memory.
3.2 GSM (GLOBAL SYSTEM FOR MOBILE COMMUNICATION)
Global System for Mobile (GSM) is a second generation cellular standard developed
to cater voice services and data delivery using digital modulation.
3.2.1 TECHNICAL DETAILS
Global System for Mobile communications is the most popular standard for mobile
phones in the world. Its promoter, the GSM Association, estimate that 82% of the global
mobile market uses the standard. GSM is used by over 2 billion people across more than 212
countries and territories. Its ubiquity makes international roaming very common between
mobile phone operators, enabling subscribers to use their phones in many parts of the world.
GSM has used a variety of voice codecs to squeeze 3.1 kHz audio into between 5.6
and 13Kbit/s. Originally, two codecs, named after the types of data channel they were
allocated, were used, called Half Rate (5.6Kbit/s) and Full Rate (13Kbit/s). These used a
system based upon linear predictive coding (LPC). In addition to being efficient with bit
rates, these codecs also made it easier to identify more important parts of the audio, allowing
the air interface layer to prioritize and better protect these parts of the signal.

There five different cell sizes in a GSM network-macro, micro, Pico, femto and
umbrella cells. The coverage area of each cell varies according to the implementation
environment. Macro cells can be regarded as cells where the base station antenna is installed
on a mast or a building above average roof top level. Micro cells are cells whose antenna
height is under average roof top level; they are typically used in urban areas. Picocells are
small cells whose coverage diameter is a few dozen meters; they are mainly used indoors.
Femtocells are cells designed for use in residential or small business environments and
connect to the service provider’s network via a broadband internet connection. Umbrella cells
are used to cover shadowed regions of smaller cells and fill in gaps in coverage between
those cells.
Cell horizontal radius varies depending on antenna height, antenna gain and
propagation conditions from a couple of hundred meters to several tens of kilometers. The
longest distance the GSM specification supports in practical use is 35 kilometers (22 mi).
Indoor coverage is also supported by GSM and may be achieved by using an indoor
picocell base station, or an indoor repeater with distributed indoor antennas fed through
power splitters, to deliver the radio signals from an antenna outdoors to the separate indoor
distributed antenna system. These are typically deployed when a lot of call capacity is needed
indoors, for example in shopping centres or airports. However, this is not a prerequisite, since
indoor coverage is also provided by in-building penetration of the radio signals from nearby
cells.
The modulation used in GSM is Gaussian minimum-shift keying (GMSK), a kind of

continuous-phase frequency shift keying. In GMSK, the signal to be modulated onto the
carrier is first smoothed with a Gaussian low-pass filter prior to being fed to a frequency
modulator, which greatly reduces the interference to neighboring channels (adjacent channel
interference).
3.2.2 SUBSCRIBER IDENTITY MODULE (SIM)
One of the key features of GSM is the Subscriber Identity Module (SIM), commonly
known as a SIM card. The SIM is a detachable smart card containing the user’s subscription
information and phonebook. This allows the user to retain his or her information after
switching handsets. Alternatively, the user can also change operators while retaining the
handset simply by changing the SIM. Some operators will block this by allowing the phone to
use only a single SIM, or only a SIM issued by them; this practice is known as SIM locking,
and is illegal in some countries.
A subscriber can usually contact the provider to remove the lock for a fee, utilize
private services to remove the lock, or make use of ample software and websites available on
the Internet to unlock the handset themselves. While most web sites offer the unlocking for a
fee, some do it for free. The locking applies to the handset, identified by its International
Mobile Equipment Identity (IMEI) number, not o the account (which is identified by the SIM
card). It is always possible to switch to another (non-locked) handset if such a handset is
available.
3.2.3 GSM MODEMS
A modem is a communication device that converts binary into analog acoustic signals
for transmission over telephone lines and converts these acoustics signals back into binary
form at the receiving end. Conversion to analog signal is known as modulation; conversion
back to binary signal is known as demodulation. In the terminology used in the RS-232C
communication standard, modems are DCEs, which mean the connected at one end to a DTE
(e.g. computer) device. Low-speed modems are designed to operate asynchronously. Each
data frame conforms an asynchronous transmission mechanism.
High-speed modems as well as leased-lines modems use synchronous transmission.

The two modems use a common time base and operate continuously at substantially the same
frequency and the phase relationship by circuit that monitors the connection.
A half-duplex modem must alternately send and received signals. Half-duplex allows
more of the channel bandwidth to be put to use but slows data communications. A full-duplex
modem can simultaneously handle two signals using two carriers to transmit and receive data.
Each carrier uses a half of the bandwidth available to it and its modulation.
ASK is not used For data communications because it is very susceptible to electrical
noise interference. Low-speed modems use FSK, higher speed modems use PSK, and the
very high speed modems use a conjunction of ASK and PSK.

The SMS/MMS Gateway requires a connection to an SMSC (Short Messaging

Service Centre) to interface with SMS and MMS networks. An SMSC connection can consist
of one or more of the following:
 GSM Modem – A GSM modem or phone connected to a PC serial port (or to a USB
port with an appropriate modem driver).
 SMPP (Short Message Peer to Peer Protocol) – A TCP/IP connection over the internet
or a private network to a service that supports v3.3 or v3.4 of the SMPP protocol.
 UCP/EMI (Universal Computer Protocol/ External Machine Interface) – A TCP/IP
connection over the internet or a private network to a service that supports v3.5 or v4.0
of the UCP/EMI protocol.
 HTTP (Hyper Text Transfer Protocol, e.g., the standard protocol for the “web”) – A
TCP/IP connection over the internet or private network to a service that accepts SMS
messages via an HTTP “GET” based protocol allows you to chain multiple Now
SMS/MMS Gateways together.)
Figure 3.2: GSM modem (Sim 300)
3.2.4 F-BUS COMMANDS
The F-Bus is bi-directional serial type bus running at 115,200bps, 8 data bits. The
serial cable contains electronics for level conversion and therefore requires power. The first
thing to do is supply power to the cable electronics and this is done by setting the DTR (Data
Terminal Ready) pin and clearing the RTS (Request to Send) pin.

For all microcontroller DIYer’s out there, connect the DTR pin to a +3 to 12 Volt
supply and RTS to a -3 to -12Volt supply. The easy way to achieve this is by using a Max232
or similar transceiver for the RS232 TX and RX pins and then connecting the DTR pin on the
serial cable to the V+ pin on the Max232. Do the same for the RTS, however connect it to the
V- pin on the Max232. The V+ and V- pins are derived from internal charge pumps that
double the input voltage. i.e. For a 5V Max232, the V+ will +10V and the V- will be -10V. I
hope this clears up this issue for most people.
The next step is to synchronize the UART in the phone with your PC or
microcontroller. This is done by sending a string of 0x55 or ‘U’ 128 times. Simple! The bus
is now ready to be used for sending frames.
GSM (Global System for Mobile communication) is a digital mobile telephony

system that is widely used in Europe and other parts of the world. GSM uses a variation of
time division multiple access TDMA) and is the most widely used of the three digital
wireless telephony technologies (TDMA, GSM, and CDMA). GSM digitizes and compresses
data, then sends it down a channel with two other streams of user data, each in its own time
slot. It operates at either the 900 MHz or 1800 MHz frequency band.
Mobile services based on GSM technology were first launched in Finland in 1991.
Today, more than 690 mobile networks provide GSM services across 213 countries and GSM
represents 82.4% of all global mobile connections. According to GSM World, there are now
more than 2 billion GSM mobile phone users worldwide. GSM World references China as
"the largest single GSM market, with more than 370 million users, followed by Russia with
145 million, India with 83 million and the USA with 78 million users."
Since many GSM network operators have roaming agreements with foreign operators,
users can often continue to use their mobile phones when they travel to other countries. SIM
cards (Subscriber Identity Module) holding home network access configurations may be
switched to those will metered local access, significantly reducing roaming costs while
experiencing no reductions in service.
GSM, together with other technologies, is part of the evolution of wireless mobile
telecommunications that includes High-Speed Circuit-Switched Data (HCSD), General

Packet Radio System (GPRS), Enhanced Data GSM Environment (EDGE), and Universal
Mobile Telecommunications Service.
3.2.5 WORKING OF GSM MODEM
 Sending SMS Messages from a microcontroller using a GSM Modem:\
A GSM modem is a wireless modem that works with GSM wireless networks. A
wireless modem is similar to a dial-up modem. The main difference is that a wireless modem
transmits data through a wireless network whereas a dial-up modem transmits data through a
copper telephone line. Most mobile phones can be used as a wireless modem.
To send SMS messages, first place a valid SIM card into a GSM modem, which is
then connected to microcontroller by RS232 cable. After connecting a GSM modem to a
microcontroller, you can control the GSM modem by sending instructions to it. The
instructions used for controlling the GSM modem are called AT commands. GSM modems
support a common set of standard AT commands. In addition to this common set of standard
AT commands, GSM modems support an extended set of AT commands. One use of the
extended AT commands is to control the sending and receiving of SMS messages.

 The following table lists the AT commands that are related to the writing and
sending of SMS messages
AT command Meaning
+CMGS Send message
+CMSS Send message from storage
+CMGW Write message to memory
+CMGD Delete message
+CMGC Send command
+CMMS More messages to send
Table 3.2: GSM AT Commands
One way to send AT commands to a GSM modem is to use a program. A program's

function is like this:
It sends the characters you typed to the GSM modem. It then displays the response it
receives from GSM modem on the screen.

 Below shows a simple example that demonstrates how to use AT commands
AT
OK
AT+CMGF=1
OK
AT+CMGW="+85291234567"
> A simple demo of SMS text messaging.
+CMGW:1
OK
AT+CMSS=1
+CMSS:20
OK
 Here is a description of what is done in the above example
Line 1: "AT" is sent to the GSM modem to test the connection. The GSM modem sends back
the result code "OK" (line 2), which means the connection between the program and the
GSM modem works fine.
Line 3: The AT command +CMGF is used to instruct the GSM modem to operate in SMS
text mode. The result code "OK" is returned (line 4), which indicates the command line
"AT+CMGF=1" has been executed successfully. If the result code "ERROR" is returned, it is
likely that the GSM modem does not support the SMS text mode. To confirm, type
"AT+CMGF=?" in the program. If the response is "+CMGF: (0, 1)" (0=PDU mode and
1=text mode), then SMS text mode is supported. If the response is "+CMGF: (0)", then SMS
text mode is not supported.
Line 5 and 6: The AT command +CMGW is used to write an SMS text message to the
message storage of the GSM modem . "+85291234567" is the recipient mobile phone
number.
Line 7: "+CMGW: 1" tells us that the index assigned to the SMS text message is 1. It
indicates the location of the SMS text message in the message storage.

Line 9: The result code "OK" indicates the execution of the AT command +CMGW is
successful.
Line 10: The AT command +CMSS is used to send the SMS text message from the message
storage of the GSM modem. "1" is the index of the SMS text message obtained from line 7.
Line 11: "+CMSS: 20" tells us that the reference number assigned to the SMS text message
is 20.
Line 13: The result code "OK" indicates the execution of the AT command +CMSS are
successful. By using the above procedure message is sent by the GSM modem.
3.2.6 CHARACTERISTICS OF GSM STANDARD
 Fully digital system using 900, 1800 MHz frequency band.

 TDMA over radio carriers (200 KHz carrier spacing).
 8 full rate or 16 half rate TDMA channels per carrier.
 User/terminal authentication for fraud control.
 Encryption of speech and data transmission over the radio path.
 Full international roaming capability.
 Low speed data services (upto 9.6Kb/s).
 Compatibility with ISDN.
 Support of Short Message Service (SMS).
3.2.7 ADVANTAGES OF GSM OVER ANALOG SYSTEM
 Capacity increases.
 Reduced RF transmission power and longer battery life.
 International roaming capability.
 Better security against fraud (through terminal validation and user authentication).
 Encryption capability for information security and privacy.
 Compatibility with ISDN, leading to wider range of service.

3.2.8 GSM APPLICATIONS
 Mobile telephony.
 GSM-R.
 Value Added Services.
 Telemetry System
 Fleet management.
 Automatic meter reading.
 Toll Collection.
 Remote control and fault reporting of DG sets.
3.3 RFID
3.3.1 RFID CONCEPT
The RFID technology is a means of gathering data about a certain item without the
need of touching or seeing the data carrier, through the use of inductive coupling or
electromagnetic waves. The data carrier is a microchip attached to an antenna (together called
transponder or tag), the latter enabling the chip to transmit information to a reader (or
transceiver) within a given range, which can forward the information to a host computer. One
important feature enabling RFID for tracking objects is its capability to provide unique
identification.
3.3.2 THE FOUR CORE COMPONENTS OF AN RFID SYSTEM
An RFID system has four basic components:

 A tag which is composed of a semiconductor chip and an antenna.
 An interrogator (sometimes called a read/write device), which is composed of an
antenna, a RF electronics module, and a control electronics module.
 A controller (sometimes called a host), which most often takes the form of a PC or a
workstation running database and control (often called middleware) software.
 An antenna, which converts electrical power to RF power.

Figure 3.3(a): Basic Building blocks of an RFID system
3.3.3 RFID TAGS
The basic function of an RFID tag is to store data and transmit data to the
interrogator. At its most basic, a tag consists of an electronics chip and an antenna
encapsulated in a package to form a usable tag, such as a packing label that might be attached
to a box.
Figure 3.3(b): RFID Tag
3.3.4 RFID INTERROGATORS (READER)
An RFID interrogator acts as a bridge between the RFID tag and the controller and
has a few basic functions to perform:
 Read the data contents of an RFID tag

 Write data to the tag (in the case of smart tags)
 Relay data to and from the controller
 Power-up the tag (in the case of passive tags).

3.3.5 SPECIFICATIONS
Frequency 125 KHz
Reading distance >= 50 mm
Interface UART
Antenna Built in / External
Supply Voltage 5V
Operating Temperature -10°C to +50°C
Tag Types Unique, TK 5530
Output Format ASCII, Wiegand 26
Table 3.3: Specifications
3.4 LCD (16x4 ALPHANUMERIC DISPLAY)
3.4.1 DESCRIPTION
Liquid crystal display is very important device in embedded system. It offers high
flexibility to user as he can display the required data on it. But due to lack of proper approach
to LCD interfacing many of them fail. Many people consider LCD interfacing a complex job
but according to me LCD interfacing is very easy task, you just need to have a logical
approach. This page is to help the enthusiast who wants to interface LCD with through
understanding. Copy and Paste technique may not work when an embedded system engineer
wants to apply LCD interfacing in real world projects.
In recent years the LCD is finding widespread use replacing LEDs this is due to
following reasons
 The declining prices of LCDs

 The ability to display numbers, characters and graphics. This is in contrast to LEDs,
which are limited to numbers and few characters.

Figure 3.4(a): LCD display
A touch screen is a special type of visual display unit with a screen which is Sensitive
to pressure or touching. The screen can detect the position of the point of touch.
Touch technology turns a CRT, flat panel display or flat surface into a dynamic data
entry that replays both keyboard and mouse. In addition to eliminating these separate data
entry devices, touch offers an intuitive interface.
3.4.2 DEFINITIONS
 Resolution: The horizontal and vertical size expressed in pixels (e.g., 1024x768).
 Dot pitch: The distance between the centres of two adjacent pixels. The smaller the
dot pitch size, the less granularity is present, resulting in a sharper image. Dot pitch
may be the same both vertically and horizontally, or different (less common).
 Viewable size: The size of an LCD panel measured on the diagonal (more specifically
known as active display area).
 Response time: The minimum time necessary to change a pixel's colour or brightness.

3.4.3 TOUCH SCREEN
 Description
A touch screen is a computer display screen that is also an input device. The screens
are sensitive to pressure; a user interacts with the computer by touching pictures or words on
the screen.
There are three types of touch screen technology:
 Resistive: A resistive touch screen panel is coated with a thin metallic electrically
conductive and resistive layer that causes a change in the electrical current which is
registered as a touch event and sent to the controller for processing. Resistive touch screen
panels are generally more affordable but offer only 75% clarity and the layer can be
damaged by sharp objects. Resistive touch screen panels are not affected by outside
elements such as dust or water.
 Surface wave: Surface wave technology uses ultrasonic waves that pass over the touch
screen panel. When the panel is touched, a portion of the wave is absorbed. This change in
the ultrasonic waves registers the position of the touch event and sends this information to
the controller for processing. Surface wave touch screen panels are the most advanced of
the three types, but they can be damaged by outside elements.
 Capacitive: A capacitive touch screen panel is coated with a material that stores electrical
charges. When the panel is touched, a small amount of charge is drawn to the point of
contact. Circuits located at each corner of the panel measure the charge and send the
information to the controller for processing. Capacitive touch screen panels must be
touched with a finger unlike resistive and surface wave panels that can use fingers
and stylus. Capacitive touch screens are not affected by outside elements and have high
clarity.

3.4.4 LCD INTERFACING
Sending commands and data to LCDs with a time delay:
Figure 3.4(b): LCD Interfacing
To send any command to the LCD, make pin RS=0. For data, make RS=1.Then place
a high to low pulse on the E pin to enable the internal latch of the LCD.
3.4.5 ADVANTAGES OF LCD
In recent years the LCD is finding widespread use replacing LEDs this is due to
following reasons
 The declining prices of LCDs

 The ability to display numbers, characters and graphics. This is in contrast to LEDs,
which are limited to numbers and few characters.

3.5 POWER SUPPLY
3.5.1 POWER SUPPLY UNIT
LPC2148 works on 3.3 V power supply. LM 117 can be used for generating 3.3 V
supply. However, basic peripherals like LCD, ULN 2003 (Motor Driver IC) etc. works on
5V. So AC mains supply is converted into 5V using below mentioned circuit and after that
LM 117 is used to convert 5V into 3.3V.
Figure 3.5(a): Block diagram for power supply.

Transformer: It is used to step down 230V AC to 9V AC supply and provides isolation

between power grids and circuit.
Rectifier: It is used to convert AC supply into DC.
Filter: It is used to reduce ripple factor of DC output available from rectifier end.
Regulator: It is used to regulate DC supply output. Here, Regulator IC 7805 is used to
provide fix 5V dc supply.
Figure 3.5(b): Circuit Diagram for Regulator

CHAPTER-4
SOFTWARE REQUIRMENT
4.1 Introduction to keilµVision3
The µVision3 IDE is a Windows-based software development platform that combines

a robust editor, project manager, and makes facility. µVision3 integrates all tools including
the C compiler, macro assembler, linker/locator, and HEX file generator. The µVision3 IDE
offers numerous features and advantages that help you quickly and successfully develop
embedded applications. They are easy to use and are guaranteed to help you achieve your
design goals.
 Features
 The µVision3 Simulator is the only debugger that completely simulates all on-chip
peripherals.
 Simulation capabilities may be expanded using the Advanced Simulation Interface
(AGSI).
 µVision3 incorporates project manager, editor, and debugger in a single environment.
 The µVision3 Device Database automatically configures the development tools for
the target microcontroller.
 The µVision3 IDE integrates additional third-party tools like VCS, CASE, and
FLASH/Device Programming.
 The ULINK USB-JTAG Adapter supports both Debugging and Flash programming
with configurable algorithm files.
 Identical Target Debugger and Simulator User Interface.
 The Code Coverage feature of the µVision3 Simulator provides statistical analysis of
your program's execution.

4.2 FLASH MAGIC
Flash Magic is a PC tool for programming flash based microcontrollers from NXP
using a serial protocol while in the target hardware Flash Magic is a feature-rich Windows
based tool for the downloading of code into NXP flash microcontrollers. It utilises a feature
of the microcontrollers called ISP, which allows the transfer of data serially between a PC
and the device. Flash Magic can erase devices, program them, read data and read and set
various configuration information. Rather than providing the basic features of ISP, Flash
Magic adds additional features and intelligence, allowing complex operations to be
performed. For example, erasing can be any collection of pages, blocks, the hex file to be
programmed or the entire device. Some devices store the ISP boot loader in flash memory, so
Flash magic implements methods to protect this code from being erased. Additional advanced
features of Flash Magic include the automatic programming of checksums, entering ISP
mode via a serial command, execution of Just in Time modules allowing endless flexibility in
the data programmed, control over RS232 signals to place devices into ISP mode, and control
over the timing of such signals. Flash Magic has been available for free for over six years and
supports all current 8-bit (8051), 16-bit (XA) and 32-bit (ARM) flash microcontrollers from
NXP.

4.3 EMBEDDED C
The trouble with projects done with assembly code is that they can be difficult to read
and maintain, especially if they are not well commented. Additionally, the amount of code
reusable from a typical assembly language project is usually very low. Use of a higher-level
language like C can directly address these issues. A program written in C is easier to read
than an assembly program.
Since a C program possesses greater structure, it is easier to understand and maintain.

Because of its modularity, a C program can better lend itself to reuse of code from project to
project. The division of code into functions will force better structure of the software and lead
to functions that can be taken from one project and used in another, thus reducing overall
development time. A high order language such as C allows a developer to write code, which
resembles a human’s thought process more closely than does the equivalent assembly code.
The developer can focus more time on designing the algorithms of the system rather than
having to concentrate on their individual implementation. This will greatly reduce
development time and lower debugging time since the code is more understandable.
By using a language like C, the programmer does not have to be intimately familiar
with the architecture of the processor. Additionally, code developed in C will be more
portable to other systems than code developed in assembly. Many target processors have C
compilers available, which support ANSI C.

CHAPTER-5
FLOW CHART AND ALGORITHM
5.1 ALGORITHM
 STEP 1: Start.
 STEP 2: Scan the RFID card (Smart Card) using RFID reader.
 STEP 3: Check if the Card is a valid card by comparing against the data stored in the
Central Database (Microprocessor temporary memory).
 STEP 4: If it is a valid card then Send a message to the Card holder stating that “Your
card has been accessed and please enter a Random Password” to the number stored in
database, else, if the card is not valid then end the Transaction.
 STEP 5: Wait for the reply from the card holder and ask the user to enter the Password
in the ATM machine.
 STEP 6: Compare the entered password and the Random Password sent by card holder.
 STEP 7: If both the password entered is same then proceed with the Transaction else
end the Transaction.
 STEP 8: User is presented with the Transaction menu and asked to enter the required
amount of withdrawal, after which another SMS is sent to user stating if the amount
entered is correct and if to proceed with Transaction then to enter the Pass-code given
by respective Banks.
 STEP 9: After receiving a valid Pass-code, the user is allowed to withdraw the amount.
 STEP 10: End

5.2 FLOWCHART FOR ATM SECURITY
Figure 5.2: Operation Flow Chart

CHAPTER-6
RESULT
6.1 TESTING AND OPERATION
Figure 6.1(a): Main View of the Project
The proposed system is implemented through the use of before mentioned

components and the final implemented result is as shown in the above figure.

 TESTING
Figure 6.1(b): Start up screen
The above figure shows the initial start up sequence of the Multi Account ATM
machine. After the multi-account RFID card has been swiped, an SMS alert stating that user
needs to enter any Random Password and sending it back to the system will enable further
transaction. As shown in figure 6.1(d), the user will be given a list of bank accounts the user
has enabled. After this selection, the user will be prompted to enter the Random Password
again in the ATM machine and if both the passwords match then user is given access to enter
the Withdrawal Amount.
Figure 6.1(c): ATM receives Random Password Figure 6.1(d): User is given a list of Bank

 CONCLUSION
When the required amount is entered in the ATM then the user is again asked for a
conformation code through SMS that is fixed for a particular bank. Finally, after the
conformation code is received and verified by the ATM then the user is allowed to withdraw
that particular amount.
Figure 6.1(e): Final Message

CHAPTER-7
ADVANTAGES & DISADVANTAGES
7.1 ADVANTAGES OF PROJECT
 Provides very good security to ATM users.

 Use of RFID allows only authorized users to use ATM facility.
 Alerts card holders during theft through GSM modem.
 Low cost and secure transaction is possible.
 There is not possible to duplicate the RFID card.
7.2 DISADVANTAGES OF PROJECT
 Difficulty for illiterates during transaction.

 If network fails, then it is not possible to transact.
 It requires more time during transaction.

CHAPTER-8
CONCLUSION AND FUTURE WORK
8.1 CONCLUSION
Thus the user can manage his/her multiple accounts in various banks with the help of
this single smart card which provides easy access reduces the complexity of managing more
than one ATM card and their passwords. It leads to avoiding transaction charges levied on the
users/ customers for transactions done in ATMs other than their respective banks. Production
cost of ATM cards can be reduced. The project is operationally feasible because here the cost
of each device is much lower compared to those products available in the market presently.
8.2 FUTURE WORK
 Can be implemented on existing ATM systems.
 We can embed a biometric scan in the smart card i.e. multi component card.
 This project can be implemented for office security, colleges, and hospitals and also
in parking system.

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Secured Money Transaction Using Multi Account Embedded ATM Card

Dept. of ECE, RLJIT 2013-2014 1

1.3 LITERATURE SURVEY

1.3.1 MULTI ACCOUNT EMBEDDED ATM CARD

Figure 1.3: Current existing system

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1.3.2 SECURE PIN ENTRY METHOD

Personal identification number (PIN) is a common method to authenticate a user for

1.3.3 REAL TIME SMS BASED SECURITY

Existing measures adopted by financial institutions require ATM card holders to

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1.3.4 CLOUD BASED ATM ENVIRONMENT

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2.1 PROPOSED SYSTEM

Figure 2.1: Proposed System

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2.2 MODEL BLOCK DIAGRAM

Figure 2.2: Model block diagram

2.3 WORKING PRINCIPLE

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3.1 ARM LPC2148 MICROCONTROLLER

The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit

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3.1.2 PIN DIAGRAM

Figure 3.1: Pin diagram of LPC2148

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 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

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3.1.4 FUNCTIONAL DESCRIPTION

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

The ARM7TDMI-S processor also employs a unique architectural strategy known as

The ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

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 On-chip Flash Memory

The LPC2141/42/44/46/48 incorporates a 32kB, 64kB, 128kB, 256kB and 512kB

 On-Chip Static RAM

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3.1.5 PIN CONTROL BLOCK

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3.1.6 FAST GENERAL PURPOSE PARALLEL I/O (GPIO)

3.1.7 10-BIT ADC

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 Optional conversion on transition on input pin or timer match signal.

3.1.8 10-BIT DAC

3.1.9 USB 2.0 DEVICE CONTROLLER

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables

A DMA controller (available in LPC2146/48 only) can transfer data between an

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 Scalable realization of endpoints at run time.

The LPC2141/42/44/46/48 each contains two UARTs. In addition to standard transmit

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3.1.11 I2C-BUS SERIAL I/O CONTROLLER

The LPC2141/42/44/46/48 each contains two I2C-bus controllers. The I2C-bus is

3.1.12 SSI SERIAL I/O CONTROLLER

Dept. of ECE, RLJIT 2013-2014 17

3.1.13 SSP SERIAL I/O CONTROLLER

3.1.14 GENERAL PURPOSE TIMERS/EXTERNAL EVENT COUNTERS

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

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3.1.15 WATCHDOG TIMER