Analog Integrated Circuits & Systems

Phase Locked Loop (PLL)

ELC401A – Fall 2017
Dr. Ahmed Nader

Department of Electronics and Communications Engineering

Faculty of Engineering – Cairo University
 Charge-Pump PLL

 PFD Implementation
 Basic Charge-Pump PLL (CP-PLL)
 Dynamics of CP-PLL
 Delay Locked Loop (DLL)
 Phase/Frequency Detector (PFD)

 Conceptual operation for a circuit that can detect both phase

and frequency differences
 PFD Sequential Implementation

 Difference between average values of QA and QB is the

quantity of interest
PFD Transfer Characteristic

KPD=??
 PFD Operation

 Difference in average will exhibit different polarity for

ωA > ωB and ωA < ωB
 PDF with Charge Pump (CP)

CP

 The gain of the CP is infinite !!

 For a finite Vcont, the phase error must be zero !!
 Example

• Effect of narrow pulses of QB on the behavior of PFD.

No much change in the overall behavior of the circuit
since the current flows between the 2 current sources
and no current goes to the capacitor (assuming I1=I2).
Basic Charge Pump PLL
 Linear Model of PDF/CP/LPF

2𝜋
∆∅ = ∆𝑡
𝑇
𝐼𝑃 𝐼 ∆∅
∆𝑉 = ∆𝑡= 𝑃 𝑇
𝐶𝑃 2𝜋𝐶𝑃
𝐼𝑃 ∆∅
Vout = t
2𝜋𝐶𝑃

• Discrete-time system (staircase) is approximated

by a continuous-time system (ramp)
 Linear Model of PDF/CP/LPF

Step Response

𝐼𝑃 ∆∅
𝑉𝑜𝑢𝑡 𝑠 = . 2
2𝜋𝐶𝑃 𝑠

𝑑𝑉𝑜𝑢𝑡
𝑉𝑖𝑚𝑝 𝑡 =
𝑑𝑡
Impulse Response
𝐼𝑃 ∆∅
𝑉𝑖𝑚𝑝 𝑠 = 𝑠𝑉𝑜𝑢𝑡 𝑠 = .
2𝜋𝐶𝑃 𝑠
Linear Model of CP-PLL

Type-II PLL

Stability?
How to Stabilize CP-PLL

Add a Zero
CP-PLL with Zero
 CP-PLL with Divider

• Divider degrades both stability

and settling of the PLL
• What to do?
Effect of VCO Jitter (Phase Noise)
 Advantages of Type-II CP-PLL

 Phase error due to finite frequency step is zero

(eliminate tough trade-off with stability)

 Acquisition range increased due to the usage of a

PFD instead of a PD