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Gate-All-Around Si Nanowire

Transistors (SNWTs) for


Extreme Scaling: Fabrication,
Characterization and Analysis

Ru Huang
Peking University (PKU)
Beijing 100871, China

1
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary

2
Introduction - 1/5

3
Introduction - 2/5
We are entering the multi-gate era!
• Intel’s 22nm is Tri-gate transistor

Source: M. Bohr and K. Mistry, http://www.intel.com

• What’s next?
4
Introduction - 3/5
Next: Gate-all-around Nanowire Transistor
Scalability
Gate-all-around
Upper Limit Gate
2 of TSi / LG Source All Drain
Ext. Around Ext.
-gate -gate cylindrical
rectangular
1 Double-
gate
FinFET  “the ideal transistor”
2/3 Tri-gate  best gate controllability
FinFET  relax the strict scaling
Number of Gates requirement of tOX and Tsi
1/2
2 3 3+ 4 4+

FinFET/Tri-gate Gate-all-around
Extreme
Fin Scaling Nanowire
Channels Channels
5
Introduction - 4/5
How to fabricate this device?
Did we know all about this kind of device?
• We already have the scaling theory for Tri-gate and GAA
• But, one cannot simply scale GAA properties to get
correct understanding of Si nanowire transistor
Strongly-confined quasi-1D structure fundamentally
different !
Carrier
Carrier
transport?
transport?

Reliability? Source Gate


Fabrication?
Fabrication? Drain
Reliability? Parasitics?
Parasitics?
Source Ext. Drain Ext.
3D 3D
System System
Quasi-1D System
Noise?
Noise?
Variability?
Variability?
Self-
Self-
heating?
heating?
6
Introduction - 5/5
 Fabricate this device from top-down approach
 Evaluate the key device characteristics for circuit
applications with confined quasi-1D structure
• clarify the related physics
• find the challenges for optimization
• new characterizing techniques
• …… Transport? Transport?
Reliability?
R. Wang, et al., IEDM 2008 Parasitics?
Parasitics?
Reliability? R. Wang, et al, T-ED 2008

J. Zhuge, et al., T-ED 2008


R. Wang, et al., IEDM 2007
J. Zou, et al, T-ED 2011
L. Zhang, et al., IEDM 2008
L. Zhang, et al., VLSI 2009 Fabrication?
Fabrication?
C. Liu, et al., T-ED 2010
C. Liu, et al., IEDM 2011 Y. Tian, et al., IEDM 2007 Noise?
Noise?
Variability?
Variability? J. Zhuge, et al., EDL 2008
J. Zhuge, et al., APL 2009
C. Liu, et al, IEDM 2011
J. Zhuge,et al., IEDM 2009 Self-heating?
R. Wang, et al, IEDM 2010
C. Liu et al, IEDM 2011
T. Yu, et al., T-ED 2010
R. Wang, et al., IEDM 2008
J. Zhuge, et al., T-Nano 2008
GAA SNWTs
R. Wang, et al, T-ED 2011. X. Huang, et al., ISQED 2012 7
Key Messages: Preview
• Fabrication and integration: almost Manufacturable
• Recent advances in understanding SNWTs
– Intrinsic carrier transport: near-ballistic transport

8
Key Messages: Preview
• Fabrication and integration: almost Manufacturable
• Recent advances in understanding SNWTs
– Intrinsic carrier transport: near-ballistic transport
90 GAA SNWT (twin NWs) [x] [this work]
80 bulk MOSFET [x]
[1]
SiC S/D FinFET [x]
[2]
70 NW FETs plannar DG MOSFET [3][x]
60
bulk MOSFET (simulation) [x][4]
Tri-gate SNWT (single NW) [5][x]
BSAT(%)

50
40
Double-gate FETs
30
20 [1] J. Jeon, et al., VLSI 2009, p. 48
Planar [2] T.-Y. Liow et al., IEDM 2006, p. 473
10 [3] V. Barral et al., Solid-State Electron.,
bulk FETs 51, p. 537, 2007.
0
10 100 500 [4] Y. Taur et al., IEDM 1998, p. 789
LG(nm) [5] S.D Suk et al., VLSI 2009, p. 142

• Better BSAT than planar and double-gate devices


9
Key Messages: Preview
• Fabrication and integration: almost Manufacturable
• Recent advances in understanding SNWTs
– Intrinsic carrier transport: near-ballistic transport
– Low-frequency noise: slightly degraded and fluctuated
– Parasitic effects (R and C): should be optimized
– Self-heating effects: observable when dNW<14nm
– Variability: holds the record low (static) variations
– Reliability: HCI is OK, but NBTI needs more studies
• Recent nanowire circuit demonstrations: On the way
– SRAM, ring oscillator, current mirror…
• Other benefits for 3D integration, MtM applications…
• Summary: We are facing a great opportunity!
10
Key Messages: Preview
• Fabrication and integration: almost Manufacturable
• Recent advances in understanding SNWTs
– Intrinsic carrier transport: near-ballistic transport
– Low-frequency noise: slightly degraded and fluctuated
– Parasitic effects (R and C): should be optimized
– Self-heating effects: observable when dNW<14nm
– Variability: holds the record low (static) variations
– Reliability: HCI is OK, but NBTI needs more studies
• Recent nanowire circuit demonstrations: On the way
– SRAM, ring oscillator, current mirror…
• Other benefits for 3D integration, MtM applications…
• Summary: We are facing a great opportunity!
11
Outline
• Introduction
• Fabrication and integration
– based on bulk (our focus)
– based on SOI
– with stacked NW channel
• Recent advances in understanding SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
12
Top-down process for SNWTs
• Key points
– NW formation
– NW releasing or suspending

TiN
Po l
y-G PKU LETI
ate
Poly Silicon

SiO2 IBM
B OX
Oxide S. Bangsaruntip
Gox SNW NUS
10 nm Silicon Nanowire
et al., IEDM, 2009
Si Purdue Oxide

Samsung IBM
NUS 10 nm Silicon Nanowire

TIT
IEDM, 2005 IEDM, 2006 IEDM, 2007 C. Dupré et al.,
Samsung NUS PKU IEDM, 2008
LETI

Sato S, et al., SSE,13


2010, TIT
Bulk SNWTs - Samsung method

HM trimming

HM Trimming for NW definition diameter = 10nm


tOX=3.5nm
SiGe/Si stack epi for releasing TiN metal-gate
S.D.Suk et al., IEDM, 2005 14
Self-aligned bulk SNWTs by epi-
free compatible process

 based on bulk substrate


 NW originally defined by e-beam, thinning
and cylinder channel shaping by self-limiting
oxidation and annealing
 NW released by isotropic etch with HM

Y. Tian et al., IEDM, 2007, PKU


15
Oxid
e

Oxid
e
Sour
ce

Drai
n

Si S
ubs
trate

Gate trench
Nitride fin patterning & etching after oxide
S/D implantation deposition

Nitride spacer formation Silicon fin etching


16
Silicon etching Si etching under
surrounding fin channel channel

Hard mask removal BPT(bottom parasitic


transistor) Stopper layer
17
Cylindrical shaping Gate oxidation &Poly-Si
gate formation
• diameter = 10nm
• tOX=5nm
• Poly gate
18
NW formation
NW shaping and diameter controlling
Patterning for Oxidation   

original channel (Temperature & time)  rr
Si
Traded with Oxidation SiO2
retardation effect

a b c

Increasing oxidation time: from triangle to circle

19
Experimental results of NWFETs

Single wire

Source

Damascene
Gate Groove

Drain

Y. Tian et al., IEDM, 2007,


PKU Multiple wire 20
Current mirror (CM) based on SNWTs
Single NW

2T CM

cascade CM

Multi NW
R.Huang et al.,T-ED,2011,PKU adjust current ratio
with NW number
21
Testing results
symbols: results lines: linear fitting
current ratio (IOUT:IIN) Inversion Inversion IIN=8A
8
20
1:2 IIN=6A
VOUT=0.3~1.2V 6
1:1

IOUT (A)
4:1
IOUT (A)

output voltage swing


10 IIN=4A
4
IIN=2A
2
0 lines: 2-T PCM
symbols: 2-T NWCM
0
0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2
IIN(A) VOUT (A)

OVC(%)=100(IOUT/IOUT)/VOUT
OVC NW CM Planar CM
2T ~0.2% ~5.7%
cascade ~0.05% ~1%

22
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects (Rpar and Cpar)
• dominant factors in Rpar and Cpar
– Self-heating effects SNWTs C
Cparasitic gc
– Variability 100%

Capacitance percentage
• Recent nanowire circuit demonstrations
80%

• Summary 60%

40%

20%

0%
10nm 15nm 25nm 32nm
gate length
23
Parasitic R and C in GAA SNWTs
• SNWT is worse
than planar devices Rsd Rsd
and FinFETs Rext
– larger and
dominant SDE
series resistances
– larger outer fringing
capacitances

24
Parasitic capacitances in SNWTs

Cparasitic = Cof + Cif +


Cov + Cside

Cof = Cof_gsd + Cof_gex

• A predictive model for parasitic C in SNWTs


has been developed*
*Jibin Zou et al., T-ED, vol. 58, no. 10, Oct. 2011,PKU 25
Impacts of parasitic C -1/2
• Outer fringe capacitance Cof is dominant
– Cof_gsd is the main contributor
Parasitic capacitance percentage

30% Cif 100% Cof_gsd

Outer fringe capacitance


25% Cside
80% Cof_gex
Cov
20%
Cof 60%
15%
40%
10%
20%
5%
0%
0% 10nm 15nm 25nm 32nm
10nm 15nm 25nm 32nm gate length
gate length
Cof_gsd Cside
Cof_gex HGate
g
Cov

J. Zhuge et al., T-ED 2008, p. 2142; PKU d


Source w Source
Extension
Cif

Jibin Zou et al., IEEE T-ED, vol. 58, no. 10, Oct. 2011.PKU 26
Lex
Key messages for design optimization
of parasitics in SNWTs
• multi-wire structure is needed
– with merged SDE structure
• gate height need to be reduced
• Optimizations in SDE regions 21
10

Optimized Doping Profile (cm-3)


Lg
– different from DG FinFETs 20
10
19
10
• FinFETs: underlap is 18 Lex =
better 10
5 nm @ Optimized
17 stdDev / Lex
10 10 nm
• SNWTs: overlap is better 16 20 nm = 0.3
10
 due to better gate control 30 nm
15
capability in SNWTs 10
channel doping
14
10
 can effectively reduce Rext -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03
but with smaller impact on Channel Direction (m)

Cparastic

J. Zhuge et al., T-ED 2008, p. 2142;


27
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects (R and C)
– Self-heating effects (SHE)
– Variability
• Recent nanowire circuit demonstrations
• Summary

28
Transistor thermal challenges
at nanoscale -1/2 Rocket
Nozzle

Nuclear
Reactor

E. Pop et al. Hot


IEDM 2001 Plate

E. Pop, Proc IEEE 2006

 Headache for analog circuits


 mismatch issue due to
Increasing
self-heating thermal distribution
with size  Reliability: NBTI …
shrinking  Thermal noise
 …… 29
Transistor thermal challenges
at nanoscale -2/2
Worse SHE for scaled technology: Confined geometries
(thin Si films in UTB, DG…) and novel materials (SiGe,
Ge, silicide…) with poor thermal conductivity

IBM

E. Pop, Proc. IEEE 2006

• SNWTs: more confined structure


So, how about the self-heating?
30
SHE Characterization of SNWTs
• AC conductance method
500
VG=1.8V
Bulk SNWTs
400 LG=130nm
VG=1.5V
ID (A)
300

200 VG=1.2V

100
Hollow: w/ SHE (DC)
Solid: w/o SHE (AC)
0
0.0 0.3 0.6 0.9 1.2 1.5
VD (V)

SNWTs on fully bulk substrate


(w/o e-SiGe S/D or SOI)
R. Wang, et al., IEDM 2008,PKU
31
Comparisons
Bulk SNWTs (this work) Bulk SNWTs FinFET [x]
(this work) (on SOI)
SOI [15] 100
100
Rth (mK/mW)

T (K)
SOI [13] SOI[14] 10
Planar
SOI [14]
SOI [12]
10 Bulk [13] 1
Planar SOI [12]

0.1
100 1000 0.01 0.1 1 10
LG (nm) Power (mW)

• SHE in SNWTs even on bulk-Si substrate is a


little bit worse than SOI devices
[12] G. Guegan et al., Mater. Res. Soc. Symp. Proc., 2006; [13] K. Etessam-Yazdani et al., ITHERM, 2006; [14] B.
M. Tenbroek et al., IEEE TED, 1996; [15] W. Jin et al., IEDM, 1999; [x] A.J. Scholten et al., IEDM 2009.
32
Improvement by increasing heat
dissipation through the gate stack?
• High-k gate dielectric has better thermal
conductivity than SiO2 or SiON gate material
• but still have non-negligible SHE when dNW < 14nm

HfOx / TaN gate, LG=21nm


S. Bangsaruntip, et al., VLSI 2010
33
Why degraded SHE in SNWTs?
• 1D heat transport for strongly-confined NW structure
– limited modes for heat dissipation
2-D heat transport
SSoouurcrece 1-D heat transport
Dr
D in
raain
3D TS TD
TS
System q System
TD

contact thermal resistance BOX

34
Why degraded SHE in SNWTs?
• 1D heat transport for strongly-confined NW structure
– limited modes for heat dissipation
2-D heat transport
SSoouurcrece 1-D heat transport
Dr
D in
raain
3D TS TD
TS
System q System
TD

contact thermal resistance BOX

• Additional contact thermal resistance


– abrupt interface between 1D-NW and 3D-S/D region
– does not exist in planar devices
• GAA: increased surface/volume ratio, strong phonon-
boundary scattering and thus increased boundary Rth
– worse than UTB SOI, DG/TG structures
35
Thermal conductivity model for Si NWs
stars:
The model includes exp. [a,b]
40
Roughness circles:
diameter dependence, =0.3nm simulation [c]
surface roughness 30 lines:

keff (W/mK)
this work (model)
and gate length
20
dependence.
Roughness d=115nm
kb 10 =1nm
k eff  d=
A B 2
C  b 56nm
1  
d d2 d2 L 0
 0 40 80 120 0 1 2 3 4 5
b 4 b 2 Diameter(nm) Roughness(nm)

[a] A. I. Hochbaum et al., Nature, vol. 451, p.163, 2008.


[b] D. Li et al., APL, vol. 83, p. 2934, 2003.
[c] P. Martin et al., PRL, vol. 102, p. 125503, 2009. X. Huang, et al., to be published.

36
Equivalent Thermal Network for SNWTs
T=300K

R g‐pad R couple1 Multi‐wires Symbol: Experiment


in parallel
Rd‐g Line: model
Symbol: Exp. Line: model
500
VG=1.8V
Red: wo/SHE
R ox Rox Rox 400 White w/SHE
Black:
Rs Rext1 Rch2 Rch4 R ext2 Rd
Rch3 VG=1.5V

Ids (uA)
Rch1
300
Rcontact R ox Rox Rox Rcontact

200 VG=1.2V
R g‐sub
R couple2
100
Rsub Bulk SNWTs
LG=130nm
0
0.0 0.3 0.6 0.9 1.2 1.5
T=300K Vds (V)
Heat dissipation: to big S/D
to gate X. Huang, et al., to be published.
37
Outline
• Fabrication and integration (a quick review)
• Recent advances in understanding SNWTs
– Intrinsic carrier transport
– Parasitic effects (R and C)
– Low-frequency noise
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary

38
“There’s plenty of room at the bottom” -- Richard P. Feynman
“There’s also plenty of noise
and variation at the bottom…”
• Variability challenges in nano-CMOS
– new process technologies
– new materials
– much smaller devices
die-to-die
within-die

wafer-to-wafer

39
Variation in nano-scale devices
Systematic OPC, Layout Dependent Strain…
Random Dopants, Line Edge
Random Roughness, High-k Morphology,
Metal Gate Granularity…

• Random variations near atomic dimensions


– impacts circuit functionality and stability
• New architecture NWFET with ultra-scaled
dimension and surrounding gate structure
– What about its variability?

40
What about GAA nanowire MOSFETs?
• Elimination of random dopant fluctuation (RDF) in
the channel, what about other sources?
Extension region RDF Effective channel length ∆L:
(Rext or Lext variation) L2 = Lext2 + Lg2
Ext. length ∆Lext
Metal-gate WF
l e ngth ∆L g
Gate Variation (WFV)

c r oss-
NW onal
secti e
ten sion shapiation
NWnel
Ex var s ∆R,
h a n ( radiu
C
etc.)
e
Sourc NW Drain
Ga te LER/LWR

Transport (ballistic effects, mobility) variation


due to strain variation, surface roughness, etc.

New sources:
diameter variation, NW LER/LWR, NW SDE RDF 41
Impacts of Variation Sources in SNWTs
(Experimental Extraction Results)
Variation Sources Variation Sources
L L
Vds=1.2V R Vgs=1.2V R
long long
Vds=1.2V
Vth (a.u.)

Ion (a.u.)
1,2 1,2
LER LER
WF WF

 R  R
 WF 100 200 300 400 100 200 300 400
 LER, L Lg (nm) Lg (nm)

J. Zhuge, et al.,
IEDM 2009,PKU
42
Discussion - 1/2: SDE RDF (1)
25

Rtotal(dNW/2) (m )
implant variation near

2
the interface
20

2
RTA variation
15

10

5
4 12 20 28 36 44

3-D KMC simulations Nanowire Diameter dNW (nm)

• Diameter-Dependent Annealing (DDA):


thinner NW results in faster diffusion
– Rext reduction and variation
– Leff reduction and variation
R. Wang et al., T-ED 2011, p. 2864.PKU 43
Discussion - 2/2: SDE RDF (2)
0.30
dNW=10nm dNW=45nm
-5
10
-6
Vdd = 1V 1.0x10 -5 Vdd = 1V -5
0.25
10 6.0x10
(RextR2) (m2)

-6
8.0x10
0.20 -5
-9 -7
4.5x10
10 -6 10
6.0x10

Id (A)
0.15
-5
-6
3.0x10
0.10 4.0x10
SNWTs -12
10
-9
10
Lg=40nm -6 1.5x10
-5
0.05 2.0x10
Lspacer=20nm

0.00 -11
0.0 10 0.0
0 5 10 15 20 25 0.0 0.3 0.6 0.9 0.0 0.3 0.6 0.9
R (nm)
Vg (V)
dNW=10nm dNW=45nm

44
SNWT vs. planar MOSFET – Simulations -1/2

Planar SNWTs
Lg=32nm Lg=32nm

• SNWT-based SRAM cells


– Larger NM and less variation of noise margin
• intrinsic channel and excellent SCE-suppression
45
SNWT vs. planar MOSFET – Simulations -2/2
SNWTs, SNM
40 SNWTs, WNM Planar
Planar, SNM SNWTs

Normalized Static Power


Planar, WNM
30
NM / NM (%)
Optimized
1.0
SNWTs SNM
Optimized
20 SNWTs WNM
0.5
10

0 0.0
10 20 30 40 50 10 20 30 40 50
Lg (nm) Lg (nm)

• Scaled SNWT-based SRAM cells


– Less NM variation and much less static
power consumption
46
Comparisons with FinFET and
UTB SOI Devices
• Experimental demonstrations so far
5
Experimental data from
2007-2010 IEDM, VLSI papers
4
AVT (mV-m)
3
With careful
2 process control

1 Samsung, VLSI 2008


AVT
VT 
Leff Weff 0
Planar FinFET UTB SNWT
bulk SOI
47
Main device characteristics
Comparison with FinFETs
• First-order device-level comparisons
with FinFETs

48
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding
SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
49
Circuit demonstration is at early stage
• SRAM (Samsung, VLSI 08)
– Larger SNM than planar and
FinFET devices
– Smallest variation demo
• Current Mirror (Peking Univ., T-ED 11)
– Good performance in both inversion and subthreshold
regions
• 25-Stage Ring Oscillators (IBM, VLSI 10)
– dNW= 3~14 nm, LG= 25~55 nm
– Limited by the SDE series resistance, need further
improvement

50
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary

51
Key Messages for GAA SNWTs: Summary
 Almost manufacturable: but still needs
better process controllability
 Variability: lowest (static) variations
– key variation sources for further optimization:
diameter variation, WFV, NW LER, SDE RDF
? Relatively severe parasitic effects
? Non-negligible SHE even on bulk: thermal
balanced design needed
? Circuit demonstration: still on the way

52
Structure features should be included
Strong confinement with GAA
• transport
• reliability Multiple surface orientations
• noise (RTN) • reliability
• noise
Shallow SDE region
• variability Gate
Source Drain
• parasitics
• noise Source Ext. Drain Ext.

3D S/D interfaced with 1D NW Quasi-1D cylindrical channel


• transport • transport
• self-heating • self-heating
• parasitics • reliability

Further in-depth understanding and special


device-circuit co-design expected
53
Thank You Very Much !
54
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