Documente Academic
Documente Profesional
Documente Cultură
Ru Huang
Peking University (PKU)
Beijing 100871, China
1
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
2
Introduction - 1/5
3
Introduction - 2/5
We are entering the multi-gate era!
• Intel’s 22nm is Tri-gate transistor
• What’s next?
4
Introduction - 3/5
Next: Gate-all-around Nanowire Transistor
Scalability
Gate-all-around
Upper Limit Gate
2 of TSi / LG Source All Drain
Ext. Around Ext.
-gate -gate cylindrical
rectangular
1 Double-
gate
FinFET “the ideal transistor”
2/3 Tri-gate best gate controllability
FinFET relax the strict scaling
Number of Gates requirement of tOX and Tsi
1/2
2 3 3+ 4 4+
FinFET/Tri-gate Gate-all-around
Extreme
Fin Scaling Nanowire
Channels Channels
5
Introduction - 4/5
How to fabricate this device?
Did we know all about this kind of device?
• We already have the scaling theory for Tri-gate and GAA
• But, one cannot simply scale GAA properties to get
correct understanding of Si nanowire transistor
Strongly-confined quasi-1D structure fundamentally
different !
Carrier
Carrier
transport?
transport?
8
Key Messages: Preview
• Fabrication and integration: almost Manufacturable
• Recent advances in understanding SNWTs
– Intrinsic carrier transport: near-ballistic transport
90 GAA SNWT (twin NWs) [x] [this work]
80 bulk MOSFET [x]
[1]
SiC S/D FinFET [x]
[2]
70 NW FETs plannar DG MOSFET [3][x]
60
bulk MOSFET (simulation) [x][4]
Tri-gate SNWT (single NW) [5][x]
BSAT(%)
50
40
Double-gate FETs
30
20 [1] J. Jeon, et al., VLSI 2009, p. 48
Planar [2] T.-Y. Liow et al., IEDM 2006, p. 473
10 [3] V. Barral et al., Solid-State Electron.,
bulk FETs 51, p. 537, 2007.
0
10 100 500 [4] Y. Taur et al., IEDM 1998, p. 789
LG(nm) [5] S.D Suk et al., VLSI 2009, p. 142
TiN
Po l
y-G PKU LETI
ate
Poly Silicon
SiO2 IBM
B OX
Oxide S. Bangsaruntip
Gox SNW NUS
10 nm Silicon Nanowire
et al., IEDM, 2009
Si Purdue Oxide
Samsung IBM
NUS 10 nm Silicon Nanowire
TIT
IEDM, 2005 IEDM, 2006 IEDM, 2007 C. Dupré et al.,
Samsung NUS PKU IEDM, 2008
LETI
HM trimming
Oxid
e
Sour
ce
Drai
n
Si S
ubs
trate
Gate trench
Nitride fin patterning & etching after oxide
S/D implantation deposition
a b c
19
Experimental results of NWFETs
Single wire
Source
Damascene
Gate Groove
Drain
2T CM
cascade CM
Multi NW
R.Huang et al.,T-ED,2011,PKU adjust current ratio
with NW number
21
Testing results
symbols: results lines: linear fitting
current ratio (IOUT:IIN) Inversion Inversion IIN=8A
8
20
1:2 IIN=6A
VOUT=0.3~1.2V 6
1:1
IOUT (A)
4:1
IOUT (A)
OVC(%)=100(IOUT/IOUT)/VOUT
OVC NW CM Planar CM
2T ~0.2% ~5.7%
cascade ~0.05% ~1%
22
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects (Rpar and Cpar)
• dominant factors in Rpar and Cpar
– Self-heating effects SNWTs C
Cparasitic gc
– Variability 100%
Capacitance percentage
• Recent nanowire circuit demonstrations
80%
• Summary 60%
40%
20%
0%
10nm 15nm 25nm 32nm
gate length
23
Parasitic R and C in GAA SNWTs
• SNWT is worse
than planar devices Rsd Rsd
and FinFETs Rext
– larger and
dominant SDE
series resistances
– larger outer fringing
capacitances
24
Parasitic capacitances in SNWTs
Jibin Zou et al., IEEE T-ED, vol. 58, no. 10, Oct. 2011.PKU 26
Lex
Key messages for design optimization
of parasitics in SNWTs
• multi-wire structure is needed
– with merged SDE structure
• gate height need to be reduced
• Optimizations in SDE regions 21
10
Cparastic
28
Transistor thermal challenges
at nanoscale -1/2 Rocket
Nozzle
Nuclear
Reactor
IBM
200 VG=1.2V
100
Hollow: w/ SHE (DC)
Solid: w/o SHE (AC)
0
0.0 0.3 0.6 0.9 1.2 1.5
VD (V)
T (K)
SOI [13] SOI[14] 10
Planar
SOI [14]
SOI [12]
10 Bulk [13] 1
Planar SOI [12]
0.1
100 1000 0.01 0.1 1 10
LG (nm) Power (mW)
34
Why degraded SHE in SNWTs?
• 1D heat transport for strongly-confined NW structure
– limited modes for heat dissipation
2-D heat transport
SSoouurcrece 1-D heat transport
Dr
D in
raain
3D TS TD
TS
System q System
TD
keff (W/mK)
this work (model)
and gate length
20
dependence.
Roughness d=115nm
kb 10 =1nm
k eff d=
A B 2
C b 56nm
1
d d2 d2 L 0
0 40 80 120 0 1 2 3 4 5
b 4 b 2 Diameter(nm) Roughness(nm)
36
Equivalent Thermal Network for SNWTs
T=300K
Ids (uA)
Rch1
300
Rcontact R ox Rox Rox Rcontact
200 VG=1.2V
R g‐sub
R couple2
100
Rsub Bulk SNWTs
LG=130nm
0
0.0 0.3 0.6 0.9 1.2 1.5
T=300K Vds (V)
Heat dissipation: to big S/D
to gate X. Huang, et al., to be published.
37
Outline
• Fabrication and integration (a quick review)
• Recent advances in understanding SNWTs
– Intrinsic carrier transport
– Parasitic effects (R and C)
– Low-frequency noise
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
38
“There’s plenty of room at the bottom” -- Richard P. Feynman
“There’s also plenty of noise
and variation at the bottom…”
• Variability challenges in nano-CMOS
– new process technologies
– new materials
– much smaller devices
die-to-die
within-die
wafer-to-wafer
39
Variation in nano-scale devices
Systematic OPC, Layout Dependent Strain…
Random Dopants, Line Edge
Random Roughness, High-k Morphology,
Metal Gate Granularity…
40
What about GAA nanowire MOSFETs?
• Elimination of random dopant fluctuation (RDF) in
the channel, what about other sources?
Extension region RDF Effective channel length ∆L:
(Rext or Lext variation) L2 = Lext2 + Lg2
Ext. length ∆Lext
Metal-gate WF
l e ngth ∆L g
Gate Variation (WFV)
c r oss-
NW onal
secti e
ten sion shapiation
NWnel
Ex var s ∆R,
h a n ( radiu
C
etc.)
e
Sourc NW Drain
Ga te LER/LWR
New sources:
diameter variation, NW LER/LWR, NW SDE RDF 41
Impacts of Variation Sources in SNWTs
(Experimental Extraction Results)
Variation Sources Variation Sources
L L
Vds=1.2V R Vgs=1.2V R
long long
Vds=1.2V
Vth (a.u.)
Ion (a.u.)
1,2 1,2
LER LER
WF WF
R R
WF 100 200 300 400 100 200 300 400
LER, L Lg (nm) Lg (nm)
J. Zhuge, et al.,
IEDM 2009,PKU
42
Discussion - 1/2: SDE RDF (1)
25
Rtotal(dNW/2) (m )
implant variation near
2
the interface
20
2
RTA variation
15
10
5
4 12 20 28 36 44
-6
8.0x10
0.20 -5
-9 -7
4.5x10
10 -6 10
6.0x10
Id (A)
0.15
-5
-6
3.0x10
0.10 4.0x10
SNWTs -12
10
-9
10
Lg=40nm -6 1.5x10
-5
0.05 2.0x10
Lspacer=20nm
0.00 -11
0.0 10 0.0
0 5 10 15 20 25 0.0 0.3 0.6 0.9 0.0 0.3 0.6 0.9
R (nm)
Vg (V)
dNW=10nm dNW=45nm
44
SNWT vs. planar MOSFET – Simulations -1/2
Planar SNWTs
Lg=32nm Lg=32nm
0 0.0
10 20 30 40 50 10 20 30 40 50
Lg (nm) Lg (nm)
48
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding
SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
49
Circuit demonstration is at early stage
• SRAM (Samsung, VLSI 08)
– Larger SNM than planar and
FinFET devices
– Smallest variation demo
• Current Mirror (Peking Univ., T-ED 11)
– Good performance in both inversion and subthreshold
regions
• 25-Stage Ring Oscillators (IBM, VLSI 10)
– dNW= 3~14 nm, LG= 25~55 nm
– Limited by the SDE series resistance, need further
improvement
50
Outline
• Introduction
• Fabrication and integration
• Recent advances in understanding SNWTs
– Parasitic effects
– Self-heating effects
– Variability
• Recent nanowire circuit demonstrations
• Summary
51
Key Messages for GAA SNWTs: Summary
Almost manufacturable: but still needs
better process controllability
Variability: lowest (static) variations
– key variation sources for further optimization:
diameter variation, WFV, NW LER, SDE RDF
? Relatively severe parasitic effects
? Non-negligible SHE even on bulk: thermal
balanced design needed
? Circuit demonstration: still on the way
52
Structure features should be included
Strong confinement with GAA
• transport
• reliability Multiple surface orientations
• noise (RTN) • reliability
• noise
Shallow SDE region
• variability Gate
Source Drain
• parasitics
• noise Source Ext. Drain Ext.
…