JAGRUTH S J

Samrudhi nilaya, Kadidal Layout, Bettamakki, Seebinakere(P),

Thirthahalli(T), Shimoga(D) -577432
Email: jagruthgowdavv@gmail.com
Linkedin:http://www.linkedin.com/in/jagruth-s-j-27b3aa16a
+91-9964549434

CAREER OBJECTIVES
To achieve high career growth through a continuous learning process and keep myself dynamic, visionary and
competitive with changing scenario of the world to obtain great height for organization.

PROFILE SUMMARY
Experience: Training in ASIC Physical Design with hands-on experience on backend design flow
including - Synthesis, Floor-planning, Power Planning, Placement, Static Timing Analysis (OCV, CPPR,
Multi- cycle path, False path) at Sarvakarma Solutions Pvt. Ltd. from July 2019.

Qualification: B E in Electrical and Electronics.

Training : Sarvakarma Solutions Pvt. Ltd, Bangalore [July 2019-Till date]
PRIMARY TECHNICAL SKILLS
Language: Verilog, TCL Scripting.
Tools: Cadence, Genus, Tempus, Innovus.
Operatting System: Windows, Linux (RED HAT).
CORE COMPETENCIES
 Good understanding of ASIC Design flow from RTL to GDSII.
 Experience in Block level implementation on advanced technology like 45nm in various stages of Physical
Design flow – Floorplan, Powerplan, Placement, CTS, Routing.
 Hands on experience on Industry Standard Tools, such as Genus, Innovus, Tempus.
 Good knowledge in Setup time, hold time, source latency, network latency, uncertainity.
 Good understanding of STA concepts like OCV, Derate factors, CPPR, Multicycle path, False path, and
fixing timing violations, Time borrowing concept in latch.
 Working knowledge on Linux environment.
 Basic knowledge in TCL Scripting.
 Written few TCL Scripts for getting desired information from tool and reports.
 Completed power plan without any connectivity and geometry violations.

EDUCATIONAL DETAILS
1. BE( Electrical and Electronics Engineering) from Vidya Vikas Institute of Engineering &
Technology, Mysore, Karnataka 7.27(CGPA)
2. Pre University (PCME) from Government PU collage, Thirthahalli, Shimoga, Karnataka (79.66%)
3. SSLC/10th from Government High School, Thirthahalli, Shimoga, Karnataka (76.80%)
DOMAIN SPECIFIC PROJECT
Graduate Trainee Engineer September-2019 to September -2019

Analyzing Timing reports in STA

Description: Analysis of timing reports in STA for provided Netlists corresponding to Different Scenarios for
all timing paths.

Tools: Cadence – Tempus.

Role/Challenges:

 Analyzed the timing reports for all possible timing paths such as Register -Register, Input –
Register, Register -Output and Input -Output.
 Setup and hold timing violations are checked for different timing paths.
 Analyzed half clock cycle paths, Multicycle paths and false path exceptions
 Analyzed timing reports with clock uncertainities such as skew, latency, jitter.

Graduate Trainee Engineer November-2019 to November-2019

Block level Implementation of Leon Processor in 45nm

Description: A block with 4 macro and 36k cell count. Operating at the frequency of 250 MHz and having 2
Clocks.

Tools: Cadence – Innovus.

Role/Challenges:

 Placement of Macro cells with Halos, Placement and routing blockages so that design is congestion
free.
 Implementing Power planning to make design floating Pin free and ensure that all macro & standard
cells are connected to VDD & VSS.
 Fixing DRVs.

Graduate Trainee Engineer November -2019 to November -2019

Block level Implementation of Low Power Design for DMA

Description: A block with 7 macros and having 27k instances with1.5 million gate count. No. of Clocks used
is 5 with 4 different Power domains.

Tools: Cadence – Innovus.

Role/Challenges:

 Placement of macros in different power domains.

 Special type of cells are used in low power design like Always on buffers, Isolation cells, Level shifters,
Power switch are observed.
 Understanding the main reasons of getting shorts and making an attempt, alter the net & try to fix them
without making an DRC error.

Graduate Trainee Engineer December-2019 to December -2019

Clock Tree synthesis

Description: Synthesized Clock tree using clock buffers and Inverters in appropriate locations, thereby
minimizing slew, insertion delay and fixing the timing violations.
Tools: Cadence – Innovus.

Roles/Challenges:

 Building a well-balanced clock tree to meet the target skew and fixing all Setup and Hold
violations.
 Analyzing and updating latency of external clock source with the clock tree.
 Analyzed uncertainity before and after Clock Tree Synthesis.
 Analyzing the timing report and check the violations before and after Clock Tree Synthesis.

ACADEMIC PROJECT
Title:3X’s EAP

Description: Here 3X’s EAP stands for 3 Axis Engraving and PCB milling Machine, By using our project
we can design a low cost PCB board in home itself, In this input instruction is given by using PC itself
whatever the design layout we given to the PC is done by our CNC machine.

INTERNSHIP

Organization: DMS Technologies, Mysore.

Description : From this internship we came to know across the End to End process in the PCB designing and
manufacturing And we also done PCB board designing using Dip Trace software according to the user need.

PERSONAL DETAILS
Name: Jagruth S J

Gender: Male.

Languages Known: English, Kannada, Telugu.

Current Address: #34/2, Sarala nilaya, Beereshwara nagar 5th cross Near Muneshwara temple,
Chunchangatta main road Bengaluru, Bengaluru, Karnataka – 560062

DECLARATION

I hereby declare that the information above is true to the best of my knowledge and I would like to assert to the
full of my satisfaction that, I would put my best efforts in the organization and work for the best possible results.

Place : Bangalore Jagruth S J

Date: