EE512: EXP 03- ANALYSIS FOR SENSE AMPLIFIER .

22, NOVEMBER 2019 1

Design Schematic of the circuit for Sense Amplifier

in cadence virtuoso, 130nm Technology
Hem Chaitanya - T19175
CMOS Digital IC Design Practicum (EE519P)
Instructor: Dr. Rahul Sreshtha
School of Computing and Electrical Engineering
Indian Institue of Technology, Mandi

Abstract—In this report, a schematic for Sense amplifier is
designed using cadance virtuoso tool, 130nm technology. The aim
of this report is to get the waveform at some nodes, and to do
analysis for the waveform at that nodes.
I. I NTRODUCTION
The shorting transistor, M4, is used to provide a DC leak-
age path from either node L3, or L4, to ground. This is
necessary to accommodate.the case where the inputs change
their value after the positive edge of CLK has occurred,
resulting.in either L3 or L4 being.left in a high-impedance
state.with a logical low voltage level.stored on the node.
Without the leakage.path that node would be susceptible.to

T He sense amplifier is.one of the.technique used.for

building of edge-triggered.registers. Sense-amplifier cir-
cuits.accept small input signals.and amplify them.to generate
charging by.leakage.currents.

rail-to-rail swings.In.this report, we.have use input.voltage II. D ESIGN AND SPECIFICATION
as 0-400mV pulse voltage and.obtained amplified.output as
0-1.2V pulse voltage. Sense amplifier.circuits are used ex- In this report, we have.used six.NMOS and four.PMOS
tensively.in memory.cores and in.low swing bus.drivers to and two.NAND gate. The.NAND gate we used.is same as
amplify.small voltage swings.present in heavily.loaded wires. what.we designed in.previous report. We.only intensiated.that
There are.many techniques.to construct these.amplifiers, with NAND gate.into this schematic. The schematic.is designed
the use of.feedback.being one.common approach. The circuit in same way as it is given is figure 1. The clock.signal
shown.in below is the sense.amplifier that we.are going to.use is applied.at the gate terminal of M1, M9.and M10. The
in this report.[1] input.which is a pulse.signal of time.preiod 5ns is applied at
In this figure.the circuit.uses a precharged.front-end am- the gate terminal.of M2 and M3. The amplified.output we.are
plifier.that samples the differential.input signal on.the rising gettng from.the output terminal.of NAND gate. The output.for
edge.of the clock signal. The.outputs of front-end are.fed into a both the NAND.gate is same but.inverted. The schematic.for
NAND cross-coupled SR FF that.holds the data and.guarantees the circuit for.is given.below:
that the differential.outputs switch only once per clock.cycle.
The differential inputs.in this implementation don’t.have to
have.rail-to-rail swing and.hence this register can be used as
a receiver.for a reduced swing differential bus.
The core of.the front-end consists.of a cross-coupled.inverter
(M5-M8), whose outputs (L1 and L2) are.precharged using
devices M9 and.M10 during the low phase of the.clock. As
a result, PMOS.transistors M7 and M8 to.be turned off and
the.NAND FF is holding.its previous.state. Transistor M1
is similar to an evaluate.switch in dynamic.circuits and is
turned off ensuring that.the differential.inputs don’t affect the
output.during the low phase of the.clock. On the rising edge.of
the clock, the evaluate transistor.turns on and the differen-
tial.input pair (M2 and M3) is enabled, and.the difference
between.the input signals.is amplified on.the output nodes
on.L1 and L2. The cross-coupled inverter.pair flips to one.of its
the stable.states based on the.value of the inputs. For example,
if IN is 1, L1 is pulled to 0, and L2 remains.at VDD. Due to the
amplifying properties of the.input stage, it is not necessary.for
the input to swing all the way up to VDD and enables the use Fig. 1. Schematic for Sense Amlifier.
of low swing signaling on the input wires.
EE512: EXP 03- ANALYSIS FOR SENSE AMPLIFIER . 22, NOVEMBER 2019 2

III. D ESIGN P ROCEDURE

A. Complete design details for schematic
At first.we have.design the schematic.for the circuit in
figure-2. Then.a pulse voltage(Vpulse) is applied.as closk
signal, as.well as input.signal. The input.ac magnitude is.given
is 400mV.and for clock pulse.it is 1.2V.

IV. S IMULATION R ESULT

A. Transient Response

Fig. 2. Response of the sense amplifier.

Here,the output.has been observed at node L1, L3

and.output. From.the plot, we can.see that the.waveform at
L1 and L3 is decaying. This.discharging of the voltage.is due
to the leakage.current through.M2.

V. C ONCLUSION
In this report the.schematic of the circuit.for Sense Am-
plifier has.been designed.using 130nm technology, as per the
given.specification using Cadence.virtuoso EDA simulation
tool. From the schematic.the waveform at the several.nodes
has.been observed. And it has.been seen that the voltage.is
discharging at node L1, L2, L3 and L4. This is.due to the
leakage.current.

VI. ACKNOWLEDGEMENT
I convey my sincere.gratitude to our instructor.Dr. Rahul
Shrestha for.his constant guidance. I would also like
to.thanks Mr.Rohit and Mr. Najrul for.their guidance.and con-
stant.support.

R EFERENCES
[1] B. Digital integrated circuits, Jan M Rabaey, Anantha P Chandrakasan,
Borivoje Nikolic, 2nd Edition
[2] P. Allen and D. Holberg, CMOS Analog Circuit Design. Oxford series
in electrical and computer engineering, Oxford University Press,2002.