1

Design of Parallel Prefix Adders

A.V. Pradeep Chandra1 , K. Jayaprasada Rao2 and T. Sivaram Gupta3
1,2,3 School of Electronics Engineering(SENSE), VIT University, Vellore-632014, Tamil Nadu, India. email:
avpchandra@gmail.com

Abstract—In now a days any digital system, digital signal
processor or control system the adder plays an important role.
Adders are also very important components in digital systems
because of their extensive use in other basic digital operations
such as subtraction, multiplication and division. Hence, improv-
ing performance of the digital adder would greatly advance
the execution of binary operations inside a design. So, in this
paper we proposed three types of parallel prefix adders , they
are Ladner-Fischer, Kogge-Stone and Sklansky adders. Parallel
prefix addition is nothing but adding the bits parallelly and
propagation of each carry to further stages at a time. It will
improves the performance of the entire digital system. The
proposed adders are aims at reduced latency, area efficient, low
power consumption in VLSI implementations compared to the
traditional binary adders.
Index Terms—prefix addition, Ling carries, CSAL
II. L ADNER - F ISCHER A DDER
The carry computation is done by using associative operator
(o) which is applied to generate and propagate bits as (g,p)
0 0 0 0
o (g ,p ) = (g+p.g ,p.p ). Similarly the continuation of this
for all generate and propagate bit (g,p) gives the notation of
(Gk:j ,Pk:j ) for k,k-1,. . . .j that is
(Gk:j , Pk:j ) = (gk , pk )o(gk−1 , pk−1 )o. . . . . . . . . o(gj+1 , pj+1 )o(gj , pj )
Here we should consider each carry ci equal to Gi:0 . The
associative operator has the property of idempotancy i.e.
(g,p)o(g,p)=(g,p). This gives rise to (Gi:j ,Pi:j ) is derived by
associating the grouped generate and propagate terms with the
condition i>m≥k>j, so the equation can be
(Gi:j , Pi:j ) = (Gi:k , Pi:k )o(Gm:j , Pm:j ) (1)

I. I NTRODUCTION From Figure1 the parallel prefix structure of Ladner-fisher the

node represents associative operator (o) which combines
INARY addition is the basic operation in digital systems the grouped terms as mentioned in eq(2) to compute the carry
B like digital signal processors, arithmetic logic units and
floating point arithmetic data paths. There are so many types of
bits and white nodes are for buffering purpose. Each black cell
having some logical implementation given in Figure 3 and the
adders are proposed before. But if speed is the main constraint, white box in Figure1 is used to calculate generate,propagate
then we are supposed to use these parallel prefix adders. When and half-sum bits for the pre-processing stage. And this white
we are dealing with Very large scale integrated circuits Parallel box also having some logical implementation as shown in
prefix adders are suitable for these requirements. The parallel Figure2.
prefix structures allow tradeoffs among the number of required
logic levels.
In this paper we proposed several varieties of carry look
ahead equations like ling carries that are simple and fast
method of computing carry. Mainly this ling carry compu-
tation depends on simple binary operator called an associative
operator. This Ling carries computation methodology can be
useful for any type of parallel prefix adders. This makes the
carry computation very easy.

A. Parallel Prefix Addition

Let A = An−1 An−2 . . . . A0 and B = Bn−1 Bn−2 . . . . . . ..
B0 can be two binary numbers to be added and
S=Sn−1 Sn−2 . . . . . . . S0 denotes their sum. An adder can be
considered as a three stage circuit 1. pre-processing stage 2.
second stage 3. final stage. The pre-processing stage computes,
carry generate bits, gi =ai .bi , carry propagate bits pi =ai + bi
and half-sum bits di =ai xor bi . The second stage computes ci
by using pi and gi and the final stage computes the sum bits,
si = di xor ci−1 . This is general procedure for parallel-prefix
addition. Figure 1. The 8-bit Ladner-Fischer adder structure
 2

After generating the pairs (G∗i ,Pi−1

∗
), maximum two prefix
levels are needed for the computation of each carry (Hi ).
Hence, this method reduces one-logic level implementation
compared to traditional adder. Then in the final stage we have
to calculate sum bits by using equation (6)
0
Si = Hi−1 .di + Hi−1 (di xorpi−1 ) (5)
Which can be implemented by using a 2:1 multiplexer with
control input as Hi−1 and two inputs as di and (di xor pi−1 ).
This sum calculation is done by diamond box in the Figure 1.
Figure 2. The logic-level implementation of white box
The logic level implementation of diamond box is as shown
in Figure 4

Figure 3. The logic-level implementation of black cell

Ling proposed some carry lookahead equations based on Figure 4. The logic level implementation of diamond box
(ai ,bi ) and (ai−1 bi−1 ). So the ith ling carry is Hi =ci +ci−1 .
Similarly each Hi can be
III. KOGGE S TONE ADDER
Kogge-stone adder is a parallel prefix form of a carry look
Hi = gi +gi−1 +pi−1 .gi−2 +. . . ..+pi−1 .pi−2 . . . . . . p1 g0 (2) ahead adder. It generates a carry on O (log n) time and is
This carry computation is faster than normal carry compu- widely considered as a fastest adder compare all others adders
tation. So, this is proposed to be faster. For Figure1 the so it is widely Used in the industry for high performance
computation of carries approach is given as follows: By using arithmetic operations. In kogge - stone adder carries are
equation (3), computed quickly by computing them in parallel. Kogge-Stone
H7 = g7 + g6 + p6 .g5 + p6 .p5 .g4 + p6 .p5 .p4 .g3 + adder is a flexible adder and it is implemented from carry look
p6 .p5 .p4 .p3 .g2 + p6 .p5 .p4 .p3 .p2 .g1 + p6 .p5 .p4 .p3 .p2 .p1 .g0 ahead structure.
H6 = g6 + g5 + p5 .g4 + p5 .p4 .g3 + p5 .p4 .p3 .g2 + The complete functioning of kogge stone adder can be
p5 .p4 .p3 .p2 .g1 + p5 .p4 .p3 .p2 .p1 .g0 easily comprehended by analyzing it in terms of three dif-
Since gi .pi = gi and assuming that G∗i =gi +gi−1 and ferent parts 1.PRE-PROCESSING STAGE 2.CARRY LOOK
Pi =pi .pi−1 , 0 ≤ i ≤ n-1, with g−1 =p−1 =0, G∗k =Pk∗ =0, for
∗ AHEAD NETWORK 3.POST PROCESSING
k<0, then the above carries can be written as, 1.PREPROCESSING STAGE:
This step involves a computation of generating and propa-
H7 = (G∗7 , P6∗ )o(G∗5 , P4∗ )o(G∗3 , P2∗ )o(G∗1 , P0∗ ) (3) gate bits corresponding to each pair of bits in two different
inputs that are A and B. These bits are given by the logic
equations
H6 = (G∗6 , P5∗ )o(G∗4 , P3∗ )o(G∗2 , P1∗ )o(G∗0 , P−1
∗
) (4) P i = Ai xorBi
Similarly,
Gi = Ai andBi
H5 = (G∗5 , P4∗ )o(G∗3 , P2∗ )o(G∗1 , P0∗ )
2.CARRY LOOK AHEAD NETWORK:
H4 = (G∗4 , P3∗ )o(G∗2 , P1∗ )o(G∗0 , P−1
∗
) This block differentiates kogge stone adder from other any
adders and is the main reason for its high speed performance.
This step involves computation of carries corresponding to
H3 = (G∗3 , P2∗ )o(G∗1 , P0∗ ) each bit. It uses group propagate and generate as intermediate
signals which are given by the logic equations
H2 = (G∗2 , P1∗ )o(G∗0 , P−1
∗
)
Pi:j = Pi:k+1 andPk:j
H1 = (G∗1 , P0∗ )
Gi:j = Gi:k+1 or(Pi:k+1 andGk:j )
H0 = (G∗0 , P−1
∗
) 3.POST PROCESSING STAGE:

This is the final step and is common to all adders of this
family (carry look ahead ). It involves computation of sum
bits and they are computed from the following equations
Si = Pi xorCi−1
Ci−1 = (Pi andCin )orGi
Figure 5. 4-bit Kogge Stone adder structure
Figure 6. The logical implementations of Kogge Stone adder
Figure 7. The 8-bit Kogge Stone adder
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A. 4-BIT KOGGE STONE ADDER
The Figure 6 is a 4 bit kogge stone adder. Each vertical
stage gives the propagate and generate the bits. The carriers
are generated by last stage. To generate the sum bit carries
are xored with propagate bit inside of the rectangular box.
For example the initial sum bit is calculated by the xor
operation between the initial inputs. The propagate bit from
the rectangular box is performing the xor operation with the
carry in bit. Finally we developed the least significant bit in a
koggestone adder network.
Figure 7 shows the 8-bit Kogge Stone adder
IV. SKLANSKY ADDER
Sklansky adder uses a new mechanism to perform its
computation called conditional sum addition logic (CSAL).
This logic carries out different “conditional” sums and carries
and propagates them through different columns. For the given
group of data, the conditional sum adder generates two pairs
of outputs.
The detailed mechanism is given in the accompanying
illustration. The Figure 8 shows the complete operation of
conditional sum adder.
Figure 8. The example of conditional sum operation
This process can be carried through different time intervals.
At each time interval two pairs of “sum and carries” are
computed by assuming that for one pair the incoming carry
bit is 0 and for the other pair it is 1. During t0 , the first
pair under the assumption (A0 ) that the incoming carry to
each column is 0 and the second pair under the assumption
(B0 ) that the incoming carry to each column is 1. But at
column 0 we consider only A0 as we have already known that
incoming carry is 0. In t0 the first row represents conditional
sums under the assumption A0 and the second row represents
the conditional carries under the same assumption A0 . The
third and fourth rows represent conditional sums and carries
respectively under the assumption B0 .
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Figure 9. The 2-bit Conditional sum adder

The Figure 9 shows the 2-bit Conditional Sum Adder. Figure 10. The 8-bit Sklansky adder
During t0 the sum-and-carry pairs are generated by using
the following logic.
V. EXPERIMENTAL RESULTS
Simulation waveforms
Si0 = xi (xor)yi

Ci0 = xi (and)yi

Figure 11. Simulation waveform of Ladner Fischer

Si1 = (not)Si0

Ci1 = xi (or)yi

Hereafter conditional pairs are calculated for each two

columns during t1 , four columns during t2 , eight columns Figure 12. Simulation waveform of Kogge Stone
during t3 and for entire sixteen columns during t4 . During t1 ,
the first sum-and-carry pair is under the assumption (A1 ) that
the incoming carry to each column is 0 and the second sum-
and-carry pair is under the assumption (B1 ) that the incoming
carry to each column is 1. Here also we consider only A1 for
pair of columns (0, 1) as we have already known that incoming
carry here is 0.
Figure 13. Simulation waveform of Sklansky
During t1 , under the assumption A1 (B1 ), the sum entries
in the first column is same as the entries of t0 under the
s.no. Parameter Ladner-Fischer Sklansky Kogge-Stone
assumption A0 (B0 ) and the entries for second column are
1 Power(uw) 6.073 6.483 4.012
determined by the upper (lower) right hand carry bit in the 2 Logic elements 26 24 29
t0 . If it is 0 (1) then the second column entries are same as 3 Area(um2 ) 118 115 85
entries of t0 under the assumption of A0 (B0 ) or else if it is 1 4 Timing(ns) 8.774 8.786 8.910
(0) then the second column entries are same as those entries Table I
R ESULTS
of t0 under the assumption of B0 (A0 ). The same procedure
is continued for further intervals t2 , t3 also.
Figure 10 shows the structure of 8-bit sklansky adder. The The above parameters are computed by using Cadence RTL
“CS” block represents two bit conditional adder as shown Compiler and Quartus -II software tools.The proposed adders
in Figure 9 and each “MUX” block represents a 2 to 1 are compared in different parameters like power, area, delay,
multiplexer. x0−7 and y0−7 are input operands of 8-bit Sklansky number of logic elements among them. The results are to
adder. S0−7 and C7 are the output sum bits and output carry be expected as area efficient Ladner Fischer , reduced logic
bit respectively. elements sklansky and high speed Kogge stone.
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VI. CONCLUSIONS
From table I The proposed adders have less area, high speed
and reduced logic level implementation.These adders preserve
all benefits of parallel-prefix adders along with some other
parameters mentioned above.

VII. ACKNOWLEGMENT
The authors are greatly supported by prof. Aarthy.M of VIT
University for ideas to present this paper.

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