SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

Department of Electronics and Communication Engineering

15EC302J-VLSI DESIGN LAB

Laboratory Observation

REGISTER NO :
NAME :
YEAR/SEM/SEC :

Faculty of Engineering & Technology

SRM Institute of Science and Technology
Bharathi salai, Ramapuram
Chennai - 600089
 15EC302J-VLSI DESIGN LAB
Contac C-D- I-
Sl. No. Description of experiments IOs Reference
t O
hours
Tanner Spice/HSPICE
1 CMOS Logic gate and circuits 4 D-I-O 1,5,6 6,7,8

2 Dynamic circuits 4 D-I-O 1,5,6 6,7,8

3 CMOS latches and flip flops 4 D-I-O 1,5,6 6,7,8
4 Carry Look Ahead Adder 2 D-I-O 1,5,6 6,7,8
5 Carry Skip Adder 2 D-I-O 1,5,6 6,7,8
6 Multiplier: Braun Array/ Booth Encoding/ Wallace 4 D-I-O 1,5,6 6,7,8
Tree

7 Memory: RAM and ROM 4 D-I-O 1,5,6 6,7,8

8 Finite State Machine 2 C 2 1,3

9 Barrel Shifter 2 C 2 1,3

10 Switch level modeling of CMOS gates and Boolean 2 C 2 1,3
Expressions
Total Contact hours 30

1. Course plan

 The list of experiment to be performed was discussed and planned to complete

the lab in 11-12 weeks.

No. Lab Experiments Sessions

0 Tutorial Lab 1
1 Design Combinational logic circuit (4 Bit Ripple Carry Adder, Multiplexer) 2,3
2 Design Sequential logic circuit (Flip Flop, Ripple Counter) 4
Design of VLSI Adder and multiplier (Carry Look ahead adder, Carry Save Adder,
3. Braun Array Multiplier & Wallace Tree Multiplier) 5,6

4 Design of Memory-RAM & ROM, Finite State Machine, Barrel Shifter 7,8
5 Switch Level modeling of CMOS gates and Boolean expression 9
6 CMOS Logic gate and Dynamic Circuits using HSPICE 10,11
 INDEX

EXP NO DATE NAME OF THE EXPERIMENT PAGE NO MARKS STAFF SIGNATURE

9
 Lab Experiment #1
Design of Combinational Logic Circuits

1.1 Objective: To learn the design of combinational logic circuits in Verilog then
simulating and synthesizing using EDA tools

1.2 Software tools Requirement

Equipment’s:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE
Simulation tool: ModelSim Simulator

1.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)

1.List the types of design methodologies for digital design with an example?
2. Give the difference between module and module instance.
3. What are built in gate primitivies?
4. Give the use of net, reg and wire data types.
5. Declare the following variables in Verilog:
a. An 8-bit vector net called a_in.
b. An integer called count.
c. An array called delays. Array contains 20 elements of the type integer.
d. A parameter cache_size equal to 512.

1.4.1 Problem 1: Write a Verilog code to implement Ripple Carry Adder.

The following points should be taken care of:
1. Use assign statement to design sub module half adder
2. Use gate primitives to design full adder using half adder
3. Construct the top module ripple carry adder using 1-bit full adder

Logic Diagram – Problem 1

Half adder:

Full adder:

1
 Ripple Carry Adder

Verilog Code - Problem 1

1.(a)HALF ADDER USING DATA FLOW MODEL

module Half_adder(s, cout, x, y);

output s;

output cout;

input x;

input y;

assign s=x^y;

assign cout=x&y;

endmodule

// TEST BENCH

module half_adder_tb_v;

// Inputs
// reg x; regy;

// Outputs

wire s; wire cout;

// Instantiate the Unit Under Test (UUT)

Half_adder uut (.s(s), .cout(cout), .x(x), .y(y) );

initial begin

// Initialize Inputs

x = 0; y = 0;
 // Wait 100 ns for global reset to
finish #100; x=0; y=1;

#100; x=1; y=0;

#100; x=1; y=1;

// Add stimulus here

end

endmodul
e

1.(b) FULL ADDER USING STRUCTURAL MODEL

module Full_adder(sum, carry, x, y, cin);

output sum;

output carry;

input x;

input y;

input cin;

wire w1,w2,w3;

Half_adder h1(w1,w2,x,y);

Half_adder h2(sum,w3,w1,cin);

or g1(carry,w2,w3);

endmodule

// TEST BENCH

module full_adder_tb_v;
// Inputs

reg x; reg y; reg cin;

// Outputs

wire sum; wire carry;

// Instantiate the Unit Under Test (UUT)

Full_adder uut (.sum(sum), .carry(carry), .x(x), .y(y), .cin(cin));

initial begin
 // Initialize Inputs x
= 0; y = 0; cin = 0;

// Wait 100 ns for global reset to

finish #100; x=0; y=0; cin=1;

#100; x=0; y=1; cin=0;

#100; x=0; y=1; cin=1;

#100; x=1; y=0; cin=0;

#100; x=1; y=0; cin=1;

#100; x=1; y=1; cin=0;

#100; x=1; y=1; cin=1;

// Add stimulus here

end

endmodul
e

1.(c) RIPPLE CARRY ADDER USING 1-BIT FULL ADDER

module ripple_carry_adder(S, cout, A, B, cin);

output [3:0]S;

output cout;

input [3:0]A;

input [3:0]B;

input cin;
wire c1,c2,c3;

full_adder f1(S[0],c1,A[0],B[0],cin);

full_adder f2(S[1],c2,A[1],B[1],c1);

full_adder f3(S[2],c3,A[2],B[2],c2);

full_adder f4(S[3],cout,A[3],B[3],c3);

endmodule
// TEST BENCH

module ripple_carry_adder_tb_v;

// Inputs

reg [3:0] A; reg [3:0] B; reg cin;

// Outputs

wire [3:0] S; wire cout;

// Instantiate the Unit Under Test (UUT)

ripple_carry_adder uut (.S(S), .cout(cout), .A(A), .B(B), .cin(cin));

initial begin

// Initialize Inputs A
= 0; B = 0; cin = 0;

// Wait 100 ns for global reset to

finish #100; A=0; B=0; cin=1;

#100; A=0; B=1; cin=0;

#100; A=0; B=1; cin=1;

#100; A=1; B=0; cin=0;

#100; A=1; B=0; cin=1;

#100; A=1; B=1; cin=0;

#100; A=1; B=1; cin=1;

// Add stimulus here

end
endmodule
Waveforms – Problem 1

Fig 1.(a) Half Adder using Data Flow Model

Fig 1.(b) Full Adder using Structural Model

Fig 1.(c) Ripple Carry Adder using 1-Bit Full Adder

1.4.2 Problem 2: Write a Verilog code to implement Multiplexer.

The following points should be taken care of:

Problem 2: Write a Verilog code to implement Multiplexer.
The following points should be taken care of:
1. Use data flow model to design 2x1 Multiplexer
2. Use Gate Level Model to design 8x1 Mux using two 4x1 Mux and one 2x1 Mux

Logic Diagram – Problem 2

2 x 1 Multiplexer

Select Signal(S0) Output(Y)

0 I0

1 I1

6
4 x 1 Multiplexer

Select Signal Output

(Y)
S0 S1

0 0 I0

0 1 I1

1 0 I2 8 x 1 Multiplexer

1 1 I3
Select Signal Output
(Y)

S2 S1 S0

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

Verilog Code - Problem 2

2.(a) MUX 2 X 1 DATA FLOW MODEL

module mux2_1(out, A, B, s);

output out;

input A;

input B;

input s;

7
assign out=(s)?A:B;

endmodule

// TEST BENCH

module mux2_1_tb_v;

// Inputs

reg A; reg B; reg s;

// Output
s wire out;

// Instantiate the Unit Under Test (UUT)

mux2_1 uut (.out(out), .A(A), .B(B), .s(s));

initial begin

// Initialize Inputs
A = 0; B = 0; s = 0;

// Wait 100 ns for global reset to

finish #100; A=1; B=1; s=0;

#100; A=1; B=1; s=1;

// Add stimulus here

end

endmodul
e

2.(b) MUX4 X 1 BEHAVIORAL MODEL

module mux4_1(out, I, s);

output reg out;

input [3:0]I;

input [1:0]s;

always@(I,s)

begin

case(s)

8
 2'b00:out=I[0];

2'b01:out=I[1];

2'b10:out=I[2];

2'b11:out=I[3];

endcase

end

endmodule

// TEST BENCH

module mux4_1_tb_v;

// Inputs

reg [3:0] I; reg [1:0] s;

// Output
s wire out;

// Instantiate the Unit Under Test (UUT)

mux4_1 uut (.out(out), .I(I), .s(s)); initial
begin

// Initialize Inputs

// Wait 100 ns for global reset to

finish #100; I=4'b1101; s=2'b01;

#100; I=4'b0100; s=2'b10;

#100; I=4'b0111; s=2'b11;

// Add stimulus here

end

endmodul
e
2.MUX 8 X 1 USING 4 X 1 MUX AND 2 X 1 MUX

module mux8_1(out, s, i);

output out;

input [2:0]s, [7:0]i;

wire [1:0]w;

mux4__1 m1(w[0], i[0], i[1], i[2], i[3], s[0], s[1]);

mux4__1 m2(w[1], i[4], i[5], i[6], i[7], s[0], s[1]);
mux2_1 m3(out,w[0],w[1], s[2]);

endmodule

// TEST BENCH

module mux8_1_tb_v;

// Inputs

reg [2:0] s; reg [7:0] i;

// Output
s wire out;

// Instantiate the Unit Under Test (UUT)

mux8_1 uut (.out(out), .s(s), .i(i)); initial
begin

// Initialize
Inputs s = 0; i = 0;

// Wait 100 ns for global reset to

finish #100; s=3'b000; i=8'b00000001;

#100; s=3'b001; i=8'b00000010; #100;

s=3'b010; i=8'b00000100; #100;

s=3'b011; i=8'b00001000; #100;

s=3'b100; i=8'b00010000;
 #100; s=3'b101; i=8'b00100000;

#100; s=3'b110; i=8'b01000000;

#100; s=3'b111; i=8'b10000000;

end

endmodule

Waveforms – Problem 2

Fig 2.(a) 2 X 1 MUX Using Data Flow Model

Fig 2 4 X 1 MUX Using Behavioral Model

Fig 2.(b) 8 X 1 MUX Using 4 X 1 MUX and 2 X 1

1.5 Post lab

Draw the block diagram of 4x16 decoder. Use 3x8 decoder to design 4x16 decoder.
1.6 Result:
Thus the design of combinational logic circuits was simulated in Verilog and synthesized
using EDA tools.
 Lab Experiment #2
Design of Sequential Circuits

2.1 Objective: To learn the design of sequential circuits in Verilog then simulating
and synthesizing using EDA tools
2.2 Software tools Requirement
Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
2.3 Prelab Questions
(write pre lab Q & A in an A4 sheet)

1. Write the difference between initial and always block.

2. List the Reduction and Logical Operators.
3. Give the use of Blocking and Nonblocking statments.
4. Differentiate case, casex and casez statements.
2.4.1 Problem 1: Write a Verilog code to implement Flip flops.
The following points should be taken care of:
1. Use If statement to design positive edge triggered SR flip
2. Use case statement to design negative edge triggered JK and T flip flop
Logic Diagram – Problem 1
Verilog Code - Problem 1
1.(a) POSITIVE EDGE TRIGGERED SR FLIPFLOP USING IF STATEMENT

module srff(q, s, r, clk, clr);

output q;

input s;

input r;

input clk;

input clr;

reg q;

initial

q=0;

always @(posedge clk)

begin

if(clr==1)

q=0;

else if(s==0&&r==0)

q=q;

else if(s==1&&r==0)

q=s;

else if(s==0&&r==1)

q=0;

else

q=1'bz;

end

endmodul
e
// TEST BENCH

module srfflop_v;

// Inputs

reg s; reg r; reg clk; reg clr;

// Output
s wire q;

// Instantiate the Unit Under Test (UUT)

srff uut (.q(q),.s(s),.r(r),.clk(clk),.clr(clr));
initial begin

// Initialize Inputs

s = 0; r = 0; clk = 0; clr = 0;

// Wait 100 ns for global reset to

finish #100 s=0;r=0;clk=0;clr=0;

#100 s=0;r=0;clk=1;clr=0;

#100 s=0;r=1;clk=0;clr=0;

#100 s=0;r=1;clk=1;clr=0;

#100 s=1;r=0;clk=0;clr=0;

#100 s=1;r=0;clk=1;clr=0;

#100 s=1;r=1;clk=0;clr=0;

#100 s=1;r=1;clk=1;clr=0;

// Add stimulus here

end

endmodule

1.(b.1) NEGATIVE EDGE TRIGGERED JK FLIPFLOP USING CASE STATEMENT

module jkff(q, clk, clr, j, k);

output q;

input clk;

input clr;
 input j;

input k;

reg q;

initial

q=0;

always@(negedge clk)

begin

case({j,k})

2'b00: q=q;

2'b01: q=0;

2'b10: q=1;

2'b11: q=~q;

endcase

end

endmodule

// TEST BENCH

module jkff_tb_v;

// Inputs

reg clk; reg clr; reg j; reg k;

// Output
s wire q;

// Instantiate the Unit Under Test (UUT)

jkff uut (.q(q),.clk(clk),.clr(clr),.j(j),.k(k));
initial begin

// Initialize Inputs

clk = 0; clr = 1; j = 0;k = 0;

#100; clr=0;

// Wait 100 ns for global reset to

finish #100; j=0; k=0;
 #100; j=0; k=1;
#100; j=1; k=0;
#100; j=1; k=1;

// Add stimulus here

end

always

#50 clk=~clk;

endmodule

1.(b.2) NEGATIVE EDGE TRIGGERED T FLIPFLOP USING CASE STATEMENT

module tffcase(q, clk, clr, t);

output q;

input clk;

input clr;

input t;

reg q;

initial

q=0;

always@(negedge clk)

begin

case({clr,t})

2'b00: q=q;

2'b10: q=0;

2'b01: q=~q;

endcase

end

endmodule

// TEST BENCH

module tffcase_tb_v;
 // Inputs

reg clk; reg clr; reg t;

// Output
s wire q;

// Instantiate the Unit Under Test (UUT)

tffcase uut (.q(q),.clk(clk),.clr(clr),.t(t));
initial begin

// Initialize Inputs
clk = 0; clr = 1; t = 0;

// Wait 100 ns for global reset to

finish #100; clr=0;

#100; clr=0; t=1;

// Add stimulus here

end

always

#50 clk=~clk;

endmodule
Waveforms – Problem 1

Fig 1.(a) SR Flipflop using IF statement

 Fig 1.(b.1) JK Flipflop using CASE statement

Fig 1.(b.2) T Flipflop using CASE statement

2.4.2 Problem 2: Write a Verilog code to implement Counters.

The following points should be taken care of:

1. Use T flip flop as a sub module to design 4-bit ripple counter.
2. Use behavioral model to design Up-Down Counter. When mode =’1’ do up counting
and for mode=’0’ do down counting.

Logic Diagram – Problem 2

Verilog Code - Problem 2

2.(a) RIPPLE COUNTER USING T FLIP FLOP

module ripple_counter_4_bit(q,clk,reset);
input clk,reset;
output[3:0]q;
T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);
endmodule

// TEST BENCH

module ripple_counter_4_bit_tb_v;

// Inputs

reg clr; reg clk;

// Outputs
wire [3:0] q;
 // Instantiate the Unit Under Test (UUT)
ripple_counter_4_bit uut
(.q(q),.clr(clr),.clk(clk));
initial begin

// Initialize Inputs
clr = 1; clk = 1;

// Wait 100 ns for global reset to finish

#100; clr=0;

// Add stimulus here

end

always

#50 clk=~clk;

endmodule

2.(b) UP DOWN COUNTER USING BEHAVIOURAL MODEL

module updowncntr(q, clr, clk, mod);

output reg [3:0] q;

input clr;

input clk;

input mod;

always@(posedge clk)

begin

case({clr,mod})

2'b11 : q=0;

2'b10 : q=0;

2'b01 : q=q+1;

2'b00 : q=q-1;

endcase

end
endmodule

// TEST BENCH

module updowncntr_tb_v;

// Inputs

reg clr; reg clk; reg mod;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

updowncntr uut (.q(q),.clr(clr),.clk(clk),.mod(mod));
initial begin

// Initialize Inputs

clr = 1; clk = 0; mod = 1;

// Wait 100 ns for global reset to
finish #100; clr=0;

#1000; mod=0;

// Add stimulus here

end

always

#50 clk=~clk;

endmodule

Waveforms – Problem 2

Fig 2.(a) Ring counter using T Flip Flop

 Fig 2.(b) Up Down counter using behavioural modelling

2.5 Post Lab :

Write a Verilog HDL Code to implement a SISO and PIPO shift registers.

2.6 Result:
Thus the design of sequential circuits is simulated in Verilog and synthesized using EDA tools.
 Lab Experiment #3
Design of VLSI Adder and multiplier

3.1 Objective: To learn the design of combinational logic circuits in Verilog then
simulating and synthesizing using EDA tools

3.2 Software tools Requirement

Equipment’s:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE
Simulation tool: ModelSim Simulator

3.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)

1. Explain the logic for Booth encoding multiplier.

3.4 problem statement

3.4.1 Design the carry look ahead adder and carry skip adder.

Logic Diagram – Problem 1

CARRY LOOKAHEAD ADDER:

Verilog Code - Problem 1-CARRY LOOKAHEAD ADDER:

module CLA_4bmod(sum,c_4,a,b,c_0);
input [3:0]a,b;
input c_0;
output [3:0]sum;
output c_4;
wire p0,p1,p2,p3,g0,g1,g2,g3;
wire c1,c2,c3,c4;
assign
p0=a[0]^b[0],
p1=a[1]^b[1],
p2=a[2]^b[2],
p3=a[3]^b[3],
g0=a[0]&b[0],
g1=a[1]&b[1],
g2=a[2]&b[2],
g3=a[3]&b[3];
assign
c1=g0|(p0&c_0),
c2=g1|(p1&g0)|(p1&p0&c_0),
c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&c_0),
c4=g3|(p3&g2)|(p3&p2&p1&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&c_0);
assign
sum[0]=p0^c_0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3,
c_4=c4;
endmodule

Carry Lookahead Adder_TB

module Cla_tb_v;
reg [3:0] a; reg [3:0] b; reg c_0;
wire [3:0] sum; wire c_4;
Cla uut (
.sum(sum),
.c_4(c_4),
.a(a),
.b(b),
.c_0(c_0)
);
initial begin
a = 0; b = 0; c_0 = 0;
#100 a = 0; b = 1; c_0 =1;
#100 a = 1; b = 1; c_0 =1;
#100 a = 0; b = 0; c_0 =1;
end
endmodule
 Logic Diagram – Problem 1-CARRY SKIP ADDER:

Verilog Code - Problem 1-CARRY SKIP ADDER:

module carry_skip_4bit(a, b, cin, sum, cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (a[3:0],b[3:0],cin,sum[3:0],c0);
generate_p p1(a,b,p,bp);
mux2X1 m0(c0,cin,bp,cout);
endmodule
//////////////////////////////////////////////////////////////////////////////////////
// Propagate Generation
/////////////////////////////////////////////////////////////////////////////////////
module generate_p(a,b,p,bp);
input [3:0] a,b;
output [3:0] p;
output bp;
assign p= a^b;//get all propagate bits
assign bp= &p;// and p0p1p2p3 bits
endmodule
//////////////////////////////////////////////////////////////////////////////////////
//4-bit Ripple Carry Adder
/////////////////////////////////////////////////////////////////////////////////////
module ripple_carry_4_bit(a, b, cin, sum, cout);
input [3:0] a,b;
input cin;
wire c1,c2,c3;
output [3:0] sum;
output cout;
full_adder fa0(a[0], b[0],cin, sum[0],c1);
full_adder fa1(a[1], b[1],c1, sum[1],c2);
full_adder fa2(a[2], b[2],c2, sum[2],c3);
full_adder fa3(a[3], b[3],c3, sum[3],cout);
endmodule
//////////////////////////////////////////////////////////////////////////////////////
//1bit Full Adder
/////////////////////////////////////////////////////////////////////////////////////
module full_adder(a,b,cin,sum, cout);
input a,b,cin;
output sum, cout;
wire x,y,z;
half_adder h1(a,b,x,y);
half_adder h2(x,cin,sum,z);
or or_1(cout,z,y);
endmodule
/////////////////////////////////////////////////////////////////////////////
// 1 bit Half Adder
//////////////////////////////////////////////////////////////////////
module half_adder( a,b, sum, cout );
input a,b;
output sum, cout;
xor xor_1 (sum,a,b);
and and_1 (cout,a,b);
endmodule
//////////////////////////////////////////////////////////////////////////////////////
//2X1 Mux
/////////////////////////////////////////////////////////////////////////////////////
module mux2X1( in0,in1,sel,out);
input in0,in1;
input sel;
output out;
assign out=(sel)?in1:in0;
endmodule

Carry Skip Adder_TB

module carry_skip_4bit_tb_v;
reg [3:0] a; reg [3:0] b; reg cin;
wire [3:0] sum;
wire cout;
carry_skip_4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
a = 0; b = 0; cin = 0;
#100 a=1010;b=1000;cin=1;
#100 a=1001;b=1010;cin=0;
#100 a=0101;b=0010;cin=1;
#100 a=0010;b=0101;cin=0;
end
endmodule

3.4 Waveforms – Problem 1

Fig 3.(a) Carry Lookahead Adder

Fig 3.(a) Carry Skip adder

3.4.2 Design the bruan array multiplier and Wallace tree multiplier.
Logic Diagram – Problem 2

4 bit Multiplier
Verilog Code - Problem 2

module braun_mul(a,b,p);
input [3:0]a,b;
output[7:0]p;
wire[32:1]w;
and g1(p[0],a[0],b[0]);
and g2(w[1],a[1],b[0]);
and g3(w[2],a[2],b[0]);
and g4(w[3],a[3],b[0]);
and g5(w[4],a[0],b[1]);
and g6(w[5],a[1],b[1]);
and g7(w[6],a[2],b[1]);
and g8(w[7],a[3],b[1]);
and g9(w[8],a[0],b[2]);
and g10(w[9],a[1],b[2]);
and g11(w[10],a[2],b[2]);
and g12(w[11],a[3],b[2]);
and g13(w[12],a[0],b[3]);
and g14(w[13],a[1],b[3]);
and g15(w[14],a[2],b[3]);
and g16(w[15],a[3],b[3]);
fadd f1(p[1],w[16],w[1],w[4],1'b0);
fadd f2(w[32],w[17],w[5],w[2],1'b0);
fadd f3(w[31],w[18],w[3],w[6],1'b0);
fadd f4(p[2],w[19],w[8],w[32],w[16]);
fadd f5(w[30],w[20],w[31],w[9],w[17]);
fadd f6(w[29],w[21],w[7],w[10],w[18]);
fadd f7(p[3],w[22],w[30],w[12],w[19]);
fadd f8(w[26],w[23],w[29],w[13],w[20]);
fadd f9(w[25],w[24],w[11],w[14],w[21]);;
fadd f10(p[4],w[27],w[26],1'b0,w[22]);
fadd f11(p[5],w[28],w[25],w[27],w[23]);
fadd f12(p[6],p[7],w[15],w[28],w[24]);
endmodule

full adder:
module fadd(sum,carry,a,b,c);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule

Braun Array Multiplier_TB

module braun_mul_tb_v;
reg a; reg b; reg c;
wire sum;
wire carry;
fadd uut (
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.c(c)
);
initial begin
a = 0; b = 0; c = 0;
#100 a=4'b1111;b=4'b1010;
#100 a=4'b1001;b=4'b0101;
#100 a=4'b1000;b=4'b0110;
#100 a=4'b0111;b=4'b1110;
end
endmodule

LOGIC DIAGRAM: WALLACE TREE MULTIPLIER:

 x3y2 x2y2 x3y1 x1y2 x3y0 x1y1 x2y0 x0y1
P a r x3y3 t x2 y3 x1y3 lp
du
o
r xc
t0y3 x2y1 x0y2 x1y0 x0y0

F i r s s
ta
e
g
H A H A

S e c o F A F s
ta
e
g
A F A F A

F i n a a
d
r
e
z7 z6 z5 z4 z3 z2 z1 z0

VERILOG CODE FOR WALLACE TREE MULTIPLIER:

module wallace(A, B, prod);

input [3:0] A,B;
output [7:0] prod;
wire s11,s12,s13,s14,s15,s22,s23,s24,s25,s26,s32,s33,s34,s35,s36,s37;
wire c11,c12,c13,c14,c15,c22,c23,c24,c25,c26,c32,c33,c34,c35,c36,c37;
wire [6:0] p0,p1,p2,p3;
//initialize the p's.
assign p0 = A & {4{B[0]}};
assign p1 = A & {4{B[1]}};
assign p2 = A & {4{B[2]}};
assign p3 = A & {4{B[3]}};
//first stage
ha ha11 (p0[1],p1[0],s11,c11);
fa fa12(p0[2],p1[1],p2[0],s12,c12);
fa fa13(p0[3],p1[2],p2[1],s13,c13);
fa fa14(p1[3],p2[2],p3[1],s14,c14);
ha ha15(p2[3],p3[2],s15,c15);
//second stage
ha ha22 (c11,s12,s22,c22);
fa fa23 (p3[0],c12,s13,s23,c23);
fa fa24 (c13,c32,s14,s24,c24);
fa fa25 (c14,c24,s15,s25,c25);
fa fa26 (c15,c25,p3[3],s26,c26);
//third stage
ha ha32(c22,s23,s32,c32);
ha ha34(c23,s24,s34,c34);
ha ha35(c34,s25,s35,c35);
ha ha36(c35,s26,s36,c36);
ha ha37(c36,c26,s37,c37);
//final product assignments
assign prod[0] = p0[0];
assign prod[1] = s11;
assign prod[2] = s22;
assign prod[3] = s32;
assign prod[4] = s34;
assign prod[5] = s35;
 assign prod[6] = s36;
assign prod[7] = s37;
endmodule

Wallace Tree Multiplier_TB

module wallace_tb_v;
reg [3:0] A; reg [3:0] B;
wire [7:0] prod;
wallace uut (
.A(A),
.B(B),
.prod(prod)
);
initial begin
A = 0; B = 0;
#100 A=4'b1111;B=4'b1010;
#100 A=4'b1001;B=4'b1100;
#100 A=4'b0110;B=4'b1101;
#100 A=4'b0111;B=4'b1110;
#100;
end
endmodule

3.5 Waveforms – Problem 2

Fig 3(b) 4-bit Braun array multiplier

 Fig 3(b) 4-bit Wallace Tree multiplier

3.5 Postlab question

1. Write the program for booth encoding multiplier using verilog.

3.6 Result:
Thus the design of VLSI adders and multipliers is simulated in Verilog and synthesized using
EDA tools.
 Lab Experiment #4
Design of FSM
4.1 Objective: To learn the design of FSM for any application in Verilog then simulating and
synthesizing using EDA tools
4.2 Software tools Requirement
Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
4.3 Prelab Questions
(write pre lab Q & A in an A4 sheet)

1. Draw the simple model of FSM.

2. What is the basic algorithm for sequence detector.
3. List the difference between Mealy and Moore Model.

4.4 Problem 1: Implement Sequence Recognizer for detecting three successive 1’s using
Verilog code.

Logic Diagram – Problem 1

State Diagram
4.4 Verilog Code - Problem 1
module fsm( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule
// TEST BENCH
module fsm_tb_v;
reg clk, rst, inp;
wire outp; reg[15:0]
sequence; integer i;
fsm dut( clk, rst, inp, outp);
initial
begin
clk = 0; rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;
for( i = 0; i <= 15; i = i + 1)
begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
end
test2;
end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
#2 clk = 1;
#2 clk = 0;
end
endtask
endmodule

4.4.Waveforms – Problem 1

Fig. Sequence recognizer for detecting three successive 1’s

4.5 Post Lab Question: Write a Verilog code to implement an FSM. (For any application)

4.6 Result: Thus, the design of FSM for any application is simulated in Verilog and
synthesized using EDA tools.
 Lab Experiment #5

Design of Barrel shifter

5.1 Objective: To learn the design of sub-circuit design in Verilog then simulating and
synthesizing using EDA tools

5.2 Software tools Requirement

Equipment’s:

Computer with Xilinx and Modelsim Software Specifications:

 HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Synthesis tool: Xilinx ISE

Simulation tool: ModelSim Simulator

5.3 Pre-lab Questions

(write pre lab Q & A in an A4 sheet)

1. Explain the logic for Barrel shifter.

 5.4 Problem statement

5.4.1 Design the 8 -bit barrel shifter using multiplexer.

5.4.1 Logic Diagram – Problem 1

5.4.2 Verilog Code - Problem 1

Barrel Shifter
module barrel(q,d,s);
input [7:0]d;
input [2:0]s;
output[7:0]q;
mux8_1 m1(q[0],d,s);
mux8_1 m2(q[1],{d[0],d[7:1]},s);
mux8_1 m3(q[2],{d[1:0],d[7:2]},s);
mux8_1 m4(q[3],{d[2:0],d[7:3]},s);
mux8_1 m5(q[4],{d[3:0],d[7:4]},s);
mux8_1 m6(q[5],{d[4:0],d[7:5]},s);
mux8_1 m7(q[6],{d[5:0],d[7:6]},s);
mux8_1 m8(q[7],{d[6:0],d[7]},s);
endmodule
//TEST BENCH:
module bs_t_v;
reg [7:0] d; reg [2:0] s;
wire [7:0] q;
bs uut (.q(q), .d(d), .s(s));
initial begin
d = 01011010; s = 000; #100;
d = 01011010; s = 001; #100;
d = 01011010; s = 010; #100;
d = 01011010; s = 011; #100;
d = 01011010; s = 100; #100;
d = 01011010; s = 101; #100;
d = 01011010; s = 110; #100;
d = 01011010; s = 111;
end
endmodule

5.4 Waveforms – Problem 1

Fig. 5.4 8 Bit Barrel shifter

5.5 Post lab

1. Write the program for Linear feedback shift register using verilog.

5.6 Result: Thus, the design of 8 Bit Barrel Shifter is simulated in Verilog and synthesized
using EDA tools.
 Lab Experiment #6
Design of Digital circuits at the MOS transistor level
6.1 Objective: To learn the design of Digital circuits at the MOS transistor level Using Switch
Level Modeling.

6.2 Software tools Requirement

Equipments:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

6.3 Pre -Lab Questions

1. Describe the various constructs to model switch level circuits.

2. What is the difference between regular switches and resistive switches.
3. Draw the circuit diagram for CMOS inverter using pmos and nmos switches and write
the verilog code using switch level modeling.

6.4 Problem Statement

6.4.1: Design inverter logic using verilog switch level modeling and verify the simulation
result using test bench.

Logic Diagram-Problem 1

6.4.2 Verilog Code - Problem 1

CMOS Inverter
module inverter(out,data);
output out;
input data;
supply1 vdd;
supply0 gnd;
pmos p1(out,vdd,data);
nmos n1(out,gnd,data);
endmodule
CMOS Inverter_TB
module inverter_tb_v;
reg data;
inverter uut (.out(out), .data(data));
initial begin
data = 0;
#100 data = 1;
end
endmodule

6.4 Waveforms – Problem 1

Fig 6.4.1 CMOS inverter

6.4.2 Design two input CMOS NAND , NOR logic using verilog switch level modeling and
verify the simulation result using testbench.

Logic Diagram-Problem 2

Fig Two input NAND Fig Two input NOR

6.4.2 Verilog Code - Problem 2

CMOS NAND Logic

module nandcmos(out,a,b);
wire t;
output out;
input a,b;
supply1 vdd;
supply0 gnd;
pmos m1(out,vdd,a);
pmos m2(out,vdd,b);
nmos m3(out,t,a);
nmos m4(t,gnd,b);
endmodule

CMOS NAND Logic_TB

module nandcmos_tb_v;
reg a; reg b;
wire out;
nandcmos uut (
.out(out), .a(a), .b(b)
);
initial begin
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
end
endmodule

CMOS NOR Logic

module norcmos(out,a,b);
wire t;
output out;
input a,b;
supply1 vdd;
supply0 gnd;
pmos m1(t,vdd,a);
pmos m2(out,t,b);
nmos m3(out,gnd,a);
nmos m4(out,gnd,b);
endmodule

CMOS NOR Logic_TB

module norcmos_tb_v;
reg a; reg b;
wire out;
norcmos uut (.out(out), .a(a), .b(b));
initial begin
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
end
endmodule
6.4 Waveforms – Problem 2

Fig 6.4 Two input NAND

Fig 6.4 Two input NOR

6.4.3: Design 2:1 Mux using CMOS switches and write verilog coding using switch level
modeling and verify the simulation result.

Logic Diagram-Problem 3

2:1 Mux USING cmos

6.4.3 Verilog Code - Problem 3

CMOS Mux 2X1

module cmos_mux(out,s,i1,i0);
output out;
input s,i0,i1;
wire sbar;
not n1(sbar,s);
cmos(oout,i0,sbar,s);
cmos(out,i1,s,bar);
endmodule

CMOS Mux 2X1_TB

module cmos_mux_tb_v;
reg s;reg i1;reg i0;
wire out;
cmos_mux uut (.out(out), .s(s),
.i1(i1),.i0(i0));
initial begin
s = 0;i1 = 1;i0 = 0; #100;
s = 0;i1 = 0;i0 = 1; #100;
s = 1;i1 = 0;i0 = 1; #100;
s = 1;i1 = 1;i0 = 1;
end
endmodule

6.4.3 Waveforms – Problem 3

Fig 6.4.3 2X1 Multiplexer using CMOS

6.5 Post Lab Question:

1. Define a memory element to store a value and design a level sensitive CMOS latch .
2. Draw the CMOS logic circuit for the following boolean expression
A(D+E)+BC

6.6 Result: Thus, the design of combinational circuit using switch level modeling is
simulated in Verilog and synthesized using EDA tools.
 TANNER SPICE

Ex.No.7 CMOS FLIP FLOPS Date:

AIM
To simulate and execute CMOS flip flops using Tanner Spice tool.

SOFTWARE REQUIRED
LT SPICE
PROCEDURE
1. Open LT Spice
2. Click File – New Schematic
3. Place the component, Edit- component
4. Connect the components, Edit- Draw wire
5. Place the ground, Edit- Place_Gnd
6. Place Label, Edit- Label_Net
7. Simulate the circuit , Simulate _ Run
8. Set the Transient response
9. Click the markers at input node and output node to verify the waveform.
SR FLIPFLOP
LOGIC DIAGRAM

OUTPUT GRAPH
D FLIPFLOP

LOGIC DIAGRAM

OUTPUT GRAPH

Result:

Thus the CMOS flip flops are simulated and outputs are executed using Tanner Spice tool.
Ex.No.8 CMOS LOGIC GATES AND CIRCUITS Date:

AIM
To simulate and execute CMOS logic gates and circuits using Tanner Spice
SOFTWARE REQUIRED
LT SPICE
PROCEDURE
1. Open LT Spice
2. Click File – New Schematic
3. Place the component, Edit- component
4. Connect the components, Edit- Draw wire
5. Place the ground, Edit- Place_Gnd
6. Place Label, Edit- Label_Net
7. Simulate the circuit , Simulate _ Run
8. Set the Transient response
9. Click the markers at input node and output node to verify the waveform.
NAND GATE LOGIC DIAGRAM

OUTPUT GRAPH
NOR GATE

LOGIC DIAGRAM

OUTPUT GRAPH
INVERTER

LOGIC DIAGRAM

OUTPUT GRAPH

Result:

Thus the CMOS logic gates are simulated and outputs are executed using Tanner Spice tool.
Ex.No.9 DYNAMIC CIRCUITS Date:

AIM
To simulate and execute dynamic circuit(NAND Gate) using Tanner Spice

SOFTWARE REQUIRED
LT SPICE

PROCEDURE
1. Open LT Spice
2. Click File – New Schematic
3. Place the component, Edit- component
4. Connect the components, Edit- Draw wire
5. Place the ground, Edit- Place_Gnd
6. Place Label, Edit- Label_Net
7. Simulate the circuit , Simulate _ Run
8. Set the Transient response
9. Click the markers at input node and output node to verify the waveform.

Logic diagram - Dynamic circuit(NAND Gate)

Output Waveform

Result:

Thus the dynamic circuit(NAND Gate) is simulated and output is executed using Tanner Spice
tool.