IR DROP

IR drop is the voltage drop across the metal straps that are used in power grids due to the resistance of
these metal straps or metal wires). Instead of actually carrying VDD to the standard cells, it will carry
Vdd – IR drop because of which there may be timing violations since delay is dependant on Vdd and if
there are fluctuations in Vdd, there will be setup and hold timing violations.

2 types:

Static IR Drop – also called as RC drop (due to the RC value of the metal straps used in the power grids)

Static IR drop may be due to long wire length, high fanout nets, high routing congestion

Dynamic IR Drop – also called as Voltage Droop (due to the switching activity of the standard cells)

Here, it actually creates bumps when multiple standard cell capacitances (wire cap) switch from H->L or
L->H asking for high current demand.

Should be checked during different RC corners and different PVT conditions (especially during OCV)

How to reduce IR Drop?

1. Adding more stripes

2. Spread the logic (if hotspots are at congested areas)
3. Using low power cells
4. Adding proper vias
5. Clock gating
6. Proper CTS structure (Minimizing clock buffers in clock tree as they switch very frequently)
 CTS

Different types of Clock Trees ?

• H-Tree (easy to implement, low skew, consumes lot of power, lot of routing resource)
• Clock Grid or Mesh (very easy to build, area inefficient, consumes power)

• Reset Tree ( Normally used to reset the flops at release of reset )

Cost function of Simulated Annealing : Area + (lamda) * Wirelength

Electromigration
Electromigration (EM) refers to the unwanted movement of materials in a
semiconductor. If the current density is high enough, there can be a momentum
transfer from moving electrons to the metal ions that make up the lattice of the
interconnect material. The ions will drift in the direction of the electron flow. The
result is the gradual displacement of metal atoms in a semiconductor, potentially
causing open and short circuits.

How to reduce EM?

• Widen the wire to reduce current density

• Reduce the frequency
• Lower the supply voltage
• Keep the wire length short ( this will provide a less reservoir to store knock off ions)
• Reduce buffer size in clock lines
What is Latchup ?

Latch up is the generation of a low-impedance path in CMOS chips between the power supply
and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs
for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and
the ground rail.

Antenna Rule Check?

Modern wafer processing happens through Plasma etch. Due to this there is
unintended high field stressing of the gate oxide due to the accumulation of charge
across the metal wires (antenna). The gate of the transistor acts like a capacitor and
there is excess potential build up as these charges flow down to the gate and can
potentially damage the gate in the long run.

For this reason there is an antenna ratio or antenna rule defined which is the ratio
of the area of the metal wire/conductor making up the antenna to the area of the
gate to which this antenna is electrically connected. If this ratio is large(>1000),
there is a high chance of the gate getting damaged.

If Area of metal/Area of gate > 1000, there is violation.

How can we counter Antenna issues ?

Bridging of adding jumpers (Like a metal 2 in between Metal 1 and Metal 3, so that
there is minimal charge accumulation going into the gate since its breaks a long
wire)

Diode insertion (Reverse biased diode)

What DRC issues you face?

- Tap cell issues ( how many to put in design )

- Via should be placed at 5mm and 2mm on either sides