BQ3123 SOP16

315/433MHZ Low Power Receiver

Application Note

Version 1.03

April, 2013

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 Application Note BQ3123 SOP16
Table of Contents
Table of Contents…...…..........................................................................................................2
1. IC Description……...............................................................................................................3
1.1. Pin Configuration...........................................................................................................3
1.2. Pin functions…….….......................................................................................................4
2. Module Description.............................................................................................................5
2.1. 315MHz Schematic……..................................................................................................5
2.2. 433MHz Schematic…………………………………………………………………………….6
2.3. Pin Assignment for Connector......................................................................................7
2.4. Absolute Maximum Ratings…………………………………………………………………7
2.5. General RF Characteristics………………………………………………………………….8
2.6. PCB Layout Consideration............................................................................................9
2.7. Signal suppression circuit…………………………………………………………………...9
3. Smith Plot of ANT PIN…………………………………………………………………………..10
4. ANTENNA DESIGN………………….…………………………………………………………...11
5. Function Description……………………………………………………………………………11
5.1. Detail Description……………………………………………………………………………..11
5.2. Voltage Regulator……………………………………………………………………………..12
5.3. RF Front-end (LNA & Mixer)…………………………………………………………………12
5.4. Phase-locked Loop (PLL)…………………………………………………………………….12
5.5. Image-rejection Filter and Band-Pass Filter………………………………………………12
5.6. Received-signal Strength Indictor (RSSI)…………………………………………………12
5.7. Automatic Gain Control (AGC)……………………………………………………………...12
5.8. Data Slicer………………………………………………………………………………………13
6. PCB Component List……………………………………………………………………………13
6.1. PCB Component List 315MHz.....................................................................................13
6.2. PCB Component List 433.92MHz ..……………….……………………………………....14
7. Xtal frequency table.……………………………………………………………………………15
8. Typical Operation Characteristic……………………………………………………………..18
9. Package Information……………………………………………………………………………19

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 Application Note BQ3123 SOP16
1. IC Description
1.1. Pin Configuration

Figure 1. BQ3123 pin assignment (top view) for the 16-Pin SOP Package

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 Application Note BQ3123 SOP16
1.2. Pin functions
Pin Pin Name Pin Function
1 DSN Negative input of differential Data-slicer. Connect an external capacitor this pin to GND.
2 DSP Positive input of differential Data-slicer. Connect an external capacitor this pin to GND.
High frequency or low frequency application select. 1: 433MHz application, 0: 315MHz
3 HL_side
application
4 CE Chip enable pin. Pull high enable the chip
5 AGND Negative supply connection for analog part.
6 ANT Antenna input: RF signal input from antenna. Internally AC coupled
7 RFGND Ground connection for ANT RF input.
Low-noise amplifier output. Must be connected to AVDD through a parallel LC tank
8 LNA_out
circuit. Different application frequency need different external LC tank.
Internal LDO Output, positive supply connection for all analog functions. Bypass with
9 AVDD
1uF capacitor located as close to AVDD pin as possible.
10 VCC_HV 2.1 ~ 5.2V Regulator input.
11 Rref Current reference terminal.
12 DO Demodulated data output.
Reference oscillator input: Reference resonator input connection to pierce oscillator
13 XTAL1
stage.
Reference oscillator input: Reference resonator input connection to pierce oscillator
14 XTAL2
stage.
Internal LDO Output, positive supply connection for all digital functions. Bypass with
15 DVDD
0.1uF capacitor located as close to DVDD pin as possible.
16 DGND Negative supply connection for digital part.
Table 1. BQ3123 pin function

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 Application Note BQ3123 SOP16
2. Module Description
2.1. 315MHz Schematic
VCC

R2
NA
R3 R10 100K
200K U1 BQ3123
C7 56nF 1 16
DSN DGND
VCC C8 0.1uF
C6 56nF 2 15 C9
DSP DVDD
18pF
R1 3 14 R9 Y1
HL_side XTAL2 16.3826M
NA NA
4 13 18pF
CE CE XTAL1
C10
5 12
AGND DO DO
C2
6 11 R4 200K C11
ANT ANT Rref 2.2nF
2pF5% 7 10
RFGND VCC_HV VCC
L1 L2 8 9 C5
C1 LNA_out AVDD 10uF
33nH 56nH 5%
6pF

L3
C3 68nH 5%
NA
J1 CON2 J2 CON4
1

4
C4
1uF
VCC
CE

DO
ANT

Figure. 2 Schematics of the BQ3123 (315MHz) Module Reference Design

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 Application Note BQ3123 SOP16
2.2. 433.92MHz Schematic

VCC

R2
200K
R3 R10 100K

NA U1 BQ3123
C7 56nF 1 16
DSN DGND
VCC C8 0.1uF
C6 56nF 2 15 C9
DSP DVDD
18pF
R1 3 14 R9 Y1
HL_side XTAL2 10.74064M
NA NA
4 13 18pF
CE CE XTAL1
C10
5 12
AGND DO DO
C2
6 11 R4 200K C11
ANT ANT Rref 2.2nF
1.5pF5% 7 10
RFGND VCC_HV VCC
L1 L2 8 9 C5
C1 LNA_out AVDD 10uF
33nH 33nH 5%
4pF

L3
C3 33nH 5%
1.5pF5%
J1 CON2 J2 CON4
1

4
C4
1uF
VCC CE

DO
ANT

Figure. 3 Schematics of the BQ3123 (433.92MHz) Module Reference Design

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 Application Note BQ3123 SOP16
2.3. Pin Assignment for Connector

J1 CON2 J2 CON4

4
VCC
ANT

DO
CE
Pin Name Description
J1,1 ANT Antenna input： RF signal input from antenna
J1,2 GND Ground connection

J2,1 VCC DC voltage supply

J2,2 CE Chip enable pin. Pull high enable the chip
J2,3 Data Out Demodulated data output
J2,4 GND Ground connection

2.4. Absolute Maximum Ratings

Rating Value Units
VDD Supply Voltage 2.1 to 5.2 V
Operation Temperature -40 to +85 ℃

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 Application Note BQ3123 SOP16
2.5. General RF Characteristics
Value
Parameter Condition Unit
Min Typ Max
fRX=315MHz, 1Kbps, BER=10-2 -106 dBm
Sensitivity
fRX=433MHz, 1Kbps, BER=10-2 -106 dBm
Shutdown to enable (VDD > 2V)
Valid data Out settling
Note(1)
RF Input power is in high-sensitivity level 5 ms
Data rate > 1Kbps
Continuous Operation (DC),
4.1 mA
fRX=315MHz
Operation Supply Current
Continuous Operation (DC),
4.2 mA
fRX=433MHz
Shut-down Current 1 uA
Reference Oscillator fRX=315MHz 16.3826 MHz
Frequency Note(2) fRX=433MHz 10.74064 MHz
Supply Voltage 2.1 3 5.2 V
Note:
(1):The Valid data out settling time depends upon the application data rate and encoding
pattern, the default value is for data rate > 1Kpbs with Manchester encoded pattern and the
value of C6 and C7 are 3.3nF.

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 Application Note BQ3123 SOP16
2.6. PCB Layout Consideration
1. Standard FR4 material is used in a two-layer PCB.
2. The BQ3123 DC supply voltage should be de-coupled as close as possible to the VCC
pins with high performance RF capacitors.
3. It is preferable to mount a large surface mount capacitor (e.g. 10µF tantalum) in parallel
with the smaller value capacitors.
4. Long power supply lines on the PCB should be avoided. All device grounds, VCC
connections and VCC bypass capacitors must be connected as close as possible to the
BQ3123 IC.
5. Full swing digital data or control signals should not be routed close to the crystal or the
power supply lines.
6. Additionally, there are ground areas on the component side of the board to ensure
sufficient grounding of critical components. A large number of via holes connect the top
layer ground areas to the bottom layer ground plane.
7. RF IO’s(ANT) trace must use 50 ohm transmission line.
8. The trace doesn’t pass through below RF_IO’s path.

2.7. Signal suppression circuit

This circuit can increase the noise interference suppression.

Note:
(1): Adjust R10 and R11 can control the intensity of the signal suppression
(2): Increased inhibition of the signal strength will affect the ability of the receiver.

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 Application Note BQ3123 SOP16
3. Smith Plot of ANT PIN
CH1 S11 ↑1 U 1: 5.565 ê -j194.5 ê
1 314.625 MHz
2: 2.113 ê -j137.9 ê
433.625 MHz
0.5 2

5
CAL

0 0.2 0.5 1 2 5 10

CPL

-5
1

2
FIL
1k

-0.5 -2

-1
START 200 MHz STOP 550 MHz

Date: 30.DEC.11 18:58:58

Figure 4. Smith Plot of ANT 315MHz

CH1 S11 ↑1 U 1: 10.62 ê -j181.2 ê

1 314.625 MHz
2: 4.955 ê -j128.9 ê
433.625 MHz
0.5 2

5
CAL

0 0.2 0.5 1 2 5 10

CPL

-5

2 FIL
1k

-0.5 -2

-1
START 200 MHz STOP 550 MHz

Date: 30.DEC.11 18:53:52

Figure 5. Smith Plot of ANT 433.92MHz

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 Application Note BQ3123 SOP16
4. ANTENNA DESIGN
For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L
(in cm), may be calculated by using the formula

the RF input matching circuit may need to be re-optimized. Note that in general, the shorter
the antenna, the worse the receiver sensitivity and the shorter the detection distance. Usually,
when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter
about 0.8 mm to 1.6 mm) rather than a multiple core wire.
If the antenna is printed on the PCB, ensure there is neither any component nor ground plane
underneath the antenna on the backside of PCB. For an FR4 PCB (εr = 4.7) and a strip-width
of 30 mil, the length of the antenna, L (in cm), is calculated by

433MHz：
Wavelength λ/4: about 165mm

315MHz：
Wavelength λ/4: about 226mm

Generally speaking, the lower the frequency, the wider the diameter required.
1) When the more numbers of been bended the antenna, the shorter the length total of the
demand.
2) When the more numbers of been bended the antenna, the lower the efficiency / gain value.
3) Bending point of the antenna that has frequency response

5. Function Description
5.1. Detail Description
The BQ3123 CMOS RF receiver, and a few external components, provides the complete
receiver chain from the antenna to the digital output data. Depending on signal power and
component selection, data rates as high as 20Kbps Manchester code can be achieved.
The BQ3123 is designed to receive binary ASK/OOK data modulated in the 300MHz to
450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to
represent digital data
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 Application Note BQ3123 SOP16
5.2. Voltage Regulator
BQ3123 provides two internal voltage regulators to the whole receiver blocks. The
regulator input pin is VCC_HV (pin 10). Pin AVDD (pin 9) is BQ3123 analog part’s supply
source and pin DVDD (pin 15) is digital parts’. Bypass capacitor 1uF is needed to connect to
pin AVDD as close as possible and 0.1uF capacitor is needed to connect to pin DVDD as
close as possible.

5.3. RF Front-end (LNA & Mixer)

The signal is received and amplified by RF front-end. The LNA and mixer have achieved
voltage gain and excellent reversed isolation at LNA input port. The gain and noise figure are
dependent on both the antenna matching network at the LNA input and LC tank network
between the LNA output and the mixer inputs. The ANT pin can be matched to 50 Ohms with
L-type circuit as shown on application circuit. Inductor and capacitor values may be different
from table depend on PCB material, PCB thickness, ground configuration, how long the trace
are in the layout and also different application frequency.

5.4. Phase-locked Loop (PLL)

The PLL block contains a phase detector, charge pump, integrated loop filter, VCO,
asynchronous clock dividers, and crystal-oscillator driver. Beside the crystal and its loaded
capacitors, this PLL does not require any external components.

5.5. Image-rejection Filter and Band-Pass Filter

The IF ports of the mixer produce quadrature-down converted IF signals. These IF
signals are low-pass filtered to remove higher frequency products prior to the image rejection
filter where they are combined to reject the image frequency. The filter is fully integrated inside
the BQ3123 and IF bandwidth is 200 KHz.

5.6. Received-signal Strength Indictor (RSSI)

The RSSI circuit provides a DC output proportional to the logarithm of the input power
level. RSSI output voltage has a slope of about 18mV/dB (of input power). The RSSI
monotonic dynamic range exceeds 75dB. The OOK/ASK demodulation is done by comparing
the RSSI signal level.

5.7. Automatic Gain Control (AGC)

The AGC circuit monitors the RSSI output. Receiver Font End (FE) would switch to low gain
mode when RSSI indicate the receipted power higher than a power threshold. Low receiver
FE gain can improve circuit’s linearity for RF high power input. With the AGC function, the
BQ3123 can reliably produce an ASK output for RF input levels up to -25dBm.

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 Application Note BQ3123 SOP16
5.8. Data Slicer
Differential data slicer need two capacitors on Pin 1/2, the value of capacitor depends upon
the application data rate and encoding pattern. For data rate > 2Kpbs application, the
suggested value of C6 and C7 are 56nF with 12E encoded pattern and 3.3nF with
Manchester encoded pattern for start-up time saving. The valid data output settling time
during power on will increase when the value of capacitor becomes 56nF.

6. PCB Component List

6.1. PCB Component List 315MHz
QTY Vendor Part Value Part Reference P/N Size
1 Best Quality BQ3123 U1 SOP16
Surface mount capacitors
1 TDK 6pF C1 0402
1 TDK 2pF 5% C2 0402
1 TDK NA C3 0402
1 TDK 1uF C4 0402
2 TDK 56nF C6,C7 0402
1 TDK 0.1uF C8 0402
2 TDK 18pF C9,C10 0402
1 TDK 2.2nF C11 0402
1 TDK 10uF C5 0805
Surface mount resistors
2 SYNTON 200KΩ R3,R4 0402
1 SYNTON 100KΩ R10 0402
Surface mount inductors
1 TDK 33nH L1 0402
1 TDK 56nH 5% L2 0402
1 TDK 68nH 5% L3 0402
Crystal
1 AURUM 16.3826MHz(20ppm) Y1 49/US
Note :
(1) : The value of L1,C1,L2,C2 ,C3 and L3 may have to be adjusted with different PCB layout
and antenna requirement.

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 Application Note BQ3123 SOP16
(2) : The value of C6 and C7 depend on the application data rate and encoding pattern.
Default 56nF is for 12E encoding pattern with 2kbps. If data rate > 1Kbps with Manchester
encoded pattern, C6 and C7 can reduce to 3.3nF for start-up time saving.
6.2. PCB Component List 433.92MHz
QTY Vendor Part Value Part Reference P/N Size
1 Best Quality BQ3123 U1 SOP16
Surface mount capacitors
1 TDK 4pF C1 0402
1 TDK 1.5pF 5% C2 0402
1 TDK 1.5pF 5% C3 0402
1 TDK 1uF C4 0402
2 TDK 56nF C6,C7 0402
1 TDK 0.1uF C8 0402
2 TDK 18pF C9,C10 0402
1 TDK 2.2nF C11 0402
1 TDK 10uF C5 0805
Surface mount resistors
2 SYNTON 200KΩ R2,R4 0402
1 SYNTON 100KΩ R10 0402
Surface mount inductors
1 TDK 33nH L1 0402
1 TDK 33nH 5% L2 0402
1 TDK 33nH 5% L3 0402
Crystal
1 AURUM 10.74064MHz(20ppm) Y1 49/US
Note :
(1) : The value of L1,C1,L2,C2 ,C3 and L3 may have to be adjusted with different PCB layout
and antenna requirement.
(2) : The value of C6 and C7 depend on the application data rate and encoding pattern.
Default 56nF is for 12E encoding pattern with 2kbps. If data rate > 1Kbps with Manchester
encoded pattern, C6 and C7 can reduce to 3.3nF for start-up time saving.

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 Application Note BQ3123 SOP16
7. Xtal frequency table
The operation RF frequency range is from 300MHz to 450MHz, and IF frequency range is
from 0.9MHz to 1.2MHz.

HL_side Frf (MHz) Fif(MHz) Xtal (MHz) HL_side Frf (MHz) Fif(MHz) Xtal (MHz)
0 300 0.99 15.600522 0 326 1.10 16.951304
0 301 0.99 15.652696 0 327 1.10 17.003478
0 302 0.99 15.704870 0 328 1.10 17.055652
0 303 0.99 15.757043 0 329 1.10 17.107826
0 304 1.01 15.808174 0 330 1.10 17.160000
0 305 1.01 15.860348 0 331 1.10 17.212174
0 306 1.01 15.912522 0 332 1.10 17.264348
0 307 1.01 15.964696 0 333 1.10 17.316522
0 308 1.01 16.016870 0 334 1.10 17.368696
0 309 1.04 16.067478 0 335 1.10 17.420870
0 310 1.04 16.119652 0 336 1.10 17.473043
0 311 1.04 16.171826 0 337 1.13 17.523652
0 312 1.04 16.224000 0 338 1.13 17.575826
0 313 1.04 16.276174 0 339 1.13 17.628000
0 314 1.04 16.328348 0 340 1.13 17.680174
0 315 1.04 16.380522 0 341 1.13 17.732348
0 316 1.04 16.432696 0 342 1.13 17.784522
0 317 1.04 16.484870 0 343 1.13 17.836696
0 318 1.04 16.537043 0 344 1.16 17.887304
0 319 1.04 16.589217 0 345 1.16 17.939478
0 320 1.07 16.639826 0 346 1.16 17.991652
0 321 1.07 16.692000 0 347 1.16 18.043826
0 322 1.07 16.744174 0 348 1.16 18.096000
0 323 1.07 16.796348 0 349 1.20 18.146087
0 324 1.07 16.848522 0 350 1.20 18.198261
0 325 1.10 16.899130 0 351 1.20 18.250435

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 Application Note BQ3123 SOP16
HL_side Frf (MHz) Fif(MHz) Xtal (MHz) HL_side Frf (MHz) Fif(MHz) Xtal (MHz)
0 352 1.20 18.302609 1 377 0.99 9.333086
0 353 1.20 18.354783 1 378 0.99 9.357778
0 354 1.20 18.406957 1 379 0.99 9.382469
0 355 1.20 18.459130 1 380 0.99 9.407160
0 356 1.20 18.511304 1 381 0.99 9.431852
0 357 1.20 18.563478 1 382 0.99 9.456543
0 358 1.20 18.615652 1 383 0.99 9.481235
0 359 1.20 18.667826 1 384 0.99 9.505926
0 360 1.20 18.720000 1 385 0.99 9.530617
0 361 1.20 18.772174 1 386 0.99 9.555309
0 362 1.20 18.824348 1 387 1.01 9.580494
0 363 1.20 18.876522 1 388 1.01 9.605185
0 364 1.20 18.928696 1 389 1.01 9.629877
0 365 1.20 18.980870 1 390 1.01 9.654568
0 366 1.20 19.033043 1 391 1.01 9.679259
0 367 1.20 19.085217 1 392 1.03 9.704444
0 368 1.20 19.137391 1 393 1.03 9.729136
0 369 1.20 19.189565 1 394 1.03 9.753827
0 370 1.20 19.241739 1 395 1.03 9.778519
0 371 1.20 19.293913 1 396 1.03 9.803210
0 372 1.20 19.346087 1 397 1.03 9.827901
0 373 1.20 19.398261 1 398 1.03 9.852593
0 374 1.20 19.450435 1 399 1.03 9.877284
0 375 1.20 19.502609 1 400 1.03 9.901975
1 375 0.99 9.283704 1 401 1.03 9.926667
1 376 0.99 9.308395 1 402 1.03 9.951358

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 Application Note BQ3123 SOP16
HL_side Frf (MHz) Fif(MHz) Xtal (MHz)
1 403 1.03 9.976049 HL_side Frf (MHz) Fif(MHz) Xtal (MHz)
1 404 1.06 10.001481 1 429 1.11 10.620000
1 405 1.06 10.026173 1 430 1.11 10.644691
1 406 1.06 10.050864 1 431 1.11 10.669383
1 407 1.06 10.075556 1 432 1.11 10.694074
1 408 1.06 10.100247 1 433 1.11 10.718765
1 409 1.06 10.124938 1 434 1.11 10.743457
1 410 1.06 10.149630 1 435 1.11 10.768148
1 411 1.06 10.174321 1 436 1.14 10.793580
1 412 1.08 10.199506 1 437 1.14 10.818272
1 413 1.08 10.224198 1 438 1.14 10.842963
1 414 1.08 10.248889 1 439 1.14 10.867654
1 415 1.08 10.273580 1 440 1.14 10.892346
1 416 1.08 10.298272 1 441 1.14 10.917037
1 417 1.08 10.322963 1 442 1.14 10.941728
1 418 1.08 10.347654 1 443 1.14 10.966420
1 419 1.08 10.372346 1 444 1.14 10.991111
1 420 1.08 10.397037 1 445 1.14 11.015802
1 421 1.08 10.421728 1 446 1.14 11.040494
1 422 1.08 10.446420 1 447 1.14 11.065185
1 423 1.08 10.471111 1 448 1.16 11.090370
1 424 1.08 10.495802 1 449 1.16 11.115062
1 425 1.11 10.521235 1 450 1.16 11.139753
1 426 1.11 10.545926
1 427 1.11 10.570617
1 428 1.11 10.595309

Note:
(1) Use interpolation to get each interval of operating RF frequency and Xtal frequency.

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 Application Note BQ3123 SOP16
8. Typical Operation Characteristic

Fig. 4. RSSI curve of BQ3123. Fig. 5. Voltage regulator characteristic.

Fig. 6. Normalized selectivity of BQ3123. Fig. 7. Supply current V.S. supply voltage.

Fig. 8. Data out settling time after pofwer ON : < 5mS.

(Input power = -108dBm, C6/C7=3.3nF)

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 Application Note BQ3123 SOP16
9. Package Information

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