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2. Applications of diode: Half wave rectifier and Full wave rectifier, Clipper and
Clamper
Date: Expt.No:
Aim:
Apparatus required:
Circuit diagram:
(0 - 20)mA
R _
+
A
1k +
+
RPS _ V (0 - 20)V
(0 - 30)V _
ZenerDiode:ForwardCharacteristics:
R (0 - 200)A
_
+
A
1k +
+ (0 - 5)V
RPS _ V
(0 - 30)V _
(0 -200)mA
R _
+
A
1k +
+
RPS _ V (0 - 20)V
(0 -30)V _
V-I CHARACTERISTICS OF PN JUNCTION DIODE AND ZENER DIODE
Model graph:
Procedure:
5. To obtain the reverse characteristics, vary the voltage in the range of 1V and note down
the voltmeter and the corresponding ammeter readings.
6. Plot the graph, with the voltage along the X axis and current along the Y axis. This gives
the reverse characteristics of the diode.
7. Calculate the cut-in voltage or knee voltage of the diode from the graph. (Cut-in voltage
is the voltage from where the current starts flowing and diode is said to conduct. This
represents the diode in the forward region.)
8. Repeat the same procedure for Zener diode for both forward and reverse characteristics.
9. Calculate the Zener breakdown voltage of the Zener diode from the graph. (Zener
breakdown is the voltage at which the voltage across the Zener diode remains constant
and the current rises sharply under the reverse bias condition.)
Tabulation:
Result:
APPLICATIONS OF DIODE: HALF WAVE RECTIFIER AND FULL WAVE RECTIFIER, CLIPPER AND CLAMPER
Date: Expt.No:
Aim:
i. To construct a half wave rectifier circuit and draw the input-output waveform
ii. To construct a Full wave rectifier circuit and draw the input-output waveform
iii. To construct a Clipper circuit and draw the input-output waveform
iv. To construct a Clamper circuit and draw the input-output waveform
Apparatus required:
R
o
VIN D
VOUT
Vref
Positive Clamper:
C
o
VIN D RL VOUT
Model graph:
Positive Clamper:
Procedure:
1. Give the connections as per the circuit diagram for half wave rectifier.
2. Give a sine wave input of any amplitude and frequency using AFO.
3. Note the input and output in the CRO.
4. Repeat the same procedure for full wave rectifier, clamper and clipper.
5. Draw the waveforms for half wave and full wave rectifier, clipper and clamper.
Tabulation:
Output
APPLICATIONS OF DIODE: HALF WAVE RECTIFIER AND FULL WAVE RECTIFIER, CLIPPER AND CLAMPER
Output
Biased Clipper
Input
Below zero
axis: Below
zero
axis:
Clamper DC level:
Output
Result:
INPUT AND OUTPUT CHARACTERISTICS OF COMMON EMITTER CONFIGURATION
Date: Expt.No:
Aim:
To construct a Common Emitter (CE) circuit and plot its input and output characteristics
Apparatus required:
Base diagram:
Circuit diagram:
IC
_ RC
A +
RS IB C 1k
_ ( 0 -200mA) +
+ A
BC 107
B +
+ 100k ( 0 - 200A) E VCE VCC
+ V ( 0 - 30V)
VBB ( 0 - 20V)
_
( 0 - 30V) VBE V _
_ ( 0 - 20V) _
Model graph:
Input characteristics:
INPUT AND OUTPUT CHARACTERISTICS OF COMMON EMITTER CONFIGURATION
Output characteristics:
Procedure:
Tabulation:
Input characteristics
VCE1 = V VCE2 = V
Base Emitter voltage VBE Base current IB Base Emitter voltage VBE Base current IB
V µA V µA
INPUT AND OUTPUT CHARACTERISTICS OF COMMON EMITTER CONFIGURATION
Output characteristics:
IB1 = µA IB2 = µA
Collector Emitter voltageVCE Collector current IC Collector Emitter voltageVCE Collector current IC
V mA V mA
Result:
DRAIN AND TRANSFER CHARACTERISTICS OFJFET AND JFET AS A SWITCH
Date: Expt.No:
Aim:
i) To construct a JFET circuit and to plot its Drain and Transfer characteristics
ii) To construct the JFET circuit as a switch
Apparatus required:
Top View
Bottom View
DRAIN AND TRANSFER CHARACTERISTICS OFJFET AND JFET AS A SWITCH
VDD 12
RD 1 k
ID 12 10 3
Circuit diagram:
JFET as a switch
VDD
o
RD
o VOUT
D
G
VIN o
BFW10
S
DRAIN AND TRANSFER CHARACTERISTICS OFJFET AND JFET AS A SWITCH
Model graph:
Drain characteristics:
Transfer characteristics
DRAIN AND TRANSFER CHARACTERISTICS OFJFET AND JFET AS A SWITCH
JFET as a switch
Procedure:
Drain Characteristics:
Transfer Characteristics:
Tabulation:
Drain characteristics
VGS1 = V VGS2 = V
Drain to source voltage VDS Drain current ID Drain to source voltage VDS Drain current ID
V mA V mA
Transfer characteristics
VDS1 = V VDS2 = V
Gate to source voltage VGS Drain current ID Gate to source voltage VGS Drain current ID
V mA V mA
JFET as a switch
Output
Result:
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Date: Expt.No:
Aim:
Apparatus required:
Specifications of IC 741:
Design:
Inverting amplifier:
Rf
AV
R1
Given gain AV ,
Let R f
Rf
so that R1
AV
Non-Inverting amplifier:
Rf
AV 1
R
Given gain AV
Let R f
Rf
so that R
AV 1
Differential amplifier:
Rf R R f
Vout V2 V1 1 f
R R R f R
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Rf
Vout V1 V2 ;
R
Vout Rf
AV
V1 V2 R
Given AV
Let R
so that R f AV R
Circuit diagram:
Inverting amplifier:
Rf
R1 +VCC
Vin o
_
Rf
o Vout Vin
+ R1
-VCC
Rf
R1 +VCC
_
Rf
o Vout (1 )Vin
Vin o + R1
-VCC
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Differential amplifier:
Rf
R +VCC
V2 o _
Rf
o Vo (V1 V2 )
V1 o + R
R
-VCC
Rf
Model graph:
Inverting amplifier:
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Non-Inverting amplifier:
Procedure:
Inverting amplifier
Rf
4. Calculate the theoretical gain using the formula AV and compare the practical
R1
gain with the theoretical gain.
5. Draw the corresponding input and output waveforms.
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Rf
4. Calculate the theoretical gain using the formula AV 1 and compare the practical
R
gain with the theoretical gain.
5. Draw the corresponding input and output waveforms.
Differential amplifier
Vout Rf
4. Calculate the theoretical gain using the formula AV and compare
V1 ~ V2 R
practical gain with the theoretical gain.
Tabulation:
Inverting amplifier:
Output
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP
Output
Differential amplifier:
V V
Result:
SUMMER, SUBTRACTOR, INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Date: Expt.No:
Aim:
i. To design and construct a summer for V1= ---------- and V2= ------------- to get an output
of Vo = -(V1+V2)
ii. To design and construct a subtractor for V1= ---------- and V2= -------------to get an output
of Vo = V1-V2
iii. To construct an integrator circuit to integrate an input signal of frequency --------
iv. To construct a differentiator circuit to differentiate an input signal with fmax= --------.
Apparatus required:
6. Output resistance 75 Ω
7. Power consumption 85 mW(typical)
8. Slew rate for RL > 2kΩ 0.5 V / µs
Design:
Inverting Summer:
R f R
V0 V1 f V2
R1 R2
If R1 R2 R f then Vo V1 V2
Let R f
R1 R2 R f
Subtractor:
R R R
V0 1 V1 V2
R R R R
Vo V1 V2
Let R
Integrator:
Given f , Let C f
1
f
2R1C f
Therefore R1 .
Differentiator:
1
f max
2R f C1
SUMMER, SUBTRACTOR, INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Therefore R f .
Choose T R f C1
Circuit diagram:
Inverting summer:
Rf
R1
+VCC
V1 o
2 _
7 Rf Rf
R2 6 o Vo V1 V2
V2 o
3 R1 R2
+ 4
-VCC
Subtractor:
R +VCC
V2 o _
Vo (V1 V2 )
o
V1o +
R
-VCC
R
SUMMER, SUBTRACTOR, INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Integrator:
Cf
R1 +VCC
_
Vi(t) o
1
R1C f
o Vo (t ) Vi (t ) dt
+
-VCC
Differentiator:
Rf
C1 +VCC
_
Vi(t) o
dVi (t )
o Vo (t ) R f C1
+ dt
-VCC
SUMMER, SUBTRACTOR, INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Model graph:
Integrator
Differentiator:
SUMMER, SUBTRACTOR, INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
Procedure:
4. Calculate the theoretical Vo using the formula V0 (V1 V2 ) for summer and
V0 V1 V2 for subtractor.
4. Draw the input and the corresponding output waveforms in the graph.
Tabulation:
Inverting summer:
Subtractor:
Integrator:
Output
Differentiator:
Output
Result:
DESIGN OF SERIES AND SHUNT VOLTAGE REGULATOR USING TRANSISTOR
Date: Expt.No:
Aim:
i. To design and construct a series voltage regulator using transistor for Vin = ----------,
Vo = ------------- and RL = -------------
ii. To design and construct a shunt voltage regulator using transistor for Vin = ----------,
Vo = ------------- and RL = -------------
Apparatus required:
Design:
IZ = mA (from datasheet)
Vo VZ VBE
Vo
IE
RL
IE IC
IB
Vin VZ
R
IZ IB
IZ = mA (from datasheet)
Vo VZ VBE
Vo
IL and I B I Z
RL
I C I B
I S I Z IC I L
Vin Vo
RS
IS
DESIGN OF SERIES AND SHUNT VOLTAGE REGULATOR USING TRANSISTOR
Circuit diagram:
Series Regulator
L
O
Power Supply
A
D
L
O
Power Supply Shunt Regulator
A
D
IE
Vin T
o o Vo
R
IB
IZ+IB RL
IZ
VZ
DESIGN OF SERIES AND SHUNT VOLTAGE REGULATOR USING TRANSISTOR
IS RS
Vin o o Vo
IZ
IC
VZ
RL
T
Model graph:
Line regulation
3. Tabulate the output voltage Vo for different values of input voltage Vin for a particular
value of load resistance RL.
4. Plot the graph with input voltage Vin along X axis vs. output voltage Vo along Y axis.
DESIGN OF SERIES AND SHUNT VOLTAGE REGULATOR USING TRANSISTOR
Tabulation:
Line regulation:
RL = Ω
V V
DESIGN OF SERIES AND SHUNT VOLTAGE REGULATOR USING TRANSISTOR
Line regulation:
RL = Ω
V V
Result:
MEASUREMENT OF VOLTAGE, CURRENT, FREQUENCY AND PHASE USING CRO
Date: Expt.No:
Aim:
Apparatus required:
Circuit diagram:
Frequency measurement
CRO
o X Y o
AFO 1 AFO 2
o Gnd Gnd o
Formula:
Phase measurement
R
+ o
X o
Y
o
AFO C CRO
Gnd o o Gnd
MEASUREMENT OF VOLTAGE, CURRENT, FREQUENCY AND PHASE USING CRO
‘θ’ is the phase difference between the two waveforms given to the X and Y channel of the CRO.
a
It is calculated using the above diagram such that sin 1 where a - Minor axis diameter
b
and b – Major axis diameter
T 360 0
Theoretical value of where ‘T’ is the total time (3600) of the input signal and ∆T
T
is the time difference.
T 3600
Phase Shift
T
MEASUREMENT OF VOLTAGE, CURRENT, FREQUENCY AND PHASE USING CRO
Quadrant Formula
II and IV quadrant a
180 0 sin 1
b
I and III quadrant a
sin 1
b
Procedure:
Voltage measurement
Frequency measurement
Phase measurement
1. Give the circuit connections as per the diagram and apply a sine wave input.
2. Note the diameter of major and minor axis.
3. Calculate the phase angle theoretically and practically and compare them.
MEASUREMENT OF VOLTAGE, CURRENT, FREQUENCY AND PHASE USING CRO
Tabulation:
Frequency measurement
Phase measurement
THEORITICAL PRACTICAL
(Direct phase measurement) (Phase measurement using Lissajous figure)
T 360 0 a
Frequency (kHz) Phase difference Minor Axis Major Axis sin 1
T b
Diameter Diameter
‘a’ ‘b’
Result: