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1-A DC Motor Driver TLE 4205

Overview Bipolar IC

Features
● Max. driver current 1 A
● Integrated free-wheeling diodes
● Short-circuit proof to ground
● Inhibit
● ESD protected inputs
● Temperature range – 40 °C ≤ Tj ≤ 150 °C
P-DIP-18-3

P-DSO-20-6

Type Ordering Code Package


TLE 4205 Q67000-A9025 P-DIP-18-3
TLE 4205 G Q67006-A9114 P-DSO-20-6

Description
TLE 4205 is an integrated power full-bridge DC-motor driver for a wide temperature
range, as required in automotive applications for example. The circuit contains two
power comparators that can be combined to a full-bridge circuit. For inductive loads
there are integrated free-wheeling diodes to + VS and ground. The outputs are short-
circuit proof up to 18 V supply voltage to ground and turn off when overtemperature
occurs. This IC is especially suitable for headlight-beam adjustment in automobiles.

Semiconductor Group 1 1998-02-01


TLE 4205

TLE 4205 TLE 4205 G

Q1 1 18 Q2 1 20 VS
N.C. 2 19 Q1
VS 2 17 N.C. 3 18 N.C.
Q2 3 16 GND 4 17 GND
GND 5 16 GND
GND 4 15 GND 6 15 GND
GND GND 7 14 GND
-Ι2 5 14 must be connected
to Pin 4 - Ι2 8 13 N.C.
+Ι2 6 13 + Ι2 9 12 ΙNH
+Ι 1 10 11 -Ι 1
+ Ι1 7 12
AEP01318

- Ι1 8 11

INH 9 10

AEP00636

Figure 1 Pin Configuration (top view)

Semiconductor Group 2 1998-02-01


TLE 4205

Pin Definitions and Functions


Pin No. Symbol Function
1 Q1 Output Q1 of channel 1; push-pull B output with DC
short-circuit protection to ground. Integrated free-wheeling
diodes to ground and the supply voltage.
2 VS Supply voltage VS; must be blocked to ground with a ceramic
capacitor of at least 100 nF directly on the pins of the IC.
3 Q2 Output Q2 of channel 2; see pin 1.
4 GND Ground
5 – I2 Inverting input channel 2; to be wired according to general
rules.
6 + I2 Non-inverting input channel 2; to be wired according to
general rules.
7 + I1 Non-inverting input channel 1; see pin 6.
8 – I1 Inverting input channel 1; see pin 5.
9 INH Inhibit; the IC is passive when this pin is open or connected to
ground.
10-18 GND Ground; must be connected to pin 4.

Semiconductor Group 3 1998-02-01


TLE 4205

Pin Definitions and Functions (TLE 4205 G)


Pin No. Symbol Function
1 Q2 Output 2 of channel 2; push-pull B output with DC short-circuit
protection to ground. Integrated free-wheeling diodes to ground
and the supply voltage.
2 N.C. Not connected
3 N.C. Not connected
4-7 GND Ground
8 – I2 Inverting input channel 2; to be wired according to general
rules.
9 + I2 Non-inverting input channel 2; to be wired according to
general rules.
10 + I1 Non-inverting input channel 1; see pin 9.
11 – I1 Inverting input channel 1; see pin 8.
12 INH Inhibit; the IC is passive when this pin is open or connected to
ground.
13 N.C. Not connected
14-17 GND Ground
18 N.C. Not connected
19 Q1 Output Q1 of channel 1, see pin 1.
20 VS Supply voltage VS; must be blocked with a ceramic capacitor
of at least 100 nF directly on the pins of the IC.

Semiconductor Group 4 1998-02-01


TLE 4205

VS
2 (20)

T1
7
+ Ι1
(10) + 1
Q1
8 - (19)
- Ι1
(11)
T2

Power Limiting
9 for T1, T3
INH
(12) Temperature
Protection

T3
6
+Ι2
(9) + 3
Q2
5 - (1)
-Ι2
(8)
T4

(4-7)
4, 10-18 (14-17)
GND AEB00637

Figure 2 Block Diagram

Semiconductor Group 5 1998-02-01


TLE 4205

Circuit Description
The IC contains two amplifiers with typical open-loop gain of 80 dB at 500 Hz.
The input stages consist of PNP-differential amplifiers. This produces a common-mode
input range of 0 V to nearly VS and a maximum differential input voltage of VS. The IC is
guarded against ground shorts by an SOA-protective circuit. The output transistors are
turned off if the chip temperature exceeds approx. 160 °C. The IC can be turned off by
an inhibit input, which very much reduces current consumption.

VS
(2)

TLE 4205

(6) 10 k Ω 10 kΩ
+Ι2

(1)
(5) Q1
-Ι2
(8)
- Ι1
(3)
Q2

(7) 10 kΩ 10 k Ω 30 k Ω
+ Ι1

200
10 k Ω
kΩ

(9) (4) (10-18)


INH GND GND AES00665

Figure 3 Circuit Diagram

Semiconductor Group 6 1998-02-01


TLE 4205

Absolute Maximum Ratings


Tj = − 40 to 150 °C
Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VS – 0.3 45 V –
Differential input voltage VID – ± VS V ∆V6-5 or ∆V7-8
TLE 4205
∆V8-9 or ∆V10-11
TLE 4205 G
Output current IQ –1 1 A –
Supply current IS 2.5 3 A –
Ground current IGND –3 2.5 A I2
Input voltage VI – 15 VS V V5; V6; V7; V8
TLE 4205
V8; V9; V10; V11
TLE 4205 G
Inhibit input VInh – 15 VS V V9 TLE 4205
V12 TLE 4205G
Junction temperature Tj – 150 °C –
Storage temperature Tstg – 50 150 °C –

Operating Range
Supply voltage VS 6 32 V –
Case temperature TC – 40 105 °C PDmax = 3 W; DIP
Case temperature TC – 40 95 °C PDmax = 3 W; SO
Thermal resistance
junction - ambient Rth JA – 60 K/W TLE 4205
junction - case Rth JC – 15 K/W TLE 4205
Thermal resistance
junction - ambient Rth JA – 65 K/W TLE 4205 G
junction - case Rth JC – 20 K/W TLE 4205 G
Outputs pin 1 (19) and pin 3 (1) short-circuit proof to GND at VS ≤ 18 V for TLE 4205
(TLE 4205G)

Semiconductor Group 7 1998-02-01


TLE 4205

Characteristics
6 V < VS < 18 V; – 40 °C < Tj < 150 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

General
Open-circuit IS – 10 30 mA active, both outputs
current consumption high
Open-circuit IS – 10 100 µA inhibit
current consumption
Turn-ON dead time td ON – 10 20 µs |I1,3| < 1 A
ref. to V9 OFF/ON TLE 4205
|I1,19| < 1 A
TLE 4205 G
Turn-OFF dead time td OFF – 10 20 µs |I1,3| < 1 A
ref. to V9 OFF/ON TLE 4205
|I1,19| < 1 A
TLE 4205 G
Open-loop gain GVO 50 80 – dB f = 500 Hz

Inputs
Input zero voltage VIO – 7.5 – 7.5 mV RS = 10 kΩ;
Input-voltage drift ∆VIO/∆T – 20 30 µV/K –
Input zero current IIO – 75 – 75 mA –
Input current II – 300 – 300 nA –
Input-current drift ∆II/∆T – – 5 nA/K –
Input common-mode VIC – – VS – 2 V –
range, positive
Input common-mode VIC – – – 0.5 V –
range, negative
Power-supply PSSR – – 200 µV/V RS = 10 kΩ;
rejection ratio
Common-mode CMRR 70 80 – dB –
rejection ratio

Semiconductor Group 8 1998-02-01


TLE 4205

Characteristics (cont’d)
6 V < VS < 18 V; – 40 °C < Tj < 150 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Outputs
Saturation voltage VSat U – 1.35 1.5 V IQ = – 0.6 A
Saturation voltage VSat L – 0.8 1.2 V IQ = 0.6 A
Forward voltage of VFU – 1 1.5 V IF = 0.6 A
free-wheeling diode
Forward voltage of VFL – 1 1.5 V IF = 0.6 A;
free-wheeling diode
Slew rate of VQ dVqdtr – 0.5 – V/µs –

Inhibit Input
Switching threshold VIH 2 – – V –
high
Switching threshold VIL – – 0.8 V –
low
H-input current IIH – 100 – µA V9 = 5 V
L-input current IIH – 0 – µA V9 = 0 V

Note: VSat U = upper


VSat L = lower

Semiconductor Group 9 1998-02-01


TLE 4205

ΙS 1000 µF
470 nF
63 V
2
Ι Ι NH
9

Ι - Ι2 Ι Q1
5 1

VS Ι + Ι2
6 TLE 4205 RL
V9 Ι - Ι1 Ι Q2
8 3
V5
V6 Ι + Ι1 VQ1
7
V8 VQ2
V7
4, 10-18
Ι GND
AES00638

Figure 4 Test Circuit

13.5 V
2 *)
100 µF 100 nF
VΙ NH 9

V+ Ι1 7 + VQ1 220 nF 1Ω
1
8 Amp 1
V- Ι1 -

TLE 4205 M

V- Ι 2 5 - 220 nF 1Ω
3
V+ Ι 2 6 +Amp 2
VQ2

4, 10-18 AES00639

*) Value depends on load current and wiring inductivity

Figure 5 Application Circuit

Semiconductor Group 10 1998-02-01


TLE 4205

Forward Voltage of the Start Point of the SOA-


Free-Wheeling Diodes versus Protection Circuit versus
Junction Temperature Junction Temperature
IED00955
1.6 IED00956
2.4
V Ι F = 0.6 A
A
1.4
VF 2.0
I
VFU
1.2
VFL 1.6
1.0
V S = 13.5 V
0.8 1.2

0.6
0.8
0.4

0.4
0.2

0 0
-40 0 40 80 ˚C 120 -40 0 40 80 ˚C 120
TJ TJ

Saturation Voltage versus Current Consumption versus


Junction Temperature Junction Temperature
IED00957 IED00958
1.6 18
I Q = 600 mA
V mA
VS = 13.5 V 16
1.4
V Sat IS
VSat U
14
1.2 VS = 13.5 V
12
1.0
VSat L 10
0.8
8

0.6
6

0.4 4

0.2 2

0 0
-40 0 40 80 ˚C 120
-40 0 40 80 ˚C 120
TJ
TJ

Semiconductor Group 11 1998-02-01


TLE 4205

Package Outlines

P-DIP-18-3
(Plastic Dual In-line Package)
7.6 ±0.2

0.5 min

4.2 max
3.5 ±0.3
~ 1.2 0.25 +0.1
1.5 max 6.4 -0.2
0.25 18x
+0.1
2.54 0.45 7.6 +1.2
18 10

1 9
22.7 -0.2 0.4 max

Index Marking GPD05035

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 12 1998-02-01


TLE 4205

P-DSO-20-6
(Plastic Dual Small Outline Package)

0.35 x 45˚

2.65 max
2.45 -0.2
7.6 -0.2 1)

0.2 -0.1

+0.09

x
8˚ ma
0.23
1.27 0.4 +0.8
+0.15 2)
0.35
0.2 24x 0.1 10.3 ±0.3

20 11

GPS05094

1 12.8 1) 10
-0.2

Index Marking

1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 13 1998-02-01