Design of PLL for UBW applications using 180nm CMOS technology

Don Bosco Institute of Technology

Department of Electronics and Communication Engineering

SYNOPSIS
On
DESIGN OF PHASE LOCKED LOOP FOR ULTRA WIDE
BAND(UWB) FREQUENCY APPLICATIONS USING 180nm CMOS
TECHNOLOGY

Submitted by

AKASH P : 1DB16EC005
HARINI S : 1DB16EC045
SUMANTH P : 1DB16EC139
DHANUSH G BHAT : 1DB16EC037

Guided by : Mrs. RASHMI S B

Group Number : 31
Date of Submission : 23/08/2019

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Design of PLL for UBW applications using 180nm CMOS technology

Abstract
The phase-locked loop (PLL) is the most important technique for generation of radio
frequency and microwave signals. It allows the generation of variable output
frequency with the same stability of a crystal oscillator by means of feedback.
In earlier days, a local oscillator was tuned to the desired input frequency and
multiplied with the input signal. The resulting output signal included the original
modulation information. The intent was to develop an alternative receiver circuit that
required fewer tuned circuits. Since the local oscillator would rapidly drift in
frequency, an automatic correction signal was applied to the oscillator, maintaining it
in the same phase and frequency of the desired signal.
The undertaken project is about these aspects of PLL, its components, and their
applications.The detailed design and description is done using the Cadence
Tool:License 6.1.The general purpose directory kit used is 180nm technology.
Phase-locked loop (PLL) circuits exist in a wide variety of high frequency
applications, from simple clock clean-up circuits, to Local Oscillators (LO) for high
performance radio communication links, and ultra fast switching frequency
synthesizers in Vector Network Analyzers (VNA).

Introduction
In the last decade, the rapid growth of wireless applications has led to an increasing
demand of fully integrated, low-cost, low-power, and high-performance transceivers.
The applications of wireless communication devices include pagers, cordless phones,
Global Positioning Systems (GPS), and Wireless Local Area Network (WLAN).
These applications have evolved from analog to digital, from 1G (first generation) to
the existing 5G, such as GPRS an EDGE.
The recent boom in mobile communication market has driven worldwide electronic
and communication companies to produce small-size, low-power, high-performance
and certainly low-cost mobile terminals. Thus, circuit designers are always seeking
high integration communication devices in cheap CMOS technology.
Phase Locked Loop(PLL) is a control system used to perform different operations
related to wireless communication systems.The major concept behind the PLL
operation is comparison of the phases of two signals (generally input and output
signal phases are compared). Thus, the phase difference between the input and output

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Design of PLL for UBW applications using 180nm CMOS technology

signal can be used for controlling the loop frequency. Even though mathematical
analysis is very complicated, the operation of the PLL is very simple.
Within this context, a PLL tunable from 3 to 10GHz is designed and presented in
180nm technology, aiming to provide advantageous power, cost and performance at
its best.

Literature survey
It has been seen that every component of PLL researched has their own limitations
and the following survey states them.
 Phase Frequency Detector (PFD): There can be various methods of phase and
frequency detection. XOR gate based detection but it is less preferred
compared to the PFD where two signals are generated named UP and DOWN
with its pulse width proportional to the phase difference .This difference
indicates the PLL that whether the feedback signal lags or leads the reference
signal respectively. The reason behind rejecting use of XOR gate as detector
was that that it can lock onto harmonics of the reference signal and most
importantly it cannot detect a difference in frequency.
 Loop Filter: Despite their inherent stability, area-efficient loop filters, and
insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I
phase-locked loops (PLLs) are used infrequently because of two major
limitations-limited lock-range and large reference spurs.
 Charge Pump: The principle of multiplication is easily capable of extension,
and by adding more capacitors, any multiple of the supply voltage, Vdd , may
be obtained. However, in practice, the Cockcroft-Walton charge pump
becomes somewhat inefficient if implemented in monolithic integrated form
because of the relatively large on-chip stray capacitance. In addition, the
output impedance of the multiplier increases rapidly with the number of
multiplying stages.
 Voltage Controlled: Wireless Transceivers and many other electronic systems
uses Voltage Controlled Oscillator block widely. The noise performance of the
VCO determines the Reception Quality of the signals in any Wireless standard.
In Integrated circuits, the parasitic components are undesired but are

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Design of PLL for UBW applications using 180nm CMOS technology

unavailable. This parasitic effect may be overcome when they are taken into
account during the initial phase.
 Frequency Divider: This has become increasingly popular in RF applications
as it allows Phase Locked Loop (PLL) synthesizers to have a frequency
resolution finer than the reference frequency. However, there are two main
disadvantages in a fractional- divider, namely, fractional spurs generation and
frequency range limitation. Fractional spurs are generated due to the fixed
pattern of the dual-modulus divider and the frequency range of a fractional-
divider is equal to its reference frequency. This limits its usefulness especially
in wide-band applications.

Problem Formulation
PLLs are easier to design and implement, and are less sensitive to voltage noise than
analog PLLs, however they typically suffer from higher phase noise due to the
quantization error of using a non-analog oscillator. For this reason phase locked loops
are not well-suited to synthesizing higher frequencies or handling high frequency
reference signals.

Motivation
Phase locked loop (PLL) is the heart of the many modern electronics as well as
communication system. Recently plenty of researches have conducted research on the
design of phase locked loop (PLL) circuit and it is still going on.
PLL, being a mixed signal circuit, involves design challenge at high frequency. Since
its inspection in early 1930s, where it was used in the synchronization of the
horizontal and vertical scans of television, it has come to an advanced form of
integrated circuit (IC).
Today, it finds uses in many other applications.Recent advances in integrated circuit
design techniques have led to the development of high performance PLL which has
become more economical and reliable. Now a whole PLL circuit can be integrated as
a part of a larger circuit on a single chip.

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Design of PLL for UBW applications using 180nm CMOS technology

Methodology

A basic form of a PLL consists of four fundamental functional blocks namely:

1. Phase Frequency Detector (PFD)
2. Charge Pump (CP) and Loop filter (LF)
3. Voltage Controlled Oscillator (VCO)
4. Frequency Divider (FD)
The phase detector basically used to compare the phase of two signals. Here, the
phase detector compares phase (or frequency) of input signal and phase of VCO
signal. The phase detector compares a phase difference between two signals and
produces a difference voltage. The difference voltage depends on the phase difference
of the two inputs of phase detector. The difference voltage will passes through the
filter circuit.
The loop filter circuit is used to reduce the unwanted part of the signal. It is used to
improve the performance of the PLL. It attenuates high frequency noise of the
detector, increases the hold and capture ranges, and the switching speed of the loop in
lock. Then output of the filter is applied to the input of VCO as a Vcontrol. If output
frequency or phase is too slow, then charge pump sources current. Charge pump
sinks current if output frequency or phase is too high. It is useful in copying currents.
The voltage controlled oscillator produces the frequency that reduces the phase
difference of input signal and local oscillator. It is the most important functional unit
in the Phase Locked Loop. Its output frequency shows the effectiveness of PLL. For

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Design of PLL for UBW applications using 180nm CMOS technology

operating at highest frequency VCO unit consumes the most of the power in the
system.
The frequency divider divides the VCO output frequency that feed to input of PFD.
This is called dc lock signal which synchronizes with input signal.

Outcomes
The phase locked loop in this project is designed for 3 – 10 GHz for Ultra-Wide Band
(UBW) applications using 180nm technology. f simulated and the layouts for its
components will be obtained.

Applications
PLL (Phase lock loop) is used for digital communication, mobile applications for high
speed clock, in electronic devices such as hard disk drivers, in RF and wireless and
optical receivers.
It also used for jitter reduction, noise reduction & frequency tracking. When any
random binary signal is given to input that has been affected by jitter due to crosstalk
on chip, electronic noise due to components or devices, or due to parasitic
capacitance,a clock recovery circuit (CRC) at the input of signal is used.
Some other applications include:
 FM demodulation networks for FM operations
 It is used in motor speed controls and tracking filter.
 It is used in frequency shifting decodes for demodulation carrier
frequencies.
 It is used in time to digital converters.
 It is used for Jitter reduction, skew suppression, clock recovery.

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Design of PLL for UBW applications using 180nm CMOS technology

References
1. Usha Kumari , “Design and Implementation of Digital Phase Lock Loop: A
Review”, IJARECE , Volume 7, Issue 3, March 2018(ISSN: 2278 – 909X).
2. Guan-Chyun Hsich , “Phase-Locked Loop Techniques”, IEEE Transactions on
Industrial Electronics, 43(6):609 – 615, January 1997.
3. Anu Tonk , “A Comparative review and analysis of different phase frequency
detectors for Phase Locked Loops”, International Journal of Engineering
Research and General Science Volume 3, Issue 6, November-December 2015,
ISSN 2091-2730.
4. J Naga Raju , “CMOS Voltage Controlled Oscillator (VCO) Design with
Minimum Transistors”, IJRTI, Volume 1, Issue 3, December 2016, ISSN:
2456-3315.
5. Ahmad Sharkia ,, “A Compact, Voltage-Mode Type-I PLL With Gain-Boosted
Saturated PFD and Synchronous Peak Tracking Loop Filter, Volume: 66
Issue: 1, Jan. 2019, ( Print ISSN: 1549-8328,Electronic ISSN: 1558-0806).
6. Chirn Chye Boon , “Fully integrated CMOS fractional-N frequency divider for
wide-band mobile applications with spurs reduction”, IEEE Transactions on
Circuits and Systems—I: Rrgular Paper, Vol. 52, No. 6, June 2005.
7. Louie Pylarinos , “Charge Pumps: An Overview” , Semantic scholar
8. http://164.100.133.129:81/eCONTENT/Uploads/session_10_Case%20study%
20on%20PLL.pdf
9. https://www.elprocus.com/phase-locked-loop-operating-principle-and-applicat
ions/
10. http://digipllsak.blogspot.com/2010/03/disadvantage.html

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