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Introduction
What is feedback control?
Why do computer systems need feedback control?
Control design methodology
System modeling
Performance specs/metrics
Controller design
Summary
Control
Controlled System
Controller
control manipulated
control Actuator
input variable
function
error
sample controlled
+ - Monitor
variable
reference
Feedback (close-loop) Control
Measure variables and use it to compute control input
More complicated (so we need control theory)
Continuously measure & correct
Cruise-control car: measure speed & change engine force
Introduction
What is feedback control?
Why do todayʼ
todayʼs computer systems need feedback control?
Control design methodology
System modeling
Performance specs/metrics
Controller design
Summary
Control design methodology
Controller
Modeling Design
analytical Dynamic model Root-Locus Control algorithm
system IDs PI Control
Satisfy
Requirement
Performance Specifications
Analysis
System Models
Linear vs. non-linear (differential eqns)
Deterministic vs. Stochastic
Time-invariant vs. Time-varying
Are coefficients functions of time?
Continuous-time vs. Discrete-time
System ID vs. First Principle
Dynamic Model
Computer systems are dynamic
Current output depends on “history”
history”
Characterize relationships among system variables
• Differential equations (time domain)
•• • •
a2 y (t ) + a1 y (t ) + a0 y (t ) = b1 u (t ) + b0u (t )
• Transfer functions (frequency domain)
Y(s) = G(s)U(s)
b1s + b0 c1 c2
G (s) = = +
a2 s 2 + a1s + a0 s ! p1 s ! p2
• Block diagram (pictorial)
• Error: E(t)=Us-U(t)
t
Ra(t)
- Us
C?
U(t)
CPU
Rc(t)
A Diversion to Math
System representations
Three ways of system modeling
"
F ( s ) = L[ f (t )] = ! f (t )e # st
dt
0#
{pi} are poles of the function and decide the system behavior
A Diversion to Math
Time response vs. pole location
Stable Unstable
C ( s )Go ( s )
Gc =
R(s) Gc(s) Y(s) 1 + C ( s )Go ( s )
Y ( s ) = Gc ( s ) R ( s )
Back to
Our utilization control example
• Error: E(t)=Us-U(t)
t
Ra(t)
- Us
C?
U(t)
CPU
Rc(t)
Model
Transfer func. & block diag.
Rc(s)
Ra(s)
Us/s C(s) Go U(s)
Control design methodology
Controller
Modeling Design
analytical Dynamic model Root-Locus Control algorithm
system IDs PI Control
Satisfy
Requirement
Performance Specifications
Analysis
Design Goals
Performance Specifications
Stability
Transient response
Steady-state error
Robustness
Disturbance rejection
Sensitivity
Performance Specs: bounded input,bounded output stability
&im=1 ( s % zi ) C1 C2 Cn
Y ( s ) = G ( s )U ( s ) = K n = + + ... +
&i =1 ( s % pi ) s % p1 s % p2 s % pn
n
$ y (t ) = ' Ci e pi t
i =1
t #!
Note : Ci e pi t ""
"# ! if Re[ pi ] > 0
Performance Specs
Stability
Stable Unstable
Performance specifications
Controlled
variable
Overshoot
Steady state error
±ε%
Reference
Time
Settling time
Example: Control & Response in an Email Server (IBM)
Response
(queue length)
Good Bad
Control
(MaxUsers)
Slow Useless
Performance Specs
Steady-state error
lim f (t ) = lim sF ( s)
t !" s !0
Us
ess=-20%
Performance Specs
Robustness
Controller
Modeling Design
analytical Dynamic model Root-Locus Control algorithm
system IDs PID Control
Satisfy
Requirement
Performance Specifications
Analysis
Controller Design
PID control
Proportional-Integral-Derivative (PID) Control
E(s) X(s)
R(s) C(s) Go(s) Y(s)
-
Controller Design
CPU Utilization Control
Rc(s)
Ra(s)
Us/s C(s) Go U(s)
Proportional Control
Stability
Proportional Controller
ra(t)=
(t)=Ke(t
Ke(t);
); C(s) = K
Transfer functions
Us/s as input: G1(s) = K/(s+K)
Rc(s)
(s) as input: G2(s) = 1/(s+K)
Stability
Pole p0 = -K<0 ⇔ System is BIBO stable iff K>0
Note: System may shoot to 100% if K<0!
Rc(s)
Ra(s)
Us/s C(s) Go U(s)
Proportional Control
Steady-state error
Assume completion rate Rc(t) keeps constant for a time period longer than
the settling time: Rc(s)=Rc/s
System response is
U s G1 ( s ) Rc G2 ( s ) KU s ! Rc
U (s) = + =
s s s(s + K )
• Compute steady-state err using final value theorem,
KU s ! Rc Rc Rc
lim U (t ) = lim sU ( s ) = lim = Us ! " ess = ! <0
t #$ s #0 s #0 s+K K K
• P-control cannot achieve the desired CPU utilization Us; instead
it will end up lower by Rc/K Oops!
• The larger the proportional gain K is, the closer will CPU
utilization approach to Us
CPU Utilization
Proportional Control
U(t)
Us
ess=-20%
Proportional-Integral Control
Stability
Proportional Controller
ra(t)=K(e(t)+Ki•∫te(τ
(t)=K(e(t)+K e(τ)dτ
)dτ) C(s) = K(1+Ki/s)
Transfer functions
Us/s as input: G1(s) = (Ks+KKi)/(s2+Ks+KKi)
Rc(s)
(s) as input: G2(s) = s/(s2+Ks+KKi)
Stability
Poles Re[p0]<0, Re[p0]<0
⇔ System is BIBO stable iff K>0 & Ki>0
Rc(s)
Ra(s)
Us/s C(s) Go U(s)
Proportional Control
Steady-state error
Assume completion rate Rc(t) keeps constant for a time period longer than
the settling time: Rc(s)=Rc/s
System response is
U s G1 ( s ) Rc G2 ( s ) ( KU s + Rc ) s + KK iU s
U (s) = + =
s s s ( s 2 + Ks + KK i )
• Compute steady-state err using final value theorem,
( KU s + Rc ) s + KK iU s
lim U (t ) = lim sU ( s ) = lim 2 = Us ! ess = 0
t "# s "0 s "0 s + Ks + KK i
U(t)
Mp =
Us 0
ess=0
ts tr tp
Controller Design
Summary & pointers
"
Z[ f (k )] = F ( z ) = ! f (k ) z # k
k =0
Discrete Modeling
Difference equation
V(m) = a1V(m-1) + a2V(m-2) + b1U(m-1) + b2U(m-2)
z domain: V(z) = a1z-1V(z) + a2z-2V(z) + b1z-1U(z) + b2z-2U(z)
Im(s)
Higher-frequency
response
Longer settling time
Re(s)
Stable
Unstable |z|=1
Intuition : z = e Ts
Feedback control works in CS