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Device description

NXHX 90-JTAG
Development board

Hilscher Gesellschaft für Systemautomation mbH


www.hilscher.com
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Table of contents
1 Introduction ..............................................................................................................................  4
1.1 About this document ........................................................................................................ 4
1.1.1 Description of the contents ...............................................................................  4
1.1.2 List of revisions .................................................................................................  4
1.1.3 Conventions in this document...........................................................................  4
1.1.4 Reference to hardware .....................................................................................  4
1.2 Other relevant documentation.......................................................................................... 5
1.3 Legal notes....................................................................................................................... 6
2 Descriptions and drawings ...................................................................................................  10
2.1 Key features ................................................................................................................... 10
2.2 Overview ........................................................................................................................ 11
2.2.1 Block diagram .................................................................................................  11
2.2.2 Positions of interfaces and operating elements ..............................................  12
2.3 Operating elements........................................................................................................ 14
2.3.1 S400 – Slide switches for console mode and alternative boot mode..............  14
2.3.2 S401 – Reset push button ..............................................................................  16
2.3.3 S700 – Slide switches for user-defined inputs ................................................  16
2.3.4 S701 – Slide switches for selecting JTAG, UART, ADCs and user LEDs ......  16
2.4 Interfaces ....................................................................................................................... 17
2.4.1 X400 – JTAG connector..................................................................................  17
2.4.2 X500 – Ethernet connectors ...........................................................................  18
2.4.3 X600 – Host interface .....................................................................................  19
2.4.4 X601 – SPM host interface connector via SQI/SPI.........................................  26
2.4.5 X700 – ADC pin header ..................................................................................  27
2.4.6 X900 – Connector for NXHX fieldbus adapter modules..................................  28
2.4.7 X901 – Connector for NXHX-ENC, NXHX-IOL and standard MMIOs ............  29
2.4.8 X902 – Connector for NXHX-RS232 adapter module (UART) .......................  30
2.4.9 X1000 – Mini-B USB connector ......................................................................  31
2.4.10 X1001 – Measuring points (vias) for UART via FTDI......................................  31
2.4.11 X1200 – Connector for +24 V power supply ...................................................  32
2.5 LEDs .............................................................................................................................. 33
3 Accessories............................................................................................................................  35
3.1 Devices for host interface............................................................................................... 35
3.1.1 Overview .........................................................................................................  35
3.1.2 NXHX-SDRSPM: SDRAM and Serial Dual-Port Memory (via USB) at host
interface ..........................................................................................................  35
3.1.3 NXHX-FTDI: Serial Dual-Port Memory via USB device at host interface .......  38
3.1.4 NXPCA-PCI: Parallel Dual-Port Memory at host interface..............................  40
3.1.5 Accessory cables and connectors for host interface.......................................  41
3.2 Fieldbus interface adapter modules ............................................................................... 42
3.2.1 Overview .........................................................................................................  42
3.2.2 NXHX-DP........................................................................................................  43
3.2.3 NXHX-CO .......................................................................................................  43
3.2.4 NXHX-DN........................................................................................................  44
3.2.5 NXHX-CC........................................................................................................  44
3.3 NXHX-RS232 serial interface adapter ........................................................................... 45
3.4 NXHX-ENC module........................................................................................................ 46
3.5 NXHX-IOL module ......................................................................................................... 48

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3.6 NXAC-POWER voltage supply unit................................................................................ 51


4 Reference................................................................................................................................  52
4.1 Schematic diagrams....................................................................................................... 52
4.1.1 Schematics NXHX 90-JTAG ...........................................................................  52
4.1.2 Schematics of the accessory devices .............................................................  63
4.2 Bills of materials ............................................................................................................. 72
4.2.1 NXHX 90-JTAG...............................................................................................  72
4.2.2 NXHX-SDRSPM .............................................................................................  75
4.2.3 NXHX-FTDI.....................................................................................................  76
4.2.4 NXHX-ENC .....................................................................................................  77
4.3 Matrix label..................................................................................................................... 78
4.4 Technical data NXHX 90-JTAG ..................................................................................... 78
List of figures .........................................................................................................................  79
List of tables...........................................................................................................................  80
Contacts..................................................................................................................................  82

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1 Introduction

1.1 About this document

1.1.1 Description of the contents


This document describes the hardware of the NXHX 90-JTAG development
board.

1.1.2 List of revisions


Index Date Revision
1 2017-06-22 Document created
2 2018-11-15 Document revised according to hardware revision 3
Table 1: List of revisions

1.1.3 Conventions in this document


# means active low signal

Notes are marked as follows:

Important:
<Important note>

Note:
<Simple note>

<Note, where to find further information>

1.1.4 Reference to hardware


Hardware Revision Part number
NXHX 90-JTAG 3 7833.000
Table 2: Reference to hardware

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1.2 Other relevant documentation


Besides this device description, the following documents are also relevant
to the user of the NXHX 90-JTAG development board:
Title Contents Document ID
Getting started: netX Studio CDT – netX 90 Getting started guide for netX 90 SoC DOC170504GSxxEN
development development with netX Studio CDT (for
software developers)
netX 90 – Technical data reference guide Describes netX 90 chip functions DOC160609TRGxxEN
netX 90 – Design-In Guide Describes the standard circuitry around the DOC180501DGxxEN
netX interfaces (for hardware developers)
Table 3: Additional documentation

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1.3 Legal notes


Copyright
© Hilscher Gesellschaft für Systemautomation mbH
All rights reserved.
The images, photographs and texts in the accompanying materials (in the
form of a user's manual, operator's manual, Statement of Work document
and all other document types, support texts, documentation, etc.) are
protected by German and international copyright and by international trade
and protective provisions. Without the prior written consent, you do not
have permission to duplicate them either in full or in part using technical or
mechanical methods (print, photocopy or any other method), to edit them
using electronic systems or to transfer them. You are not permitted to make
changes to copyright notices, markings, trademarks or ownership
declarations. Illustrations are provided without taking the patent situation
into account. Any company names and product designations provided in
this document may be brands or trademarks by the corresponding owner
and may be protected under trademark, brand or patent law. Any form of
further use shall require the express consent from the relevant owner of the
rights.

Important notes
Utmost care was/is given in the preparation of the documentation at hand
consisting of a user's manual, operating manual and any other document
type and accompanying texts. However, errors cannot be ruled out.
Therefore, we cannot assume any guarantee or legal responsibility for
erroneous information or liability of any kind. You are hereby made aware
that descriptions found in the user's manual, the accompanying texts and
the documentation neither represent a guarantee nor any indication on
proper use as stipulated in the agreement or a promised attribute. It cannot
be ruled out that the user's manual, the accompanying texts and the
documentation do not completely match the described attributes, standards
or any other data for the delivered product. A warranty or guarantee with
respect to the correctness or accuracy of the information is not assumed.
We reserve the right to modify our products and the specifications for such
as well as the corresponding documentation in the form of a user's manual,
operating manual and/or any other document types and accompanying
texts at any time and without notice without being required to notify of said
modification. Changes shall be taken into account in future manuals and do
not represent an obligation of any kind, in particular there shall be no right
to have delivered documents revised. The manual delivered with the
product shall apply.
Under no circumstances shall Hilscher Gesellschaft für Systemautomation
mbH be liable for direct, indirect, ancillary or subsequent damage, or for
any loss of income, which may arise after use of the information contained
herein.

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Liability disclaimer
The hardware and/or software was created and tested by Hilscher
Gesellschaft für Systemautomation mbH with utmost care and is made
available as is. No warranty can be assumed for the performance or
flawlessness of the hardware and/or software under all application
conditions and scenarios and the work results achieved by the user when
using the hardware and/or software. Liability for any damage that may have
occurred as a result of using the hardware and/or software or the
corresponding documents shall be limited to an event involving willful intent
or a grossly negligent violation of a fundamental contractual obligation.
However, the right to assert damages due to a violation of a fundamental
contractual obligation shall be limited to contract-typical foreseeable
damage.
It is hereby expressly agreed upon in particular that any use or utilization of
the hardware and/or software in connection with
· Flight control systems in aviation and aerospace;
· Nuclear fusion processes in nuclear power plants;
· Medical devices used for life support and
· Vehicle control systems used in passenger transport
shall be excluded. Use of the hardware and/or software in any of the
following areas is strictly prohibited:
· For military purposes or in weaponry;
· For designing, engineering, maintaining or operating nuclear systems;
· In flight safety systems, aviation and flight telecommunications systems;
· In life-support systems;
· In systems in which any malfunction in the hardware and/or software
may result in physical injuries or fatalities.
You are hereby made aware that the hardware and/or software was not
created for use in hazardous environments, which require fail-safe control
mechanisms. Use of the hardware and/or software in this kind of
environment shall be at your own risk; any liability for damage or loss due
to impermissible use shall be excluded.

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Warranty
Hilscher Gesellschaft für Systemautomation mbH hereby guarantees that
the software shall run without errors in accordance with the requirements
listed in the specifications and that there were no defects on the date of
acceptance. The warranty period shall be 12 months commencing as of the
date of acceptance or purchase (with express declaration or implied, by
customer's conclusive behavior, e.g. putting into operation permanently).
The warranty obligation for equipment (hardware) we produce is 36
months, calculated as of the date of delivery ex works. The aforementioned
provisions shall not apply if longer warranty periods are mandatory by law
pursuant to Section 438 (1.2) BGB, Section 479 (1) BGB and Section 634a
(1) BGB [Bürgerliches Gesetzbuch; German Civil Code] If, despite of all
due care taken, the delivered product should have a defect, which already
existed at the time of the transfer of risk, it shall be at our discretion to
either repair the product or to deliver a replacement product, subject to
timely notification of defect.
The warranty obligation shall not apply if the notification of defect is not
asserted promptly, if the purchaser or third party has tampered with the
products, if the defect is the result of natural wear, was caused by
unfavorable operating conditions or is due to violations against our
operating regulations or against rules of good electrical engineering
practice, or if our request to return the defective object is not promptly
complied with.

Costs of support, maintenance, customization and product care


Please be advised that any subsequent improvement shall only be free of
charge if a defect is found. Any form of technical support, maintenance and
customization is not a warranty service, but instead shall be charged extra.

Additional guarantees
Although the hardware and software was developed and tested in-depth
with greatest care, Hilscher Gesellschaft für Systemautomation mbH shall
not assume any guarantee for the suitability thereof for any purpose that
was not confirmed in writing. No guarantee can be granted whereby the
hardware and software satisfies your requirements, or the use of the
hardware and/or software is uninterruptable or the hardware and/or
software is fault-free.
It cannot be guaranteed that patents and/or ownership privileges have not
been infringed upon or violated or that the products are free from third-party
influence. No additional guarantees or promises shall be made as to
whether the product is market current, free from deficiency in title, or can be
integrated or is usable for specific purposes, unless such guarantees or
promises are required under existing law and cannot be restricted.

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Confidentiality
The customer hereby expressly acknowledges that this document contains
trade secrets, information protected by copyright and other patent and
ownership privileges as well as any related rights of Hilscher Gesellschaft
für Systemautomation mbH. The customer agrees to treat as confidential all
of the information made available to customer by Hilscher Gesellschaft für
Systemautomation mbH and rights, which were disclosed by Hilscher
Gesellschaft für Systemautomation mbH and that were made accessible as
well as the terms and conditions of this agreement itself.
The parties hereby agree to one another that the information that each
party receives from the other party respectively is and shall remain the
intellectual property of said other party, unless provided for otherwise in a
contractual agreement.
The customer must not allow any third party to become knowledgeable of
this expertise and shall only provide knowledge thereof to authorized users
as appropriate and necessary. Companies associated with the customer
shall not be deemed third parties. The customer must obligate authorized
users to confidentiality. The customer should only use the confidential
information in connection with the performances specified in this
agreement.
The customer must not use this confidential information to his own
advantage or for his own purposes or rather to the advantage or for the
purpose of a third party, nor must it be used for commercial purposes and
this confidential information must only be used to the extent provided for in
this agreement or otherwise to the extent as expressly authorized by the
disclosing party in written form. The customer has the right, subject to the
obligation to confidentiality, to disclose the terms and conditions of this
agreement directly to his legal and financial consultants as would be
required for the customer's normal business operation.

Export provisions
The delivered product (including technical data) is subject to the legal
export and/or import laws as well as any associated regulations of various
countries, especially such laws applicable in Germany and in the United
States. The products / hardware / software must not be exported into such
countries for which export is prohibited under US American export control
laws and its supplementary provisions. You hereby agree to strictly follow
the regulations and to yourself be responsible for observing them. You are
hereby made aware that you may be required to obtain governmental
approval to export, reexport or import the product.

Terms and conditions


Please read the notes about additional legal aspects on our netIOT web
site under http://www.netiot.com/netiot/netiot-edge/terms-and-
conditions/.

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2 Descriptions and drawings

2.1 Key features


The NXHX 90-JTAG is a development board for the netX 90 SoC featuring:
· Host interface connector by use case:
– Companion chip with host interface: 8/16 bit parallel dual-port
memory, 2 x SPI/SQI as serial dual-port memory
– Stand-alone chip application: 16 bit SDRAM, MII for Ethernet PHY,
and custom-specific module solutions
· Additional host interface pin header connector for serial dual-port
memory (SPM0) via SPI/SQI
· JTAG MIPI-20 interface for debugging
· On-board JTAG-to-USB adapter (FTDI) for OpenOCD
· On-board UART-to-USB adapter (FTDI) for diagnosis/firmware
download
· USB Mini-B connector for JTAG-to-USB debugging and UART-to-USB
diagnosis/firmware download via FTDI
· 2-port RJ45 Ethernet interface with “Link” and “Activity” LEDs
· Interface for NXHX “legacy fieldbus” modules
(PROFIBUS, CANopen, DeviceNet and CC-Link)
· 4MB SQI Flash
· RS-232 serial interface
· Encoder interface with BiSS, SSI or EnDat connectivity
· Analog-to-digital converter (ADC) interface
· MMIO connectivity
· System status LED, power LED and two communication status LEDs
· Switches for configuring alternative boot option and console modes
· Four user output LEDs and four input dip switches
· Reset push button
· Power connector jack for +24 V

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2.2 Overview

2.2.1 Block diagram

Figure 1: NXHX 90-JTAG block diagram

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2.2.2 Positions of interfaces and operating elements

Figure 2: Positions on NXHX 90-JTAG

No. in Name Description For details see section


figure
(1) X900 Connector for NXHX fieldbus adapter modules X900 – Connector for NXHX fieldbus adapter
modules [} page 28]
(2) S400 Slide switches for selecting console mode and S400 – Slide switches for console mode and
alternative boot mode alternative boot mode [} page 14]
(3) X601 Serial Dual Port Memory (SPM) host interface X601 – SPM host interface connector via SQI/
connector for SQI/SPI SPI [} page 26]
(4) X1001 Measuring points (vias) for UART via FTDI X1001 – Measuring points (vias) for UART via
FTDI [} page 31]
(5) X902 Connector for NXHX-RS232 adapter module X902 – Connector for NXHX-RS232 adapter
module (UART) [} page 30]
(6) S701 Slide switches for: S701 – Slide switches for selecting JTAG, UART,
ADCs and user LEDs [} page 16]
· Configuring JTAG interface
(via 20 pin connector or USB jack)
· Configuring UART interface
(via NXHX-RS232 connector or USB jack)
· Enabling user LEDs or ADCs
(7) X901 Connector for NXHX-ENC module, NXHX-IOL X901 – Connector for NXHX-ENC, NXHX-IOL
(IO Link) module, MMIO and BiSS signals and standard MMIOs [} page 29]
(8) X700 ADC pin header X700 – ADC pin header [} page 27]
(9) X400 JTAG MIPI-20 connector X400 – JTAG connector [} page 17]
(10) X1000 Mini-B USB connector for debugging and X1000 – Mini-B USB connector [} page 31]
diagnosis via FTDI

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No. in Name Description For details see section


figure
(11) X1200 24 V DC power supply connector (jack for X1200 – Connector for +24 V power
barrel connector) supply [} page 32]
(12) PWR Power LED LEDs [} page 33]
(P1202)
(13) S700 Slide switches for user-defined input S700 – Slide switches for user-defined
inputs [} page 16]
(14) MMIO4 User definable LEDs (output) LEDs [} page 33]
(P700)
MMIO5
(P701)
MMIO6
(P702)
MMIO7
(P703)
(15) P101 AOI label –
(16) S401 Reset push button S401 – Reset push button [} page 16]
(17) COM1 COM1 LED (communication status) LEDs [} page 33]
(P501)
(18) COM0 COM0 LED (communication status)
(P500)
(19) X500 (B) RJ45 connector Ethernet channel 1 (CH1) X500 – Ethernet connectors [} page 18]
(20) X500 (A) RJ45 connector Ethernet channel 0 (CH0)
(21) SYS SYS LED (system status) LEDs [} page 33]
(P400)
(22) X600 Host interface connector X600 – Host interface [} page 19]
(23) X300 Reference voltage connector (via) for ADCs X700 – ADC pin header [} page 27]
(VREF_ADC)
(24) P102 Matrix label Matrix label [} page 78]
Table 4: Positions on printed circuit board

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2.3 Operating elements

2.3.1 S400 – Slide switches for console mode and alternative boot mode
For identifying the switches on the board, see position (2) in section
Positions of interfaces and operating elements [} page 12].

Standard boot mode


In standard boot mode, the ROM code searches for a valid firmware and
– if available – starts it. If the ROM code cannot find a valid “regular”
firmware, it tries to start a valid “maintenance” firmware instead. If neither
“regular” nor “maintenance” firmware is found, the ROM code automatically
enters console mode.
S400 settings for standard boot mode:
Switch 5 = OFF
Switch 6 = OFF

Console mode
The ROM code of the netX 90 features a console mode that enables the
handling of firmware programming depending on the selected console
mode interface, e.g. via UART, via Ethernet, etc. Thus you can download a
firmware file to the flash memory of the device, e.g. from your development
PC by using the “flasher tool” of netX Studio CDT.

Note:
The verification of the ROM code using the final silicon chip is not
yet completed. Therefore, initially, we recommend using the default
console mode by keeping switches 1, 2 and 3 of S400 in OFF
position. A full description of the console modes will be provided
after the verification.
Note also that downloading a firmware to the netX 90 is possible via
the JTAG interface. You can use the on-board JTAG-to-USB
connection, as described in the Getting started: netX Studio CDT –
netX 90 development, DOC170504GSxxEN, (in chapter How to ...
Use the Flasher tool).

S400 settings for console mode:


Switch 5 = ON
Switch 6 = OFF or ON

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Alternative boot mode


In alternative boot mode, the ROM code starts the “maintenance”
firmware instead of the “regular” firmware. The maintenance firmware is
capable of programming a new firmware (firmware update).
Potential use cases are:
· Firmware update procedures:
A new firmware received via web server or host interface is stored
either on-chip in INTFLASH1 or off-chip in an externally connected SQI
Flash. A software reset cycle initiated by a software command or a
hardware reset cycle (by S401 reset button or power-on) while switch 6
is at ON position starts a maintenance firmware, which programs the
new firmware.
· Multiple firmware versions:
The netX 90 has a maintenance firmware stored in INTFLASH1 and
holds multiple firmware versions for different Real-Time Ethernet
protocols in an externally connected SQI Flash. The maintenance
firmware programs the firmware selected by the system integrator, e.g.
via a rotary DIP-switch (or other ways).

Note:
The alternative boot mode is not yet supported because the
required “maintenance firmware“ is still under development.
Note also that if console mode and alternative boot mode are both
enabled (i.e. if switch 5 and 6 are both in ON position), the console
mode always has priority over the alternative boot mode.
If e.g. a power loss disrupts the programming of the new firmware,
the ROM code detects that the procedure is incomplete and re-
starts the maintenance firmware without prior selection.

S400 settings for alternative boot mode:


Switch 5 = OFF
Switch 6 = ON

Description of the S400 switches


S400 Switch Signal Position Connects to Function
1 SQI_SIO2 OFF Internal pull-up Reserved for future use (keep switches in
ON GND via 4.7 kΩ OFF position).
Note: In the final version of the netX 90
2 SQI_SIO1 OFF Internal pull-up ROM code, these switches will configure the
ON GND via 4.7 kΩ console mode.
3 SQI_SIO0 OFF Internal pull-up
ON GND via 4.7 kΩ
4 Not used - - -
5 RDY OFF Internal pull-up Disables console mode
ON GND via 1 kΩ Enables console mode
(currently only UART)
6 RUN OFF Internal pull-up Disables alternative boot mode
ON GND via 1 kΩ Enables alternative boot mode
(not yet supported)
Table 5: S400 for configuring console mode and alternative boot mode

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2.3.2 S401 – Reset push button


For identifying the button on the board, see position (16) in section
Positions of interfaces and operating elements [} page 12] .
S401 Signal Connects to Function
RST_IN# GND Resets the netX

Table 6: S401 – Reset button

2.3.3 S700 – Slide switches for user-defined inputs


For identifying the switches on the board, see position (13) in section
Positions of interfaces and operating elements [} page 12].
S700 Switch Signal Position Connects to
1 MMIO00/ENDAT0_IN/BISS0_SL OFF Internal pull-down
ON +3.3V via 1 kΩ
2 MMIO01/ENDAT0_OUT/BISS0_MO OFF Internal pull-down
ON +3.3V via 1 kΩ
3 MMIO02/ENDAT0_OE/BISS0_OE OFF Internal pull-down
ON +3.3V via 1 kΩ
4 MMIO03/ENDAT0_CLK/BISS0_MA OFF Internal pull-down
ON +3.3V via 1 kΩ
Table 7: S700 for user-defined inputs

2.3.4 S701 – Slide switches for selecting JTAG, UART, ADCs and user
LEDs
For identifying the switches on the board, see position (6) in section
Positions of interfaces and operating elements [} page 12]
S701 Switch Name Position Function
1 JTAG OFF Enable JTAG via FTDI (JTAG-to-USB: use Mini
USB connector for debugging)
ON Enable JTAG via JTAG connector (use JTAG
MIPI-20 connector for debugging)
2 UART OFF Enable UART via FTDI (UART-to-USB: use
Mini USB connector for diagnosis/firmware
download)
ON Enable UART via RS232 (use NXHX-RS232 at
X902 for diagnosis/firmware download)
3 Not connected
4 User OFF Enable ADCs (disables user LEDs)
LEDs ON Enable user LEDs (disables ADCs)
Table 8: S701 miscellaneous configuration

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2.4 Interfaces

2.4.1 X400 – JTAG connector


JTAG MIPI-20 connector X400. For identifying the connector on the board,
see position (9) in section Positions of interfaces and operating
elements [} page 12].

Note:
To enable this interface, put switch 1 of S701 into ON position (see
position (6) in section Positions of interfaces and operating
elements [} page 12]).

JTAG Pin Signal


MIPI-20-ARM ARM-20-SWD
ARM-20-JTAG
1 +3V3 3V3
2 TMS SWDIO
3 GND GND
4 TCLK SWDCLK
5 GND GND
6 TDO TRACE_CTL
7 Not connected Not connected
8 TDI Not connected
9 GND GND
10 RESET# RESET#
11 GND GND
12 Not connected TRACE_CLK
13 GND GND
14 MLED0 TRACE_DATA_0
15 GND GND
16 MLED1 TRACE_DATA_1
17 GND GND
18 MLED2 TRACE_DATA_2
19 GND GND
20 MLED3 TRACE_DATA_3
Table 9: Pin assignments MIPI-20 JTAG connector

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2.4.2 X500 – Ethernet connectors


Two RJ45 jack Ethernet connectors X500. For identifying the connectors on
the board, see position (20) for channel 0 and position (19) for channel 1 in
section Positions of interfaces and operating elements [} page 12].
Ethernet Pin Signal Description
1 TX+ Transmit data positive
2 TX– Transmit data negative
3 RX+ Receive data positive
4 Term 1 Connected and terminated to FE via RC
5 Term 1 combination*
6 RX– Receive data negative
7 Term 2 Connected and terminated to FE via RC
8 Term 2 combination*
* Bob Smith Termination
Table 10: Ethernet RJ45 pin assignment

For a description of the LEDs of the Ethernet connector, see section


LEDs [} page 33].

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2.4.3 X600 – Host interface


Host interface connector X600. For identifying the connector on the board,
see position (22) in section Positions of interfaces and operating
elements [} page 12].
The netX 90 offers many pin sharing options, which – for better overview –
are grouped into three tables:
· Host interface mode
– Parallel DPM
– Extension bus
– SDRAM
– Serial DPM
· MMIO and internal signals
– SQI
– I2C
– MPWM
– SPI
· Communication interfaces and digital I/O
– UART
– XC
– GPIO
– IO Link
– Ethernet
– PIO
– XM
– CAN
– MLED

Important:
The pinning of the X600 host interface was especially designed to fit
the different pinning layouts of the various host interface modules
offered by Hilscher, therefore some of the pins share the same
signals.
Connect at this interface only modules that are listed in section
Devices for host interface [} page 35].

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Signal options according to host interface mode


X600 Connector Pin Signal
layout X600 netX 90 Standard Signal options according to host interface mode
signal Parallel Extension SDRAM Serial
DPM bus DPM
1 – +3V3 – – – –
2 – GND – – – –
3 D5 HIF_A16 DPM_ALE EXT_A16 SD_CAS# –
4 F1 HIF_SDCLK DPM_SIRQ EXT_CS2# SD_CLK –
5 – GND – – – –
6 L3 RST_OUT# RST_OUT# – – –
7 M3 RST_IN# RST_IN# – – –
8 – n.c. – – – –
9 E8 MII1_COL – EXT_D2 SD_D2 –
10 E10 MII1_RXER – EXT_D0 SD_D0 –
11 F2 HIF_DIRQ# DPM_DIRQ EXT_CS1# – –
12 E3 HIF_RDY DPM_RDY EXT_RDY SD_CKE –
13 – GND – – – –
14 E2 HIF_RD# DPM_RD# EXT_RD# – –
15 – n.c. – – – –
16 E1 HIF_WR# DPM_WR# EXT_WR# SD_WE# –
17 E7 PHY0_LED_LI – EXT_D3 SD_D3 –
NK_IN
18 E9 MII1_CRS – EXT_D1 SD_D1 –
19 D7 HIF_BHE# HIF_BHE# EXT_BHE# SD_DQM1 –
20 – GND – – – –
21 – n.c. – – – –
22 – n.c. – – – –
23 – n.c. – – – –
24 D8 HIF_CS# DPM_CS# EXT_CS0# SD_CS# –
25 – GND – – – –
26 – n.c. – – – –
27 – n.c. – – – –
28 – n.c. – – – –
29 D6 HIF_A17 DPM_WRH# EXT_A17 SD_DQM0 –
30 E4 MII0_CRS – EXT_D7 SD_D7 –
31 E5 MII0_COL – EXT_D6 SD_D6 –
32 F5 MII0_TXEN – EXT_D5 SD_D5 –
33 – GND – – – –
34 D4 HIF_A15 DPM_A15 EXT_A15 SD_RAS# –
Table 11: Pin assignment of X600 according to HIF mode (1)

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X600 Connector Pin Signal


layout X600 netX 90 Standard Signal options according to host interface mode
signal Parallel Extension SDRAM Serial
DPM bus DPM
35 D3 HIF_A14 DPM_A14 EXT_A14 SD_BA1 –
36 D2 HIF_A13 DPM_A13 EXT_A13 SD_BA0 –
37 D1 HIF_A12 DPM_A12 EXT_A12 SD_A12 –
38 C1 HIF_A11 DPM_A11 EXT_A11 SD_A11 –
39 B2 HIF_A10 DPM_A10 EXT_A10 SD_A10 –
40 C2 HIF_A9 DPM_A9 EXT_A9 SD_A9 –
41 A3 HIF_A8 DPM_A8 EXT_A8 SD_A8 –
42 B3 HIF_A7 DPM_A7 EXT_A7 SD_A7 –
43 C3 HIF_A6 DPM_A6 EXT_A6 SD_A6 –
44 A4 HIF_A5 DPM_A5 EXT_A5 SD_A5 –
45 B4 HIF_A4 DPM_A4 EXT_A4 SD_A4 –
46 C4 HIF_A3 DPM_A3 EXT_A3 SD_A3 –
47 A5 HIF_A2 DPM_A2 EXT_A2 SD_A2 –
48 B5 HIF_A1 DPM_A1 EXT_A1 SD_A1 –
49 C5 HIF_A0 DPM_A0 EXT_A0 SD_A0 –
50 – GND – – – –
51 A6 HIF_D15 DPM_D15 – – DPM0_SQI_SIO3
52 B6 HIF_D14 DPM_D14 – – DPM0_SQI_SIO2
53 C6 HIF_D13 DPM_D13 – – DPM0_SPI_SIRQ
54 A7 HIF_D12 DPM_D12 – – DPM0_SPI_DIRQ
55 B7 HIF_D11 DPM_D11 – – DPM0_SPI_CLK
56 C7 HIF_D10 DPM_D10 – – DPM0_SPI_CS#
57 A8 HIF_D9 DPM_D9 – – DPM0_SPI_MOSI
58 B8 HIF_D8 DPM_D8 – – DPM0_SPI_MISO
59 C8 HIF_D7 DPM_D7 EXT_D15 SD_D15 DPM1_SQI_SIO3
60 A9 HIF_D6 DPM_D6 EXT_D14 SD_D14 DPM1_SQI_SIO2
61 B9 HIF_D5 DPM_D5 EXT_D13 SD_D13 DPM1_SPI_SIRQ
62 C9 HIF_D4 DPM_D4 EXT_D12 SD_D12 DPM1_SPI_DIRQ
63 A10 HIF_D3 DPM_D3 EXT_D11 SD_D11 DPM1_SPI_CLK
64 B10 HIF_D2 DPM_D2 EXT_D10 SD_D10 DPM1_SPI_CS#
65 C10 HIF_D1 DPM_D1 EXT_D9 SD_D9 DPM1_SPI_MOSI
66 B11 HIF_D0 DPM_D0 EXT_D8 SD_D8 DPM1_SPI_MISO
67 – +3V3 – – – –
68 E6 PHY1_LED_LIN – EXT_D4 SD_D4 –
K_IN
Table 12: Pin assignment of X600 according to HIF mode (2)

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Signal options of MMIOs and internal interfaces


Pin Signal options: MMIOs and internal interfaces
X600 netX 90 MMIO SQI (APP CPU) I2C MPWM SPI
1 – – – – – –
2 – – – – – –
3 D5 – – I2C_APP_SCL – –
4 F1 – – – – –
5 – – – – – –
6 L3 – – – MPWM5 –
7 M3 – – – – –
8 – – – – – –
9 E8 – – – – –
10 E10 – – – – –
11 F2 MMIO17 SQI1_APP_SIO3 – – –
12 E3 – – – – –
13 – – – – – –
14 E2 MMIO16 SQI1_APP_SIO2 – – –
15 – – – – – –
16 E1 – – – – –
17 E7 – – – – –
18 E9 – – – – –
19 D7 – – – – –
20 – – – – – –
21 – – – – – –
22 – – – – – –
23 – – – – – –
24 D8 – – – – –
25 – – – – – –
26 – – – – – –
27 – – – – – –
28 – – – – – –
29 D6 – – I2C_APP_SDA – –
30 E4 – – – – –
31 E5 – – – – –
32 F5 – – – – –
33 – – – – – –
34 D4 – – – – SPI0_APP_MISO
Table 13: Signal options of X600 pins – MMIO and internal interfaces (1)

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Pin Signal options: MMIOs and internal interfaces


X600 netX 90 MMIO SQI (APP CPU) I2C MPWM SPI
35 D3 – – – – SPI0_APP_MOSI
36 D2 – – – – SPI0_APP_CS0#
37 D1 – – – – SPI0_APP_CS1#
38 C1 – – – – SPI0_APP_CLK
39 B2 – – – – –
40 C2 – – – – –
41 A3 – – – – –
42 B3 – – – – –
43 C3 – – – – –
44 A4 – – – – –
45 B4 – – – – –
46 C4 – – – – –
47 A5 – – – – –
48 B5 – – – – –
49 C5 – – – – –
50 – – – – – –
51 A6 MMIO15 SQI1_APP_MOSI – – –
52 B6 MMIO14 SQI1_APP_MISO – – –
53 C6 MMIO13 SQI1_APP_CLK – – –
54 A7 MMIO12 SQI1_APP_CS0# – – –
55 B7 MMIO11 – – – –
56 C7 MMIO10 – – – –
57 A8 MMIO9 – – – –
58 B8 MMIO8 – – – –
59 C8 – – – – –
60 A9 – – – – –
61 B9 – SQI0_APP_SIO3 – – SPI2_APP_CS2#
62 C9 – SQI0_APP_SIO2 – – SPI2_APP_CS1#
63 A10 – SQI0_APP_CLK – – SPI2_APP_CLK
64 B10 – SQI0_APP_CS0# – – SPI2_APP_CS0#
65 C10 – SQI0_APP_MOSI – – SPI2_APP_MOSI
66 B11 – SQI0_APP_MISO – – SPI2_APP_MISO
67 – – – – – –
68 E6 – – – – –
Table 14: Signal options of X600 pins – MMIO and internal interfaces (2)

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Signal options of communication interfaces and digital I/O


Pin Signal options: Communication interfaces and digital I/O
X600 netX UART XC GPIO IO Link Ethernet PIO XM CAN MLED
90 (APP CPU)
1 – – – – – – – – – –
2 – – – – – – – – – –
3 D5 – – – – – – – – –
4 F1 UART_XPIC XC_TRI – – – – – – –
_APP_RTS# GGER0
5 – – – – – – – – – –
6 L3 – – – IO_LINK7_ – PIO_APP27 – – –
OUT
7 M3 – – – – – – – – –
8 – – – – – – – – – –
9 E8 – – – – – – XM1_I05 – –
10 E10 – – – – – – – – –
11 F2 UART_XPIC – – – – – – – –
_APP_CTS#
12 E3 UART_XPIC – – – ETH_RXCLK – – – –
_APP_RXD
13 – – – – – – – – – –
14 E2 UART_APP_ – – – ETH_MDC – – – –
RTS#
15 – – – – – – – – – –
16 E1 UART_APP_ – – – ETH_MDIO – – – –
CTS#
17 E7 – – – – – – – – –
18 E9 – – – – – – – – –
19 D7 UART_APP_ – – – ETH_RXER – – – –
RXD
20 – – – – – – – – – –
21 – – – – – – – – – –
22 – – – – – – – – – –
23 – – – – – – – – – –
24 D8 UART_APP_ – – – – – – – –
TXD
25 – – – – – – – – – –
26 – – – – – – – – – –
27 – – – – – – – – – –
28 – – – – – – – – – –
29 D6 – – – – – – – – –
30 E4 – – – – ETH_B_CRS – – – –
31 E5 – – – – ETH_B_COL – XM0_I05 – –
32 F5 – – – – ETH_B_TXEN – XM0_I04 – –
33 – – – – – – – – – –
34 D4 – – – – – – – – –
Table 15: Signal options of X600 pins – communication interfaces and digital I/O (1)

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Pin Signal options: Communication interfaces and digital I/O


X600 netX UART XC GPIO IO Link Ethernet PIO XM CAN MLED
90 (APP CPU)
35 D3 – – – – – – – – –
36 D2 – – – – ETH_TXCLK – – – –
37 D1 – – – – ETH_TXEN – – – –
38 C1 – – – – ETH_TXD3 – – – –
39 B2 – – GPIO7 – ETH_TXD2 – – – –
40 C2 – – GPIO6 – ETH_TXD1 – – – –
41 A3 – – GPIO5 – ETH_TXD0 – – – –
42 B3 – – GPIO4 IO_LINK1B ETH_RXDV – – – –
_WAKEUP
43 C3 – – GPIO3 IO_LINK1B ETH_RXD3 – – – –
_OE
44 A4 – – GPIO2 IO_LINK1B ETH_RXD2 – – – –
_OUT
45 B4 – – GPIO1 IO_LINK1B ETH_RXD1 – – – –
_IN
46 C4 – – GPIO0 IO_LINK0B ETH_RXD0 – – – –
_WAKEUP
47 A5 – – – IO_LINK0B ETH_CRS – – CAN0_AP –
_OE P_TX
48 B5 – – – IO_LINK0B ETH_COL – – CAN0_AP –
_OUT P_RX
49 C5 UART_XPIC – – IO_LINK0B ETH_TXER – – – –
_APP_TXD _IN
50 – – – – – – – – – –
51 A6 – – – IO_LINK7_ – – – – MLED1
WAKEUP 1
52 B6 – – – IO_LINK6_ – – – – MLED1
WAKEUP 0
53 C6 – – – IO_LINK5_ – – – – MLED9
WAKEUP
54 A7 – – – IO_LINK4_ – – – – MLED8
WAKEUP
55 B7 – – – IO_LINK3_ – – – – MLED7
WAKEUP
56 C7 – – – IO_LINK2_ – – – – MLED6
WAKEUP
57 A8 – – – – – – – – MLED5
58 B8 – – – – – – – – MLED4
59 C8 – – – – – PIO_APP7 – CAN1_AP –
P_TX
60 A9 – – – – – PIO_APP6 – CAN1_AP –
P_RX
Table 16: Signal options of X600 pins – communication interfaces and digital I/O (2)

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Pin Signal options: Communication interfaces and digital I/O


X600 netX UART XC GPIO IO Link Ethernet PIO XM CAN MLED
90 (APP CPU)
61 B9 – – – – – PIO_APP5 – – –
62 C9 – – – – – PIO_APP4 – – –
63 A10 – – – – – PIO_APP3 – – –
64 B10 – – – – – PIO_APP2 – – –
65 C10 – – – – – PIO_APP1 – – –
66 B11 – – – – – PIO_APP0 – – –
67 – – – – – – – – – –
68 E6 – – – – – – – – –
Table 17: Signal options of X600 pins – communication interfaces and digital I/O (3)

2.4.4 X601 – SPM host interface connector via SQI/SPI


Pin header X601 for connecting a host to the Serial Dual-Port Memory
(SPM) of the netX via SQI/SPI. For identifying the connector on the board,
see position (3) in section Positions of interfaces and operating
elements [} page 12].
X601 Pin Signal
SQI0 SPI0
1 SIRQ# SIRQ#
2 +3V3 +3V3
3 DIRQ# DIRQ#
4 GND GND
5 CLK CLK
6 GND GND
7 CS# CS#
8 GND GND
9 SIO0 MOSI
10 GND GND
11 SIO1 MISO
12 GND GND
13 SIO2 Not connected
14 GND GND
15 SIO3 Not connected
18 GND GND
Table 18: Pin assignments X601

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2.4.5 X700 – ADC pin header


Pin header X700 for using the internal ADC (analogue to digital converter)
of the netX. For identifying the connector on the board, see position (8) in
section Positions of interfaces and operating elements [} page 12].

Note:
To enable this interface, put switch 4 of S701 into OFF position (see
position (6) in section Positions of interfaces and operating
elements [} page 12]).

You can use jumpers or bridges to monitor on-board operating voltages or


connect analog input signals for measurements.
Note that the selection of the ADC reference voltage (internal or external) is
programmable by register, and can be optionally provided by the internal
reference buffer, which is 2.6 V or 3.3 V. Therefore, the analog inputs
referring to VDDIO_AD and 3V3_AD are equipped with a voltage divider for
2.4 V (see schematic diagram IO/ADC [} page 58]).
For rail-to-rail operations up to 3.3 V, the external reference voltage
VREF_ADC must be supplied at X300. For identifying the X300 via
connector on the board, see position (23) in section Positions of interfaces
and operating elements [} page 12].

Device destruction by exceeding the allowed reference voltage


The reference voltage must not exceed 3.3 V; otherwise the netX 90 will be
damaged!

X700 Pin Signal


1 MMIO04/ADC0-0
2 VDDIO_AD
3 MMIO05/ADC0-1
4 3V3_AD
5 MMIO06/ADC1-0
6 +1V2
7 MMIO07/ADC1-1
8 +1V2
9 GND
10 GND
Table 19: Pin assignments X700

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2.4.6 X900 – Connector for NXHX fieldbus adapter modules


Pin header connector X900 for NXHX fieldbus adapter modules. For
identifying the connector on the board, see position (1) in section Positions
of interfaces and operating elements [} page 12].
You can mount the following modules on this connector:
· NXHX‑DP for PROFIBUS (part number: 7923.410)
· NXHX‑CO for CAN open (part number: 7923.500)
· NXHX‑DN for DeviceNet (part number: 7923.510)
· NXHX‑CC for CC-Link (part number: 7923.740)

Note:
Each fieldbus module requires the appropriate fieldbus-specific
communication firmware on the netX.

X900 Pin Signal


1 XM0_TX
2 XM0_RX
3 XM0_IO0
4 XM0_IO1
5 GND
6 +3V3
7 Not connected
8 Not connected
9 Not connected
10 Not connected
Table 20: Pin Assignment X900

For the technical details of the fieldbus adapter modules, see section
Fieldbus interface adapter modules [} page 42].

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2.4.7 X901 – Connector for NXHX-ENC, NXHX-IOL and standard MMIOs


MMIO pin header connector X901 for the NXHX-ENC (part number
7924.000) and the NXHX-IOL module.
This connector can also be used as interface for standard MMIO, BiSS and
EnDat signals, and for connecting UART (NXHX-RS232 adapter module)
and CAN (NXHX-CO adapter module) peripherals to the application CPU of
the netX 90.
For identifying the connector on the board, see position (7) in section
Positions of interfaces and operating elements [} page 12].
X901 Pin Signal
No netX EnDat BiSS ADC NXHX-IOL NXHX-CO NXHX-
90 RS232
1 MMIO1 ENDAT0_OUT BISS0_MO – IN_C/Q0 CAN0_APP_TX UART_APP
CAN1_APP_TX _TXD
2 MMIO0 ENDAT0_IN BISS0_SL - OUT_C/Q1 CAN0_APP_RX UART_APP
CAN1_APP_RX _RXD
3 MMIO3 ENDAT0_CLK BISS0_MA – #EN_L+ – UART_APP
_RTS#
4 MMIO2 ENDAT0_OE BISS0_OE - ENC/Q0 - UART_APP
_CTS#
5 GND - - – GND GND GND
6 +3V3 - - - +3V3 +3V3 +3V3
7 MMIO5 - - ADC0-1 #IOLIRQ PIO4 PIO4
8 MMIO4 - - ADC0-0 OUT_I/Q PIO5 PIO5
or *
#RSTOUT
9 MMIO7 - - ADC1-1 I2C_SCL RSTOUT RSTOUT
10 MMIO6 - - ADC1-0 I2C_SDA - -
* To be configured by S1 switch on the NXHX-IOL module (see section NXHX-IOL
module [} page 48])
Table 21: Pin assignments X901

Note:
If you intend to use EnDat or BiSS signals, make sure to set all
switches of S700 to OFF position. For identifying S700 on the
board, see position (13) in section Positions of interfaces and
operating elements [} page 12].

· For technical details of the NXHX-ENC module, see section NXHX-ENC


module [} page 46].
· For technical details of the NXHX-IOL module, see section NXHX-IOL
module [} page 48].
· For technical details of the NXHX-RS232 module, see section NXHX-
RS232 serial interface adapter [} page 45].
· For technical details of the NXHX-CO module, see section NXHX-
CO [} page 43].

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2.4.8 X902 – Connector for NXHX-RS232 adapter module (UART)


Pin header connector X902 for the serial NXHX-RS232 adapter module
(part number 7923.010). For identifying the connector on the board, see
position (5) in section Positions of interfaces and operating
elements [} page 12].
To enable a UART connection to your development PC via the NXHX-
RS232 module mounted onto this interface, put switch 2 of S701 into ON
position (see section S701 – Slide switches for selecting JTAG, UART,
ADCs and user LEDs [} page 16]).
By using the UART console mode, you can e.g. download a firmware file to
the internal flash memory of the netX 90 SoC.
X902 Pin Signal
1 AIF_U0_TXD
2 AIF_U0_RXD
3 AIF_U0_RTS
4 AIF_U0_CTS
5 GND
6 +3V3
7 Not connected
8 Not connected
9 Not connected
10 Not connected
Table 22: Pin assignments X902

For the technical details of the NXHX-RS232 adapter module, see section
NXHX-RS232 serial interface adapter [} page 45].

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2.4.9 X1000 – Mini-B USB connector


The Mini-B USB connector X1000 is the FTDI JTAG-to-USB debug
interface. It can also be used as UART interface for diagnosis and firmware
download. For identifying the connector on the board, see position (10) in
section Positions of interfaces and operating elements [} page 12].

Note:
To enable the USB connector as JTAG interface, put switch 1 of
S701 into OFF position. To enable the USB connector as UART
interface, put switch 2 of S701 into OFF position (for location of
S701, see position (6) in section Positions of interfaces and
operating elements [} page 12]).

USB socket Pin Signal Description


1 VBUS +5V input
(to supply power for the protection circuit
and to detect “cable connected”)
2 D- Data -
3 D+ Data +
4 - Not connected
5 GND Ground
Shield Connected to GND via 1 MΩ and 10nF
Table 23: Pin assignments of Mini-B USB connector

2.4.10 X1001 – Measuring points (vias) for UART via FTDI


Measuring points for UART via FTDI. For identifying the vias on the board,
see position (4) in section Positions of interfaces and operating
elements [} page 12].
X1001 Via Signal
1 FTDI_U0_TXD
2 FTDI_U0_RXD
3 FTDI_U0_RTS
4 FTDI_U0_CTS

Table 24: Pin assignments X1001

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2.4.11 X1200 – Connector for +24 V power supply


Barrel connector jack X1200 for +24 V DC voltage supply. For identifying
the connector on the board, see position (11) in section Positions of
interfaces and operating elements [} page 12].
Socket Number Description
(1) 24 V ± 6 V DC
(2) GND Ground

Table 25: Pin assignment power supply socket

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2.5 LEDs
Overview
The NXHX 90-JTAG is equipped with the following LEDs:
Pos. in Name LED function Color Signal
device
drawing
(21) SYS System status (green) RUN
(P400)
(yellow) RDY

(12) PWR Power status (green) +3V3


(P1202)
(18) COM0 Communication status (green) MLED0/
(P500) (depending on TRACE_DATA_0
communication protocol)
(red) MLED0/
TRACE_DATA_0
(17) COM1 Communication status (green) MLED1/
(P501) (depending on TRACE_DATA_1
communication protocol)
(red) MLED1/
TRACE_DATA_1
(20) LINK LINK LED CH0 (Ethernet at (green) MLED2/
(X500-C) RJ45 jack) TRACE_DATA_2
(19) LINK LINK LED CH1 (Ethernet at (green) MLED3/
(X500-D) RJ45 jack) TRACE_DATA_3
(20) ACT Activity (RX/TX) LED CH0 (yellow) MLED2/
(X500-C) (Ethernet at RJ45 jack) TRACE_DATA_2
(19) ACT Activity (RX/TX) LED CH1 (yellow) MLED3/
(X500-D) (Ethernet at RJ45 jack) TRACE_DATA_3
(14) MMIO4 User definable LED (yellow) MMIO04/ADC0-0
(P700)
MMIO5 User definable LED (yellow) MMIO05/ADC0-1
(P701)
MMIO6 User definable LED (yellow) MMIO06/ADC1-0
(P702)
MMIO7 User definable LED (yellow) MMIO07/ADC1-1
(P703)
Table 26: LEDs on the NXHX 90-JTAG

Note:
The meaning of the COM0, COM1, LINK and ACTIVITY (RX/TX)
LEDs depend on the communication protocol that is used on the
NXHX 90-JTAG board. The meaning of the signaling of these LEDs
is therefore not described in this document.

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SYS LED
For identifying the LED on the board, see position (21) in section Positions
of interfaces and operating elements [} page 12].
The subsequent table describes the meaning of the system LED.

Note:
Additional LED signaling sequences will be implemented in future
revisions of the device.

LED Color State Meaning


SYS Duo LED yellow/green

(green) On Firmware is running

Blinking yellow No firmware found, device has automatically


(yellow) (on and off) entered console mode

Alternating Device has entered console mode after console


(yellow) between mode was selected at S400
darker and
brighter yellow

(off) Off Power supply is off


Table 27: System Status LED

User LEDs
The user LEDs MMIO4 (P700) ... MMIO7 (P703) [for identifying the LEDs
on the board, see position (14) in section Positions of interfaces and
operating elements [} page 12]] are intended for programming by the user
of the NXHX 90-JTAG board. The meaning of the signaling of these LEDs
is therefore not described in this document.

Note:
To enable the user defined LEDs, put switch 4 of S701 into ON
position (see position (6) in section Positions of interfaces and
operating elements [} page 12]).

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3 Accessories

3.1 Devices for host interface

3.1.1 Overview
This section describes the NXHX host interface devices that can be
connected to the X600 host interface connector of the NXHX 90-JTAG
board (for identifying the X600 connector on the board, see position (22) in
section Positions of interfaces and operating elements [} page 12]).

3.1.2 NXHX-SDRSPM: SDRAM and Serial Dual-Port Memory (via USB)


at host interface
NXHX-SDRSPM is a host interface module providing 64 Mbit SDRAM and
a SPM-to-USB FTDI bridge (SPM = Serial Dual-Port Memory).

Positions on printed circuit board

Figure 3: NXHX-SDRSPM

No Description
(1) AOI manufacturing label
(2) Matrix label
(3) Host interface, soldered side (connector is at bottom side)
(4) Mini-B USB Connector
Table 28: Positions in figure

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Technical data NXHX-SDRSPM device


Parameter Value
SDRAM 64 Mbit, 3.3V
Data width: 16 bit
Interface SPM-to-USB adapter (FTDI)
USB connector type Mini-B
Host interface connector 68 pin, female
(at bottom side)
Dimensions 65 x 30 mm
Order number 7703.080
Table 29: Technical data NXHX- SDRSPM device

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Pin assignments
Pinning of the host interface connector (see position (3) in figure above):
Pin Signal Pin Signal
1 +3V3 35 SD_BA1
2 GND 36 SD_BA0
3 SD_CAS# 37 SD_A12
4 SD_CLK 38 SD_A11
5 GND 39 SD_A10
6 - 40 SD_A9
7 RSTIN_HIF# 41 SD_A8
8 - 42 SD_A7
9 SD_D2 43 SD_A6
10 SD_D0 44 SD_A5
11 - 45 SD_A4
12 SD_CKE 46 SD_A3
13 GND 47 SD_A2
14 - 48 SD_A1
15 - 49 SD_A0
16 SD_WE# 50 GND
17 SD_D3 51 DPM0_SPI_SIO3
18 SD_D1 52 DPM0_SPI_SIO2
19 SD_DQM1 53 DPM0_SPI_SIRQ
20 GND 54 DPM0_SPI_DIRQ
21 - 55 DPM0_SPI_CLK
22 - 56 DPM0_SPI_CS#
23 - 57 DPM0_SPI_MOSI
24 SD_CS# 58 DPM0_SPI_MISO
25 GND 59 SD_D15
26 - 60 SD_D14
27 - 61 SD_D13
28 - 62 SD_D12
29 SD_DQM0 63 SD_D11
30 SD_D7 64 SD_D10
31 SD_D6 65 SD_D9
32 SD_D5 66 SD_D8
33 GND 67 +3.3 V
34 SD_RAS# 68 SD_D4
Table 30: Pinning host interface of NXHX-SDRSPI device

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Pinning of the Mini-B USB connector (see position (4) in figure above):
USB socket Pin Signal Description
1 VBUS +5V input
2 D- Data –
3 D+ Data +
4 - Not connected
5 GND Ground
Shield Connected to GND via 1 MΩ and 10nF
Table 31: Pinning of USB interface

3.1.3 NXHX-FTDI: Serial Dual-Port Memory via USB device at host


interface
NXHX-FTDI is a USB interface using an FTDI chip to connect the host
interface as serial Dual-Port Memory to a PC via USB.

Positions on the printed circuit board

Figure 4: NXHX-FTDI printed circuit board

No Name Description
(1) X100 Mini-B USB Connector
(2) X400 Host interface, soldered side (connector is at bottom
side)
(3) - AOI manufacturing label
(4) X101 Reserved serial interface
(5) - Matrix label (at bottom side)
Table 32: Positions in figure

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Technical data NXHX-FTDI device


Parameter Value
USB Mini-B
Host interface connector 68 pin, female
(at bottom side)
Dimensions 65 x 30 mm
Order number 7703.050
Table 33: Technical data NXHX-FTDI device

Pin assignments
Pinning of the X400 host interface (see position (2) in figure above):
Pin Signal Pin Signal
1 +3.3 V 35 -
2 GND 36 -
3 - 37 -
4 - 38 -
5 GND 39 -
6 - 40 -
7 RSTIN# 41 -
8 - 42 -
9 - 43 -
10 - 44 -
11 - 45 -
12 - 46 -
13 - 47 -
14 - 48 -
15 - 49 -
16 - 50 -
17 - 51 SPM_SIO3
18 - 52 SPM_SIO2
19 - 53 SPM_SIRQ#
20 - 54 SPM_DIRQ#
21 - 55 SPM_CLK
22 - 56 SPM_CS#
23 - 57 SPM_MOSI
24 - 58 SPM_MISO
25 - 59 -
26 - 60 -
27 - 61 -
28 - 62 -
29 - 63 -
30 - 64 -
31 - 65 -
32 - 66 -
33 - 67 +3.3 V
34 - 68 -
Table 34: Pinning host interface X400 of NXHX-FTDI device

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Pinning of the USB interface (see position (1) in figure above):


Pin Name Description
1 VBUS Not connected
2 D- Data –
3 D+ Data +
4 ID Not connected
5 GND Ground
Table 35: Pinning of USB interface

3.1.4 NXPCA-PCI: Parallel Dual-Port Memory at host interface


The NXHX 90-JTAG can be accessed from a PC via the NXPCA-PCI card
(part number 7902.100), using the X600 host interface as parallel dual-port
memory.

Figure 5: NXHX 90-JTAG connected to NXPCA-PCI Board

For further information about the NXPCA-PCI card, please refer to


the user manual NXPCA-PCI – Hardware description and
installation instructions, DOC080901UMxxEN.

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3.1.5 Accessory cables and connectors for host interface

3.1.5.1 CAB-NXPCA-PCI
The CAB-NXPCA-PCI cable can be used to connect the host interface
X600 of the NXHX 90-JTAG with the Hilscher NXPCA-PCI Card or other
host devices.
CAB-NXPCA-PCI Value
Part number 4400.000
Cable length 45 cm
Connectors 68 pin socket connector
Table 36: Technical data CAB-NXPCA-PCI

3.1.5.2 CAB-NXEB5
The CAB-NXEB5 cable can be used to connect the host interface X600 of
the NXHX 90-JTAG with the Hilscher NXPCA-PCI Card or other host
devices.
CAB-NXEB5 Value
Part number 4400.001
Cable length 6.35 cm
Connectors 68 pin socket connector
Table 37: Technical data CAB-NXEB5

3.1.5.3 CON-NXHIF/M
The CON-NXHIF/M male host interface socket can be used as connector
for PCB in hardware development.
CON-NXHIF/M Value
Part number 4400.003
Connector 68 pin male socket connector
Table 38: Technical data CON-NXHIF/M

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3.2 Fieldbus interface adapter modules

3.2.1 Overview
This section describes the NXHX fieldbus adapter modules that can be
mounted on the X900 fieldbus connector of the NXHX 90-JTAG board (for
identifying the X900 connector on the board, see position (1) in section
Positions of interfaces and operating elements [} page 12]).
The general layout of the fieldbus interface adapter modules is as follows:
Fieldbus adapter/interface with duo status LED (Ready/Error).

Figure 6: Fieldbus connector (dimensions in mm)

Pin Signal Pin Signal


1 XMAC TX 6 +3.3V
2 XMAC RX 7 PIO 4
3 XMAC IO 0 8 PIO 5
4 XMAC IO 1 9 RSTOUT
5 GND 10 n.c.
Table 39: Pins of connector to NXHX Fieldbus adapter

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3.2.2 NXHX-DP
NXHX-DP is a PROFIBUS interface (RS-485).
NXHX-DP Value
Interface PROFIBUS, RS-485
Connector D-Sub, 9 pin, female
Isolation Not isolated
Part number 7923.410
Table 40: NXHX-DP technical data
PROFIBUS Pin Signal Description
3 Rx/Tx + Receive- / Transmit data positive
5 GND Data ground
8 Rx/Tx ‑ Receive- / Transmit data negative
1, 2, 4, n.c. -
6, 7, 9

9 pin, D-Sub,
female
Table 41: PROFIBUS RS-485 pin assignment

3.2.3 NXHX-CO

Note:
The NXHX-CO module can also be mounted on connector X901
(see position (7) in section Positions of interfaces and operating
elements [} page 12]) in order to connect CAN peripherals to the
application CPU of the netX 90.

NXHX-CO is a CAN interface.


NXHX-CO Value
Interface CAN/CANopen
Connector D-Sub, 9 pin, male
Isolation Not isolated
Part number 7923.500
Table 42: NXHX-CO technical data
CANopen Pin Signal Description
2 CAN L CAN bus low
3 GND Ground
7 CAN H CAN bus high
1, 4, 5, n. c. -
6, 8, 9

9 pin, D-Sub,
male
Table 43: CANopen pin assignment

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3.2.4 NXHX-DN
NXHX-DN is a DeviceNet interface
NXHX-DN Value
Interface DeviceNet
Connector COMBICON MSTBA 2.5
Isolation Not isolated
Part number 7923.510
Table 44: NXHX-DN technical data
DeviceNet Pin Signal Description
1 DGND Ground
2 CAN L CAN Low signal
3 n. c. -
4 CAN H CAN High signal
5 DN V+ +24 V DeviceNet power supply

COMBICON
socket, female
Table 45: DeviceNet pin assignment

3.2.5 NXHX-CC
NXHX-CC is a CC-Link interface.
NXHX-CC Value
Interface CC-Link
Connector COMBICON MSTBA 2.5
Isolation Not isolated
Part number 7923.740
Table 46: NXHX-CC technical data
CC-Link Pin Signal Description
1 DA Data positive
2 DB Data negative
3 DG Data ground
4 SLD Shield, internally connected to FG and PE.
Internally connected via 3.3 nF to DG.
5 FG Field ground, internally connected to SLD and
PE. Internally connected via 3.3 nF to DG.

COMBICON
socket, female
Table 47: CC-Link pin assignment

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3.3 NXHX-RS232 serial interface adapter


This section describes the NXHX-RS232 adapter module that can be
mounted on the serial interface connector X902 of the NXHX 90-JTAG
board (for identifying the X902 connector on the board, see position (5) in
section Positions of interfaces and operating elements [} page 12]).

Note:
The NXHX-RS232 module can also be mounted on connector X901
(see position (7) in section Positions of interfaces and operating
elements [} page 12]) in order to connect UART peripherals to the
application CPU of the netX 90.

Technical data
NXHX-RS is a RS-232 interface.
NXHX-RS Value
Interface RS-232
Connector D-Sub, 9 pin, male
Isolation Not isolated
Part number 7923.010
Table 48: NXHX-RS technical data

Pin assignments
RS-232 Pin Signal Description
2 RxD Receive data
3 TxD Transmit data
4 DTR Data Terminal Ready
5 GND Reference potential
7 RTS Request to send
8 CTS Clear to send
9 pin, D-Sub, male
1, 6, 9 n. c. -
Table 49: RS-232 pin assignment D-Sub

Note:
To enable the NXHX-RS232 adapter module, put switch 2 of the
S701 switch on the NXHX 90-JTAG board into ON position (see
section S701 – Slide switches for selecting JTAG, UART, ADCs and
user LEDs [} page 16]).

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3.4 NXHX-ENC module


This section describes the NXHX-ENC encoder module (part number
7924.000) that can be mounted on the X901 connector of the NXHX 90-
JTAG board (for identifying the X901 connector on the board, see position
(7) in section Positions of interfaces and operating elements [} page 12]).

Positions on printed circuit board

Figure 7: NXHX-ENC printed circuit board

No Name Description
(1) X101 Interface to NXHX board (connector is on the
bottom side)
(2) - Matrix label
(3) X102 Single-ended connector for encoder
(4) X103 Differential connector for encoder
(5) - AOI manufacturing label
Table 50: Positions on NXHX-ENC

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Pin assignments
Pinning of X102 (single-ended connector):
Pin header X102 Pin Signal
1 RS485_RX_BUF
2 RS485_TX_BUF
3 RS485_CLK_BUF
4 RS485_TX_EN_BUF
5 5V
6 GND
Table 51: Pin assignments X102

Pinning of X103 (differential connector):


Pin header X103 Pin Signal
1 Data+
2 Data-
3 CLOCK+
4 CLOCK-
5 5V
6 GND
Table 52: Pin assignments X103

Note:
If you intend to use EnDat or BiSS signals, make sure to set all
switches of S700 to OFF position. For identifying S700 on the
board, see position (13) in section Positions of interfaces and
operating elements [} page 12].

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3.5 NXHX-IOL module


This section describes the NXHX-IOL module, which is an IO Link interface
adapter that can be mounted on the X901 connector of the NXHX 90-JTAG
board. For identifying the X901 connector on the board, see position (7) in
section Positions of interfaces and operating elements [} page 12].

Note:
The NXHX-IOL module requires a separate +24V power supply!

Positions on printed circuit board

Figure 8: NXHX-IOL

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No Name Description
(1) X1 Interface to NXHX board (connector is on the bottom side)
(2) X2 +24 supply voltage connector socket (Mini Combicon)
(3) S1 Slide switch for enabling reset by software from netX
(4) S2 Manual reset push button
(5) P1 2 x LEDs (yellow): reserved for port status and IO status indication.
P2
(6) X4 4 pole M8 female IO Link connector
Table 53: Positions on NXHX-IOL

Technical data
NXHX-IOL Value
Interface IO Link
IO Link Connector 4 pole M8 female connector
Supply voltage +24 V
Part number 7923.640
Table 54: NXHX-IOL technical data

Pin assignments
Pin assignments of IO Link connector:
M8 Pin Signal
1 L+
2 I/Q
3 GND
4 C/Q

Table 55: Pin assignment IO Link connector

Pin assignments of supply voltage:


Mini Combicon Pin Signal
1 GND
2 +24 V

Table 56: Pin assignment supply voltage

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Resetting the IO Link driver of the NXHX-IOL module


After each power cycle, the IO Link driver must be reset. You can reset the
driver either by pushing the S2 reset button [see position (4) in the device
drawing above] or by means of a “reset-by-software” from the netX via the
MMIO4 pin.
To enable a reset-by-software from the netX, you must set the S1 switch
[see position (3) in the device drawing] to the upper position:

Figure 9: Software reset enabled (OUT_I/Q signal disabled)

Thus, the MMIO4 pin of the netX is connected to the #RSTOUT signal of the
IO Link driver. Note that enabling the reset-by-software option disables the
OUT_I/Q signal of the driver, because the #RSTOUT signal and the
OUT_I/Q signal share the same MMIO4 pin.
To enable the OUT_I/Q signal of the driver (and thus disable the reset-by-
software option), you must set the S1 switch to the lower position:

Figure 10: OUT_I/Q signal enabled (Software reset disabled)

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3.6 NXAC-POWER voltage supply unit


Hilscher recommends using the NXAC-POWER supply unit (CINCON
TR15RA240) as voltage supply for the NXHX 90-JTAG board.
The unit is included in the delivery of the NXHX 90-JTAG board.
The power supply NXAC-POWER has the following technical data:
NXAC-POWER Value
Part number Hilscher: 7930.000
CINCON: TR15RA240
Input 100-240 V ~0.4 A (47-63 Hz)
Output 24 V / 0.625 A, short-circuit-proof
Cable length 1.8 m
Connector With barrel connector, sizes in mm

Sizes of barrel connector NXAC-POWER


Table 57: Technical data power supply NXAC-POWER

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4 Reference

4.1 Schematic diagrams

4.1.1 Schematics NXHX 90-JTAG


This section provides the schematics of the NXHX 90-JTAG board for the
following items:
· netX 90 CPU core
· Power supply of netX 90 on NXHX 90-JTAG board
· System
· Ethernet interface
· Host interface
· IO/ADC (user defined inputs, user defined LEDs, ADC)
· Switching matrix (switches for JTAG and UART)
· Extension modules (extension board interfaces on NXHX 90-JTAG
board
· FTDI
· +24V power supply

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1 2 3 4 5 6 7 8 9 10 11 12 13 14

+3V3
A +3V3 A
4.1.1.1
Reference

R206 R200 R201


10k ±1% 4.7K K300-A 4.7K

0201
0402
0402
J1 SYSTEM ETHERNET J12
RDY 4 RDY# PHY0_TX+ 5 PHY0_TXP
J2 J11
RUN 4 RUN# PHY0_TX- 5 PHY0_TXN
H12
PHY0_RX+ 5 PHY0_RXP
B M3 H11 B
NETX_RESET_IN# 4 RST_IN# PHY0_RX- 5 PHY0_RXN
L3
RSTOUT# 6 RST_OUT# /IO_LINK7_OUT/PIO_APP27/MPWM5
J3 E12
BOD# 11 BOD PHY1_TX+ 5 PHY1_TXP
E11
PHY1_TX- 5 PHY1_TXN
M9 F12
OSC_XTI 4 OSC_XTI PHY1_RX+ 5 PHY1_RXP
M10 F11
OSC_XTO 4 OSC_XTO PHY1_RX- 5 PHY1_RXN
L9
CLK25OUT /IO_LINK7_OE/PIO_APP28/MENC_MP1
G12
PHY_EXTRES
C G11 DEBUG C
U0_TXD 8 UART_TXD
G10
U0_RXD 8 UART_RXD LED L10
TRACE_DATA0/ MLED0 4,5 MLED0/TRACE_DATA_0
C11 K10
netX 90 CPU

JT_TDI/TRCCLK 8 JT_TDI /TRACECLK TRACE_DATA1/ MLED1 4,5 MLED1/TRACE_DATA_1

NXHX 90-JTAG | Device description


C12 J10
JT_TDO/TRCCTL 8 JT_TDO /TRACECTL TRACE_DATA2/ MLED2 4,5 MLED2/TRACE_DATA_2
D11 K11
JT_TMS/SWDIO 8 JT_TMS /SWDIO TRACE_DATA3/ MLED3 4,5 MLED3/TRACE_DATA_3
D12
JT_TCLK/SWCLK 8 JT_TCK /SWDCLK
D10 K7
JT_TRST# 8 JT_TRST SQI_CS1#/I2C0_COM_SCL/GPIO8/ADC3_IN2/ COM_IO0
K6
ETH_B_TXER/I2C0_COM_SDA/GPIO9/ADC3_IN3/ COM_IO1
K5
MII0_TXER/UART_RTS#/I2C1_COM_SCL/GPIO10/ADC3_IN6/ COM_IO2 8 U0_RTS#
K4
D H1 FLASH MII1_TXER1/UART_CTS#/I2C1_COM_SDA/GPIO11/ADC3_IN7/ COM_IO3 8 U0_CTS#
D
SQI_SIO0 4 SQI_MOSI /SQIROM_SIO0
G2
SQI_SIO1 4 SQI_MISO /SQIROM_SIO1
G3
SQI_SIO2 4
H3
SQI_SIO2 /SQIROM_SIO2 MII K8
SQI_SIO3 4 SQI_SIO3 /SQI_CS2#/SQIROM_SIO3 PIO_APP25/ETH_B_MDC/IO_LINK6_OE/ADC2_IN5/ MII_MDC
H2 L8
SQI_CLK 4 SQI_CLK /SQIROM_CLK PIO_APP26/ETH_B_MDIO/IO_LINK7_IN/ADC2_IN6/ MII_MDIO
G1
SQI_CS0# 4 SQI_CS0# /SQIROM_CS#
E5
SD_D6/EXT_D6/ETH_B_COL/XM0_IO5/ MII0_COL 6 SD_D06
E4
HIF SD_D7/EXT_D7/ETH_B_CRS/ MII0_CRS 6 SD_D07
6 F4
HIF_A00 C5 DPM PIO_APP8/ETH_B_RXCLK/FB0CLK/XM0_ECLK/FO0_SD/ MII0_RXCLK
J5
HIF_A0 /DPM_A0/IO_LINK0B_IN/UART_XPIC_APP_TXD/ETH_TXER/EXT_A0/SD_A0 ETH_B_RXD0/XM0_RX/FO0_RX/ MII0_RXD0 9 XM0_RX
HIF_A01 B5 J4
HIF_A1 /DPM_A1/IO_LINK0B_OUT/CAN0_APP_RX/ETH_COL/EXT_A1/SD_A1 PIO_APP9/ETH_B_RXD1/XM0_TX_ECLK/XM0_TX/FO0_TX/ MII0_RXD1 9 XM0_TX
E HIF_A02 A5 H5 E
HIF_A2 /DPM_A2/IO_LINK0B_OE/CAN0_APP_TX/ETH_CRS/EXT_A2/SD_A2 PIO_APP10/ETH_B_RXD2/XM0_IO0/FO0_EN/ MII0_RXD2 9 XM0_IO0
HIF_A03 C4 H4
HIF_A3 /DPM_A3/IO_LINK0B_WAKEUP/GPIO0/ETH_RXD0/EXT_A3/SD_A3 MENC0_A/ETH_B_RXD3/IO_LINK2_IN/ MII0_RXD3
HIF_A04 B4 G4
HIF_A4 /DPM_A4/IO_LINK1B_IN/GPIO1/ETH_RXD1/EXT_A4/SD_A4 MENC0_B/ETH_B_RXDV/IO_LINK3_IN/ MII0_RXDV
HIF_A05 A4 F3
HIF_A5 /DPM_A5/IO_LINK1B_OUT/GPIO2/ETH_RXD2/EXT_A5/SD_A5 MENC0_N/ETH_B_RXER/IO_LINK4_IN/ MII0_RXER
HIF_A06 C3 G5
HIF_A6 /DPM_A6/IO_LINK1B_OE/GPIO3/ETH_RXD3/EXT_A6/SD_A6 MPWM_BRAKE/PIO_APP11/ETH_B_TXCLK/IO_LINK2_OUT/ MII0_TXCLK
HIF_A07 B3 J7
HIF_A7 /DPM_A7/IO_LINK1B_WAKEUP/GPIO4/ETH_RXDV/EXT_A7/SD_A7 PIO_APP12/ETH_B_TXD0/XM0_TXOE_ECLK/XM0_TXOE/ADC2_IN7/ MII0_TXD0
HIF_A08 A3 J6
HIF_A8 /DPM_A8/GPIO5/ETH_TXD0/EXT_A8/SD_A8 PIO_APP13/ETH_B_TXD1/IO_LINK2_OE/XM0_IO1/ADC3_IN4/ MII0_TXD1 9 XM0_IO1
HIF_A09 C2 H7
HIF_A9 /DPM_A9/GPIO6/ETH_TXD1/EXT_A9/SD_A9 PIO_APP14/ETH_B_TXD2/IO_LINK3_OUT/XM0_IO2/ADC2_IN4/ MII0_TXD2
HIF_A10 B2 H6
HIF_A10 /DPM_A10/GPIO7/ETH_TXD2/EXT_A10/SD_A10 PIO_APP15/ETH_B_TXD3/IO_LINK3_OE/XM0_IO3/ADC3_IN5/ MII0_TXD3
HIF_A11 C1 F5
HIF_A11 /DPM_A11/SPI0_APP_CLK/ETH_TXD3/EXT_A11/SD_A11 SD_D5/EXT_D5/ETH_B_TXEN/XM0_IO4/ MII0_TXEN 6 SD_D05
HIF_A12 D1
HIF_A12 /DPM_A12/SPI0_APP_CS1#/ETH_TXEN/EXT_A12/SD_A12
F HIF_A13 D2 E7 F
HIF_A13 /DPM_A13/SPI0_APP_CS0#/ETH_TXCLK/EXT_A13/SD_BA0 SD_D3/EXT_D3/ PHY0_LED_LINK_IN 6 SD_D03
HIF_A14 D3
HIF_A14 /DPM_A14/SPI0_APP_MOSI/EXT_A14/SD_BA1
HIF_A15 D4 E8
HIF_A15 /DPM_A15/SPI0_APP_MISO/EXT_A15/SD_RAS# SD_D2/EXT_D2/XM1_IO5/ MII1_COL 6 SD_D02
SD_CAS# D5 E9
HIF_A16 /DPM_ALE/I2C_APP_SCL/EXT_A16/SD_CAS# SD_D1/EXT_D1/ MII1_CRS 6 SD_D01
SD_DQM0 D6 D9
HIF_A17 /DPM_WRH#/I2C_APP_SDA/EXT_A17/SD_DQM0 MPWM0/PIO_APP16/FB1CLK/XM1_ECLK/FO1_SD/ MII1_RXCLK
G9
MENC1_A/XM1_RX/FO1_RX/LVDS1_TX-/ MII1_RXD0

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


HIF_D00 B11 G8
HIF_D0 /DPM_D0/SQI0_APP_MISO/SPI2_APP_MISO/PIO_APP0/DPM1_SPI_MISO/EXT_D8/SD_D8 MENC_MP0/PIO_APP17/SQI0_APP_SIO2_B/XM1_TX_ECLK/XM1_TX/FO1_TX/LVDS1_TX+/ MII1_RXD1
HIF_D01 C10 F9
HIF_D1 /DPM_D1/SQI0_APP_MOSI/SPI2_APP_MOSI/PIO_APP1/DPM1_SPI_MOSI/EXT_D9/SD_D9 MENC1_N/PIO_APP18/SQI0_APP_SIO3_B/XM1_IO0/FO1_EN/LVDS1_RX+/ MII1_RXD2
HIF_D02 B10 F8
HIF_D2 /DPM_D2/SQI0_APP_CS0#/SPI2_APP_CS0#/PIO_APP2/DPM1_SPI_CS#/EXT_D10/SD_D10 MENC1_B/IO_LINK5_IN/LVDS1_RX-/ MII1_RXD3
HIF_D03 A10 F10
HIF_D3 /DPM_D3/SQI0_APP_CLK/SPI2_APP_CLK/PIO_APP3/DPM1_SPI_CLK/EXT_D11/SD_D11 MPWM_FAIL/IO_LINK6_IN/ MII1_RXDV

Figure 11: netX 90 CPU core schematic diagram


HIF_D04 C9 E10
HIF_D4 /DPM_D4/SQI0_APP_SIO2/SPI2_APP_CS1#/PIO_APP4/DPM1_SPI_DIRQ/EXT_D12/SD_D12 SD_D0/EXT_D0/ MII1_RXER 6 SD_D00
G HIF_D05 B9 H10
HIF_D5 /DPM_D5/SQI0_APP_SIO3/SPI2_APP_CS2#/PIO_APP5/DPM1_SPI_SIRQ/EXT_D13/SD_D13 PIO_APP19/IO_LINK4_OUT/ADC2_IN2/ MII1_TXCLK
HIF_D06 A9 J9 G
HIF_D6 /DPM_D6/CAN1_APP_RX/PIO_APP6/DPM1_SQI_SIO2/EXT_D14/SD_D14 MPWM1/PIO_APP20/SQI0_APP_CLK_B/XM1_TXOE_ECLK/XM1_TXOE/LVDS0_RX-/ MII1_TXD0
HIF_D07 C8 J8
HIF_D7 /DPM_D7/CAN1_APP_TX/PIO_APP7/DPM1_SQI_SIO3/EXT_D15/SD_D15 MPWM2/PIO_APP21/SQI0_APP_CS0#_B/IO_LINK4_OE/XM1_IO1/LVDS0_RX+/ MII1_TXD1
HIF_D08 B8 H9
HIF_D8 /DPM_D8/MLED4/MMIO8/DPM0_SPI_MISO MPWM3/PIO_APP22/SQI0_APP_MISO_B/IO_LINK5_OUT/XM1_IO2/LVDS0_TX-/ MII1_TXD2
HIF_D09 A8 H8
HIF_D9 /DPM_D9/MLED5/MMIO9/DPM0_SPI_MOSI MPWM4/PIO_APP23/SQI0_APP_MOSI_B/IO_LINK5_OE/XM1_IO3/LVDS0_TX+/ MII1_TXD3
HIF_D10 C7 K9
HIF_D10 /DPM_D10/MLED6/MMIO10/IO_LINK2_WAKEUP/DPM0_SPI_CS# PIO_APP24/IO_LINK6_OUT/XM1_IO4/ADC2_IN3/ MII1_TXEN
HIF_D11 B7
HIF_D11 /DPM_D11/MLED7/MMIO11/IO_LINK3_WAKEUP/DPM0_SPI_CLK
HIF_D12 A7 E6
HIF_D12 /DPM_D12/SQI1_APP_CS0#/MLED8/MMIO12/IO_LINK4_WAKEUP/DPM0_SPI_DIRQ SD_D4/EXT_D4/ PHY1_LED_LINK_IN 6 SD_D04
HIF_D13 C6
HIF_D13 /DPM_D13/SQI1_APP_CLK/MLED9/MMIO13/IO_LINK5_WAKEUP/DPM0_SPI_SIRQ
HIF_D14 B6
HIF_D14 /DPM_D14/SQI1_APP_MISO/MLED10/MMIO14/IO_LINK6_WAKEUP/DPM0_SQI_SIO2
HIF_D15 A6
HIF_D15 /DPM_D15/SQI1_APP_MOSI/MLED11/MMIO15/IO_LINK7_WAKEUP/DPM0_SQI_SIO3
H M7 H
BISS0_SL/ENDAT0_IN/IO_LINK0_IN/ADC2_IN0/ MMIO0 7,9 MMIO00/ENDAT0_IN/BISS0_SL
HIF_CS# D8 L7
HIF_CS# /DPM_CS#/UART_APP_TXD/EXT_CS0#/SD_CS# BISS0_MO/ENDAT0_OUT/IO_LINK0_OUT/ADC2_IN1/ MMIO1 7,9 MMIO01/ENDAT0_OUT/BISS0_MO
HIF_BHE# D7 M6
HIF_BHE# /DPM_BHE#/UART_APP_RXD/ETH_RXER/EXT_BHE#/SD_DQM1 ENDAT0_OE/IO_LINK0_OE/ADC3_IN0/ MMIO2 7,9 MMIO02/ENDAT0_OE/BISS0_OE
HIF_RD# E2 L6
HIF_RD# /DPM_RD#/SQI1_APP_SIO2/UART_APP_RTS#/MMIO16/ETH_MDC/EXT_RD# BISS0_MA/ENDAT0_CLK/IO_LINK0_WAKEUP/ADC3_IN1/ MMIO3 7,9 MMIO03/ENDAT0_CLK/BISS0_MA
HIF_WR# E1 M5
HIF_WR# /DPM_WR#/UART_APP_CTS#/ETH_MDIO/EXT_WR#/SD_WE# BISS1_SL/ENDAT1_IN/IO_LINK1_IN/ADC0_IN0/ MMIO4 7,9 MMIO04/ADC0-0
HIF_RDY E3 L5
HIF_RDY /DPM_RDY/UART_XPIC_APP_RXD/ETH_RXCLK/EXT_RDY/SD_CKE BISS1_MO/ENDAT1_OUT/IO_LINK1_OUT/ADC0_IN1/ MMIO5 7,9 MMIO05/ADC0-1
HIF_DIRQ# F2 M4
HIF_DIRQ /DPM_DIRQ/SQI1_APP_SIO3/UART_XPIC_APP_CTS#/MMIO17/EXT_CS1# ENDAT1_OE/IO_LINK1_OE/ADC1_IN0/ MMIO6 7,9 MMIO06/ADC1-0
HIF_SIRQ# F1 L4
HIF_SDCLK /DPM_SIRQ/UART_XPIC_APP_RTS#/XC_TRIGGER0/EXT_CS2#/SD_CLK BISS1_MA/ENDAT1_CLK/IO_LINK1_WAKEUP/ADC1_IN1/ MMIO7 7,9 MMIO07/ADC1-1

netx90 - 2270.000
I R205 I
R202 R203 6.49k ±1%
0201

10k ±1% 10k ±1%

0201
0201
changed!
must not be
This resistor

place near netX

GND GND GND

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netX90 power supply:


4.1.1.2
A A
Reference

INTPHY_VDDC INTPHY_VDDIO
+3V3 Iout current measurement
+3V3_NETX K300-B X300
L11 L2
PHY_VDDIO VREF_ADC
TP300 A2 C300
VDDIO1
A11 100nF X7R 0402
short circuit VDDIO2
B L1 B
VDDIO3 16 V
L12 M1
+1V2 VDDIO4 GND_ADC
K12
PHY_VDDC
GND
B1 +1V2
VDDC1
B12
VDDC2
M2
VDDC3
M11 M8
VDDC4 VDD_PLL
A1 C301
GND1
C A12 0402 100nF X7R C
GND2
F6
GND3 16 V
F7
GND4
G6 Iout current measurement
GND5

NXHX 90-JTAG | Device description


K3 +1V2
GND6 GND
G7
GND7 R300
M12
GND8 +1V2_OUT TP301
K2 K1
GND_DCDC DCDC_LX_OUT
10 µH short circuit
netx90 - 2270.000 0.6 A C302 C319
GND 74438323100
D 0805 10uF X7R 0805 10uF X7R D
+3V3_NETX
10 V 10 V
na
Power supply netX 90

GND GND
C303 C304 C305 C306 C307 C308
0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0805 10uF X7R 0805 10uF X7R
16 V 16 V 16 V 16 V 10 V 10 V

E E
GND

+1V2

C309 C310 C311 C312 C313 C314


F 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0805 10uF X7R 0805 10uF X7R F
netX90 PHY power supply filters 16 V 16 V 16 V 16 V 10 V 10 V

Würth
742 792 040 GND

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


INTPHY_VDDC +1V2

R301

C315 C316 Z=600 Ohm @100MHz


G 2000mA
0402 100nF X7R 0805 10uF X7R G
LEFS600RA2-0805

Figure 12: netX 90 power supply schematic diagram


16 V 10 V 0805

GND GND

Würth
INTPHY_VDDIO 742 792 040 +3V3_NETX

H R302 H

C317 C318 Z=600 Ohm @100MHz


2000mA
0402 100nF X7R 0805 10uF X7R
LEFS600RA2-0805
16 V 10 V 0805

GND GND

I I

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A A
4.1.1.3

Alternative boot mode P400 +3V3


JTAG connector +3V3 MIPI-20-ARM
Reference

ARM-20-SWD
X400 ARM-20-JTAG TRST (pin16) must not be used.
R400
RUN 3 1 1
RUN 2 0402 +3V3 +3V3 Using TRST can cause damage of debugger or netX.
green 8
270 CONNECTOR_JT_TDI/TRCCLK 8 TDI n.c.
6
0603 CONNECTOR_JT_TDO/TRCCTL 8 TDO TRACE_CTL
R401 2
CONNECTOR_JT_TMS/SWDIO 8 TMS SWDIO P407
RDY 4 2 4
RDY 2 0402 CONNECTOR_JT_TCK/SWCLK 8 TCLK SWDCLK
B yellow 10 B
270 CONNECTOR_JT_RESET# 8 RESET# RESET#
12
LEDSYG n.c. TRACE_CLK
14
MLED0/TRACE_DATA_0 2,5 MLED0 TRACE_DATA_0
16
MLED1/TRACE_DATA_1 2,5 MLED1 TRACE_DATA_1
18
Alternative boot mode MLED2/TRACE_DATA_2 2,5 MLED2 TRACE_DATA_2
20
This switch must be set to "ON" during boot MLED3/TRACE_DATA_3 2,5 MLED3 TRACE_DATA_3
3
S400-F phase to activate 'alternative boot mode'. GND GND
System

R402 5
GND GND
6 7 9
0402 GND GND
11
CHS-06 1k GND GND
13
P402 GND GND
C GND 15 C
GND GND
17
GND GND
19
GND GND
Console mode FTSH-110-01-L-DV-007-K

NXHX 90-JTAG | Device description


This switch must be set to "ON" during boot pin 7 removed
S400-E phase to activate 'console mode'. GND
R403
5 8
0402
CHS-06 1k reset
P401
GND
D NetX has an built-in pull-up, schmitt trigger, D
glitch filter and delay generator.

Not used P404


console mode description

(SIO2)
(SIO1)
(SIO0)

S0-A
S0-B
S0-C
Console mode options +3V3_NETX
S400-D 7 UART (default) open open open
R404 S400-A 4 9
6 UART open open close
1 12 R405
0201 CHS-06
E 4.7k ±1% CHS-06 5 UART open close open S401 10k ±1% E
0201
place near netX

R406 S400-B
4 UART open close close
2 11 1 3
0201 2 NETX_RESET_IN#
2 4
4.7k ±1% CHS-06 3 UART close open open C405 C400
S400-C TASTB3S-SMD 0402
R407 GND 1nF C0G 0402 1nF C0G
2 UART close open close
3 10
0201 50 V 50 V
4.7k ±1% CHS-06 1 UART close close open
GND 0 UART close close close GND GND

Figure 13: System schematic diagram


F R408 F
RSTIN_JTAG# 8 1 2
S0-A, S 0-B and 60-C are used for
MBR0520LT
changing 'console mode option'.
Currently only UART option is available, but in R409
future much more options will be available.

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


RSTIN_HIF# 6 1 2
P403 MBR0520LT
These diodes protect the reset generator
from damage if the reset signals are used
with push/pull outputs.
G Flash +3V3 G
C401 P405
ROM 32Mbit +3V3
R410
5 2
10k ±1% DI(IO0) DO(IO1)

0201
8

options
VCC System clock
6
CLK

console mode
1 CS# C402 G400
0402 100nF X7R 1 4
SQI_SIO0 2 OSC_XTI 2 GND1
H SQI_SIO1 2 7 HOLD#(IO3) 16 V H
3 4 R411 25 MHz
SQI_SIO2 2 WP#(IO2) GND
3 2
SQI_SIO3 2 OSC_XTO 2 0402 GND2
SQI_CLK 2 W25Q32VSSIG 0 C403 C404
SQI_CS0# 2 GND KX-6E-25MHz
10pF C0G 020110pF C0G 0201 GND
25V 25V

GND GND

I I

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A A
4.1.1.4
Reference

Vorwärtsspannung der Diode muss über den Temperaturbereich


betrachtet werden.

P508
B B

Ethernet transformers and jacks MLEDs


Power circuit for MLEDs
LED_VDD The LED power circuit is only needed once.
X500-C
C +3V3 C
R500
A12 A11
0402 ACT0
120 yellow 2 R502 P505

NXHX 90-JTAG | Device description


MLED2/TRACE_DATA_2 2,4 CH0
R501 BAS316
A9 A10 LED_VDD
0402 LINK0 R303 is required to decrease the maximal
1
270 green available forward voltage of both LEDs.
X500-A JX80-0037NL If the diode R303 is missing, LEDs could glow.
A1 1
Ethernet interface

PHY0_TXP 2 TX+ GND The diode R303 MUST NOT be a


A4
schottky diode.
D A2 2 R503 D
PHY0_TXN 2 TX- LED_VDD P504 Make sure R303 can handle maximum
A3 3 CH0 X500-D C500
PHY0_RXP 2 RX+ 1k current of all LEDs.

0603
A5 0402 100nF X7R
A6 6 R504
PHY0_RXN 2 RX- 16 V
75Ohm
4 B12 B11
0402 ACT1
75Ohm
5
120 yellow R305 is required to produce a permanent load for
C501 C502 75Ohm
7
MLED3/TRACE_DATA_3 2,4 CH1 R303 to specify minimal break-down voltage.
0402 100nF X7R 0402 100nF X7R A8 75Ohm
8 R505 GND
1nF B9 B10
16 V 16 V 2000V 0402 LINK1
JX80-0037NL 270 green
FE JX80-0037NL P506
E GND E
GND
X500-B LED_VDD C305 is required to guarantee that load jumps
B1 1 P500
PHY1_TXP 2 TX+ have no influence on the 'LED_VDD'.
B4
0603 The load jumps can be produced by blinking
B2 2 R506
PHY1_TXN 2 TX- LEDs.
B3 3 CH1 4 2
PHY1_RXP 2 RX+ 0402
B5 red
120 P507
B6 6
PHY1_RXN 2 RX- MLED0/TRACE_DATA_0 2,4 COM0
75Ohm
4 R507
75Ohm
5 1 3
0402
F C503 C504 75Ohm
7 green F
270
0402 100nF X7R 0402 100nF X7R B8 75Ohm
8
LEDSRG
1nF GND
16 V 16 V 2000V
JX80-0037NL
FE LED_VDD
C505 X500-E P501

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


0603 MLED 00-03
C1 R508
GND After power on, the internal resistors on pins

1808
C3 4 2
0402 MLED00-03 are deactivated.
1nF C2 red

Figure 14: Ethernet interface schematic diagram


120 Thus, no external resistors are needed.
250 VAC JX80-0037NL MLED1/TRACE_DATA_1 2,4 COM1 The software on the netX must deactivate
G R509 P502 these internal pull-up resistors.
0402 1 3 G
GND FE 270 green
LEDSRG MLED 04-11
GND After power on, the internal resistors (56k-116k)
on pins MLED04-11 are activated.
Use an external 4.7k pull-up and an external 4.7k
pull-down resistor for each signal to make sure
P503 that the LEDs are not glowing during start-up.
The software on the netX must deactivate
the internal pull-up resistors.
H H

I I

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Host interface (HIF)


4.1.1.5
A A
module article no. status
Reference

NXPCA-PCI 7902.100 supported

NXHX-FTDI 7703.050 supported +3V3


NXHX-SDRSPM 7703.080 supported

NXHX-IO 7703.010 not supported


B B
NXHX-SDR 7703.020 not supported

10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
10k ±1%
NXHX-PHY 7703.030 not supported

NXHX-SDRSPI 7703.070 not supported

0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
0201
+3V3

HIF 2
X600
+3V3 1

R600
R601
R602
R603
R604
R605
R606
R607
R608
R609
R610
R611
R612
R613
R614
R615
GND 2
C SD_CAS# SD_CAS# 3 C
HIF_SIRQ# HIF_SIRQ# 4
SPM GND 5
RSTOUT# 6
RSTOUT# 2

NXHX 90-JTAG | Device description


+3V3
Host interface

RSTIN_HIF# 7
SQI0 SPI0 RSTIN_HIF# 4
X601 8
1 2 R616 C600 SD_D02 SD_D02 9
SIRQ# SIRQ# HIF_D13 2,6 0402
3 4 1nF C0G SD_D00 SD_D00 10
DIRQ# DIRQ# HIF_D12 2,6 10k ±1%

0201
5 6 HIF_DIRQ# HIF_DIRQ# 11
CLK CLK HIF_D11 2,6 50 V
7 8 HIF_RDY HIF_RDY 12
CS# CS# HIF_D10 2,6
9 10 GND 13
SIO0 MOSI HIF_D09 2,6
D 11 12 HIF_RD# HIF_RD# 14 D
SIO1 MISO HIF_D08 2,6
13 14 GND GND 15
SIO2 n.c. HIF_D14 2,6
15 16 HIF_WR# HIF_WR# 16
SIO3 n.c. HIF_D15 2,6
SD_D03 SD_D03 17
XJLZ16SG
SD_D01 SD_D01 18
GND HIF_BHE# HIF_BHE# 19
GND 20
21
22
SSIO 23
HIF_CS# HIF_CS# 24
E GND 25 E
SSIO connector. Only for internal development
26
27
28
SD_DQM0 SD_DQM0 29
SD_D07 SD_D07 30
P600
SD_D06 SD_D06 31
SD_D05 SD_D05 32
+3V3 GND 33
HIF_A15 HIF_A15 34
X602 HIF_A14 HIF_A14 35
F 1 HIF_A13 HIF_A13 36 F
2 HIF_A12 HIF_A12 37
HIF_D08 2,6 SSIO_LO#
3 HIF_A11 HIF_A11 38
4 HIF_A10 HIF_A10 39
HIF_D14 2,6 SSIO_LI#
5 HIF_A09 HIF_A09 40
6 HIF_A08 HIF_A08 41
HIF_D15 2,6 SSIO_CLK#

Figure 15: Host interface schematic diagram

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


7 HIF_A07 HIF_A07 42
8 HIF_A06 HIF_A06 43
HIF_D09 2,6 SSIO_DO
9 HIF_A05 HIF_A05 44
10 HIF_A04 HIF_A04 45
HIF_D10 2,6 SSIO_DI
HIF_A03 HIF_A03 46
10FMN-SMT-A-TF
G HIF_A02 HIF_A02 47
normal type
na HIF_A01 HIF_A01 48 G
GND HIF_A00 HIF_A00 49
GND 50
HIF_D15 HIF_D15 51
HIF_D14 HIF_D14 52
HIF_D13 HIF_D13 53
HIF_D12 HIF_D12 54
HIF_D11 HIF_D11 55
HIF_D10 HIF_D10 56
HIF_D09 HIF_D09 57
H HIF_D08 HIF_D08 58 H
HIF_D07 HIF_D07 59
HIF_D06 HIF_D06 60
HIF_D05 HIF_D05 61
HIF_D04 HIF_D04 62
HIF_D03 HIF_D03 63
HIF_D02 HIF_D02 64
HIF_D01 HIF_D01 65
HIF_D00 HIF_D00 66
+3V3 67
SD_D04 SD_D04 68
I XSLP68SG-0.635 I

GND

Edited Name C. Marquardt © Copyright


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User defined inputs +3V3 User defined LEDs


A +3V3 A
4.1.1.6

description

S0-D
description 1 2 4
Reference

S700-A S700-B 3 S700-C 4 S700-D S701-D

S0
S0-C
DS-04 DS-04 DS-04 DS-04 CHS-04
open enable ADCs
open open enable ENC module (NXHX-ENC)
close enable user LEDs
open close enable buzzer
8 7 6 5 R704 5
close open enable inputs 0201
B R700 R701 R702 R703 10k ±1% B
close close do not use this setting 1k ±1% 1k ±1% 1k ±1% 1k ±1% K700-B P700

0201
0201
0201
0201
GND
R705
2 3 2 1
1A 1Y 0402
MMIO00/ENDAT0_IN/BISS0_SL 2,9 680
1
MMIO01/ENDAT0_OUT/BISS0_MO 2,9 1OE LEDSY-0603
IO/ADC

MMIO02/ENDAT0_OE/BISS0_OE 2,9 yellow


74LVC126T
MMIO03/ENDAT0_CLK/BISS0_MA 2,9
K700-C P701
C R706 C
5 6 2 1
2A 2Y 0402
680
4
2OE LEDSY-0603

NXHX 90-JTAG | Device description


74LVC126T yellow

K700-D P702
R707
9 8 2 1
3A 3Y 0402
680
D 10 D
3OE LEDSY-0603
74LVC126T yellow

K700-E P703
R708
12 11 2 1
4A 4Y 0402
680
13
4OE LEDSY-0603
yellow GND
74LVC126T
E E
+3V3

14 K700-A
VCC C700
POWER BOX 0402 100nF X7R
GND
16 V

Figure 16: IO/ADC schematic diagram


F 7 74LVC126T F

GND

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


G ADC G
The pins of ;00 can be bridged to use +1V2 +1V2 +3V3
ADC presets. +3V3
Alternatively ADCs can be supplied with
external signals.
Pay attention to setting of
P704 S0-D. R710
R709 1.3k
0603

X700 1.3k
0603

H 1 2 VDDIO_AD H
MMIO04/ADC0-0 2,9
3 4 3V3_AD
MMIO05/ADC0-1 2,9
5 6 +1V2 R712
MMIO06/ADC1-0 2,9
7 8 +1V2 R711
MMIO07/ADC1-1 2,9 3.3k ±1%
0603

9 10
3.3k ±1%
0603

XJLZ10SG
C701 C702 C703 C704
0402 10nF X7R 0402 10nF X7R
0402 10nF X7R 0402 10nF X7R
50 V 50 V 50 V 50 V
I X701 X702 X703 X704 I
GND GND GND GND GND GND GND GND

301.202.001.1 301.202.001.1 301.202.001.1 301.202.001.1


Jumper 2.54 mm Jumper 2.54 mm Jumper 2.54 mm Jumper 2.54 mm

Edited Name C. Marquardt © Copyright


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4.1.1.7
A A
Reference

JTAG switch +3V3

+3V3 1 S701-A description

S0-A
CHS-04
B K800 open enable JTAG over FTDI B
C800
0402 100nF X7R 16 15
VCC OE# close enable JTAG over JTAG connector
16 V GND 8 R800
8 L=B1 1
GND H=B2 S 0201
10k ±1%
GND GND
4 1B1
2
JT_TCLK/SWCLK 2 1A
10 FTDI_JTAG_TCK
1B2
3
JT_TDI/TRCCLK 2 10 FTDI_JTAG_TDI
7 2B1
5
JT_TDO/TRCCTL 2 2A
10 FTDI_JTAG_TDO
2B2
6
JT_TMS/SWDIO 2 10 FTDI_JTAG_TMS
C 9 3B1
11 C
JT_TRST# 2 3A
10 FTDI_JTAG_TRST#
3B2
10
RSTIN_JTAG# 4 10 FTDI_JTAG_SRST#
12 4B1
14
4A 13
4B2

NXHX 90-JTAG | Device description


C803
0402 1nF C0G +3V3 74CBTLV3257T
50 V
Switching matrix

C801 K801
GND 0402 100nF X7R 16 15
VCC OE#
D 16 V GND D
8 L=B1 1
GND H=B2 S
4 CONNECTOR_JT_TCK/SWCLK
GND 4 CONNECTOR_JT_TDI/TRCCLK
4 1B1
2
1A
4 CONNECTOR_JT_TDO/TRCCTL
1B2
3
4 CONNECTOR_JT_TMS/SWDIO
7 2B1
5
2A 6
2B2 4 CONNECTOR_JT_RESET#
9 3B1
11
3A 10
3B2
12 4B1
14
4A 13
E 4B2
E
74CBTLV3257T

UART switch
F +3V3 F
description

S0-B
+3V3 2 S701-B
open enable UART over FTDI
CHS-04

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


C802 K802 close enable UART over RS232 (NXHX-RS232)

Figure 17: Switching matrix schematic diagram


0402 100nF X7R 16 15
VCC OE#
16 V GND 7 R801
8 L=B1 1
GND H=B2 S 0201
G 10k ±1%
GND GND TX/RX and RTS/CTS are crossed for FTDI G
4 1B1
2
U0_RXD 2 1A
10 FTDI_U0_TXD connection.
1B2
3
U0_TXD 2 10 FTDI_U0_RXD
7 2B1
5
U0_CTS# 2 2A
10 FTDI_U0_RTS
2B2
6
U0_RTS# 2 10 FTDI_U0_CTS
9 3B1
11
3A 10 P800
3B2
12 4B1
14
4A 13
4B2 9 AIF_U0_RXD TX/RX and RTS/CTS must be crossed by null
9 AIF_U0_TXD modem cable.
H 74CBTLV3257T 9 AIF_U0_CTS H
9 AIF_U0_RTS

P801

I I

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A A
4.1.1.8
Reference

NXHX fieldbus modules


With this connector you can
B use the following modules: B
art. no. art. name

7923.410 NXHX-DP
XM0_IO0 2
XM0_TX 2 7923.500 NXHX-CO
XM0_RX 2
XM0_IO1 2 +3V3 7923.510 NXHX-DN
2 X900 1
7923.740 NXHX-CC
C 4 3 C
6 5
8 7
10 9

NXHX 90-JTAG | Device description


NXHX-AIF
Male Connector GND
Extension boards

D NXHX-ENC module D
With this connector you can
use the following module:

MMIO07/ADC1-1 2,7 art. no. art. name


MMIO05/ADC0-1 2,7
MMIO03/ENDAT0_CLK/BISS0_MA 2,7 7923.010 NXHX-RS232
MMIO01/ENDAT0_OUT/BISS0_MO 2,7
MMIO00/ENDAT0_IN/BISS0_SL 2,7 7923.500 NXHX-CO
MMIO02/ENDAT0_OE/BISS0_OE 2,7 +3V3
MMIO04/ADC0-0 2,7 7924.000 NXHX-ENC
MMIO06/ADC1-0 2,7 X901
E 2 1 E
4 3
6 5
8 7
10 9
NXHX-AIF
Male Connector
GND

F F

NXHX-RS232 module
With this connector you can

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


use the following module:

AIF_U0_RTS 8 art. no. art. name

Figure 18: Extension boards schematic diagram


AIF_U0_TXD 8
AIF_U0_RXD 8 7923.010 NXHX-RS232
G AIF_U0_CTS 8 +3V3
X902 G
2 1
4 3
6 5
8 7
10 9
NXHX-AIF
Male Connector GND

H H

I I

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FTDI: FTDI power supply filters

+1V8_FTDI
4.1.1.9
A A
+3V3 +3V3_FTDI_FILTERED +5V_USB
+5V_USB
Reference

R1000 X1000
R1001 1
VBUS
C1000 C1001 C1002 2
Z=600 Ohm @100MHz 0402 D-
0402 100nF X7R 0402 100nF X7R 0402 100nF X7R C1003 C1004 3
2000mA 10 ±1% D+
0805 10uF X7R 0402 100nF X7R 4
16 V 16 V 16 V LEFS600RA2-0805 ID
R1002 5
0805 10 V 16 V R1003 4 2 1 5 GND
6
0402 SHIELD1
B 7 B
10 ±1% SHIELD2

IO3
IO2
IO1
C1005 C1006 XUSBB5BW-MINI

VUSB
GND GND 0201 10pF C0G 0201 10pF C0G C1007
0402 100nF X7R
25V 25V C1014
+3V3 16 V R1005

GND
1210 10nF X7R
+3V3_FTDI_FILTERED2 1M
1206

+3V3 TPD3E001DRLR 3 1000 V


R1004
C1008 C1009 C1010 C1011 Z=600 Ohm @100MHz
C 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R
2000mA
C1012 C1013 GND GND GND GND GND GND C
0805 10uF X7R 0402 100nF X7R
16 V 16 V 16 V 16 V LEFS600RA2-0805
0805 10 V 16 V
FTDI to USB

NXHX 90-JTAG | Device description


GND GND

+3V3 +1V8_FTDI +3V3_FTDI_FILTERED2 +3V3_FTDI_FILTERED

D D
+3V3

56
42
31
20
64
37
12
9
4
K1000
16
FTDI_JTAG_TCK 8 ADBUS0
17 +3V3

VPLL
VPHY
FTDI_JTAG_TDI 8 ADBUS1 +1V8_FTDI
18

VCCIO4
VCCIO3
VCCIO2
VCCIO1
FTDI_JTAG_TDO 8 ADBUS2

VCORE3
VCORE2
VCORE1
19 +3V3
FTDI_JTAG_TMS 8 ADBUS3
21
FTDI_JTAG_TRST# 8 ADBUS4
E 22 50 E
FTDI_JTAG_SRST# 8 ADBUS5 VREGIN R808 is used to test the reset conditions with
23 R1008
ADBUS6 flying probe.
24 49 C1015 C1016 R1007
ADBUS7 VREGOUT 4.7
0402

R1006 0805 10uF X7R 0402 100nF X7R


1k

0402
26 6
ACBUS0 REF 0603 10 V 16 V Q1000
27
ACBUS1 12k ±1% P1000

place near netX


28 3
ACBUS2 >= 2.93V VCC
29 GND GND GND
ACBUS3
30 7 FTDI_INTERN_USB_DATA- 2 C1018
ACBUS4 DM RESET
32 8 FTDI_INTERN_USB_DATA+ 0402 100nF X7R
ACBUS5 DP
33 C1017
ACBUS6 16 V
F 34 0402 1nF C0G 1 F
X1001 ACBUS7 GND
50 V
1 38 14 FTDI_RESET#
FTDI_U0_TXD 8 BDBUS0 RESET# MIC803-30D2VM3
2 39
FTDI_U0_RXD 8 BDBUS1
3 40 GND GND

Figure 19: FTDI to USB schematic diagram


FTDI_U0_RTS 8 BDBUS2
4 41 63 FTDI_CS
FTDI_U0_CTS 8 BDBUS3 EECS

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


43 62 FTDI_CLK
BDBUS4 EECLK
44 61 FTDI_DATA
Male Connector BDBUS5 EEDATA

FT2232HQ
na 45
BDBUS6
46
+5V_USB BDBUS7 G1000 +3V3
2 +3V3
OSCI
G 48 1 4
BCBUS0 GND1
52 G
BCBUS1 12MHz
53
BCBUS2
R1009 54 3 2 R1010 R1011 R1012
BCBUS3 GND2
55 3
4.7K BCBUS4 OSCO 10k ±1% 10k ±1% 10k ±1%

0402
0201
0201
0201

57
BCBUS5 JXS32-12M
58 R1014
BCBUS6
FTDI_PWRSAV# 59 13 C1019 C1020
BCBUS7/PWRSAV# TEST 0402
0603 15pF 0603 15pF
2.2k
R1013 60 PWREN# 50 V 50 V
36 +3V3
10k ±1% SUSPEND#

GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND
AGND
C1021

0201
H H

5
1
FT2232HQ

51
47
35
25
15
11
65
10
3 4 +3V3
DI DO
6
ORG
8
VCC
1
CS C1022
2 CLK 0402 100nF X7R
GND GND GND GND GND
5 16 V
GND
I ST93C56 I
GND

Edited Name C. Marquardt © Copyright


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+24V filter
A A
4.1.1.10
Reference

Vfd = 0.8 V +24V_FILTERED


Imax = 0.7 A
B X1200 R1200 R1201 B
Iin ~ 0.35 A
+24V_IN 1 2 1
3
2.2µH
GND 2
TSSW3U45 0.7 A
LUM1613_13 74479775222A
0805

R1202
SM15T36CA
C1202
C 1210 2.2uF X7R C
100V

NXHX 90-JTAG | Device description


+24V Power supply

D D
GND

Brown-out detection (BOD)

R1205 must be assembled when netX is supplyed


with +3V3 over +5V USB.
For BOD testing, R1205 must be dissassembled
E and R1204 and R1207 must be assembled. E
P1201
Iin current measurement
+24V_FILTERED
+3V3_NETX

Uin=18-40V
TP1200
Iin_max=220mA short circuit
F R1203 40 V / 3,3 V R1204 R1205 F
5.1k 270k 10k ±1%

0402
0603
0402

na
enable at ~14V T1200
2 BOD#
21
3 PVIN1

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


R1206 22 R1207
PVIN2
23
PVIN3 56k ±1%
0603

8 24
VIN PVIN4 na Uout=3.3V ±3%
25
1 PVIN5 Iout_max=1000mA
BZX84C12LT1G 26

Zener
TP1202 3,1V-5,5V -> DCM/CCM Mode PVIN6 Iout_nom=500mA

Figure 20: +24V Power supply schematic diagram


G 2 27
EN/MODE PVIN7 Iout_min=85mA
28 GND G
PVIN8
34
ATTENTION 5V-PGOOD-SIGNAL PVIN_PAD Iout current measurement
5
3 TP1201 PGOOD +3V3
11
SW1 R1213
12

100V
R1209 SW2 TP1204
C1203 BZX84C4V7 9 13
VCC SW3
10k ±1% 14 4020

0402
1 R1208 SW4 short circuit
1210 na 32 22µH

Zener
SW_PAD
Tss=2,8ms 4 29 1A
SS SW(BST/ILIM)
20

2.2uF X7R
SW(NC) 74437324220 C1207 R1214
H C1206 R1212 0402 220pF
10k H
0402

3 0603 1uF
TON R1211 1.5k 50 V
0402

0 16 V

place as close as possible to XR76205 VIN


place only when PGOOD is needed R1210 30
BST 0402
1 I_lim=1A C1208 C1209 C1210
11k ±1% ILIM TP1203 2

0402
C1204 C1205 6 U_FB=0.6V 0805 4.7µF 0805 4.7µF 0805 4.7µF P1202
FB
4.7µF 0805 47nF X7R 0402 f(uin40V)=980kHz 16 V 16 V 16 V LEDSG-0603
f(uin32V)=990kHz 15
16 V 16 V PGND1 na green
f(uin24V)=1040kHz 16 R1215
PGND2 1
f(uin18V)=1090kHz 17
PGND3 2.2k
0402

7 18 R1216
AGND1 PGND4
I 10 19 I
AGND2 PGND5 680
0402

31 33
AGND-PAD PGND_PAD

XR76205
GND GND GND GND GND GND GND GND GND GND GND GND

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Reference 63/82

4.1.2 Schematics of the accessory devices


This section provides the schematics of the following accessory devices of
the NXHX 90-JTAG board:
· NXHX-SDRSPM
· NXHX-FTDI
· NXHX-ENC

NXHX 90-JTAG | Device description © Hilscher 2018


DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Host Interface
4.1.2.1
A A
Reference

+3V3

Pin description
of NXHX 90-JTAG
Pin function
of NXHX-SDRSPM
B B
X400
1
+3V3 +3V3
2
GND GND
3
SD_CAS# SD_CAS# [3] SD_CAS#
4
HIF_SIRQ# SD_CLK [3] SD_CLK
5
GND GND
6
RSTOUT# RSTOUT#
7
RSTIN_HIF# RSTIN_HIF# [4] RSTIN_HIF#
8
9
SD_D02 SD_D02 [3] SD_D02
C 10 C
SD_D00 SD_D00 [3] SD_D00
11
HIF_DIRQ# EXT_CS1#
12
HIF_RDY SD_CKE [3] SD_CKE
13
GND GND

NXHX 90-JTAG | Device description


14
HIF_RD# EXT_RD#
15
16
HIF_WR# SD_WE# [3] SD_WE#
17
NXHX-SDRSPM

SD_D03 SD_D03 [3] SD_D03


18
SD_D01 SD_D01 [3] SD_D01
19
HIF_BHE# SD_DQM1 [3] SD_DQM1
20
GND GND
D 21 D
22
23
24
HIF_CS# SD_CS# [3] SD_CS#
25
GND GND
26
27
28
29
SD_DQM0 SD_DQM0 [3] SD_DQM0
30
SD_D07 SD_D07 [3] SD_D07
31
SD_D06 SD_D06 [3] SD_D06
E 32 E
SD_D05 SD_D05 [3] SD_D05
33
GND GND
34
HIF_A15 SD_RAS# [3] SD_RAS#
35
HIF_A14 SD_BA1 [3] SD_BA1
36
HIF_A13 SD_BA0 [3] SD_BA0
37
HIF_A12 SD_A12 [3] SD_A12
38
HIF_A11 SD_A11 [3] SD_A11
39
HIF_A10 SD_A10 [3] SD_A10
40
HIF_A09 SD_A09 [3] SD_A09
41
HIF_A08 SD_A08 [3] SD_A08
42
HIF_A07 SD_A07 [3] SD_A07
F 43 F
HIF_A06 SD_A06 [3] SD_A06
44
HIF_A05 SD_A05 [3] SD_A05
45
HIF_A04 SD_A04 [3] SD_A04
46
HIF_A03 SD_A03 [3] SD_A03
47
HIF_A02 SD_A02 [3] SD_A02
48
HIF_A01 SD_A01 [3] SD_A01

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


49
HIF_A00 SD_A00 [3] SD_A00
50
GND GND
51
HIF_D15 DPM0_SQI_SIO3 [4] DPM0_SPI_SIO3
52
HIF_D14 DPM0_SQI_SIO2 [4] DPM0_SPI_SIO2
53
HIF_D13 DPM0_SPI_SIRQ [4] DPM0_SPI_SIRQ
G 54
HIF_D12 DPM0_SPI_DIRQ [4] DPM0_SPI_DIRQ
55 G
HIF_D11 DPM0_SPI_CLK [4] DPM0_SPI_CLK
56
HIF_D10 DPM0_SPI_CS# [4] DPM0_SPI_CS#
57
HIF_D09 DPM0_SPI_MOSI [4] DPM0_SPI_MOSI
58
HIF_D08 DPM0_SPI_MISO [4] DPM0_SPI_MISO
59
HIF_D07 SD_D15 [3] SD_D15
60
HIF_D06 SD_D14 [3] SD_D14
61

Figure 21: NXHX-SDRSPM connector schematic diagram


HIF_D05 SD_D13 [3] SD_D13
62
HIF_D04 SD_D12 [3] SD_D12
63
HIF_D03 SD_D11 [3] SD_D11
64
HIF_D02 SD_D10 [3] SD_D10
H 65 H
HIF_D01 SD_D09 [3] SD_D09
66
HIF_D00 SD_D08 [3] SD_D08
67
+3V3 +3V3
68
SD_D04 SD_D04 [3] SD_D04
XSLP68BG-0.635

GND

I I

Edited Name A. Lang © Copyright


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A A
Reference

B B

C C
C2
+3V3

NXHX 90-JTAG | Device description


H7 A9
SD_A00 [2] A0 VDD1
H8 E7
SD_A01 [2] A1 VDD2
J8 J9
SD_A02 [2] A2 VDD3
J7 C1 C3 C4 C9
SD_A03 [2] A3 0805
J3 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 10uF X7R
SD_A04 [2] A4
J2 A1
SD_A05 [2] A5 VSS1 16 V 16 V 16 V 10 V
D H3 E3 D
SD_A06 [2] A6 VSS2
H2 J1
SD_A07 [2] A7 VSS3
H1
SD_A08 [2] A8
G3 GND
SD_A09 [2] A9
H9 E2
SD_A10 [2] A10 NC1
G2 G1
SD_A11 [2] A11 NC2(A12) [2] SD_A12
+3V3

G7 B3
SD_BA0 [2] BA0 VDDQ1
G8 A7
SD_BA1 [2] BA1 VDDQ2
E C7 E
VDDQ3
E8 D3
SD_DQM0 [2] DQML VDDQ4
F1 C5 C6 C7 C8
SD_DQM1 [2] DQMH 0805
SD_CS# [2] G9 CS#
0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 10uF X7R
F8 A3
SD_RAS# [2] RAS# VSSQ1 16 V 16 V 16 V 10 V
F7 B7
SD_CAS# [2] CAS# VSSQ2
F9 C3
SD_WE# [2] WE# VSSQ3
F2 D7
SD_CLK [2] CLK VSSQ4
F3
SD_CKE [2] CKE
GND

F A8 F
A DQ0 [2] SD_D00
B9
DQ1 [2] SD_D01
B8
DQ2 [2] SD_D02
C9
DQ3 [2] SD_D03
C8
DQ4 [2] SD_D04
D9
DQ5 [2] SD_D05

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


D8
DQ6 [2] SD_D06
E9
DQ7 [2] SD_D07
E1
DQ8 [2] SD_D08
D2
DQ9 [2] SD_D09
D1
DQ10 [2] SD_D10
G C2
DQ11 [2] SD_D11
C1 G
DQ12 [2] SD_D12
B2
DQ13 [2] SD_D13
B1
DQ14 [2] SD_D14
A2
DQ15 [2] SD_D15

Figure 22: NXHX-SDRSPM SDRAM schematic diagram


SDRAM64M16-3V3A7B

H H

I I

Edited Name A. Lang © Copyright


J Date 07.08.2018 NXHX-SDRSPM J
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Checked Name C. Marquardt Systemautomation mbH Page 3
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FTDI: FTDI power supply filters

A +1V8_FTDI A
+3V3 +3V3_FTDI_FILTERED
Reference

R1016
C1011 C1012 C1013 Z=600 Ohm @100MHz
0402 100nF X7R 0402 100nF X7R 0402 100nF X7R
2000mA
C1020 C1021
0805 10uF X7R 0402 100nF X7R
16 V 16 V 16 V LEFS600RA2-0805
0805 10 V 16 V
B B
GND GND

+3V3

+3V3 +3V3_FTDI_FILTERED2

R1018
C1014 C1015 C1016 C1017 Z=600 Ohm @100MHz
C 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R 0402 100nF X7R C1024 C1025 +5V_USB C
2000mA +5V_USB
0805 10uF X7R 0402 100nF X7R
16 V 16 V 16 V 16 V LEFS600RA2-0805 X2
0805 10 V 16 V
1
VBUS

NXHX 90-JTAG | Device description


R800 10 ±1% USB_D- 2
0402 D-
R801 10 ±1% USB_D+ 3
0402 D+
GND GND 4
ID
5
R802 4 2 1 5 GND
6
SHIELD1
+3V3 +1V8_FTDI +3V3_FTDI_FILTERED2 +3V3_FTDI_FILTERED 7
SHIELD2
IO3
IO2
IO1
C800 C801 XUSBB5BW-MINI
VUSB

D 0402 10pF 0402 10pF C802 D


0402 100nF X7R
50 V 50 V C803
+3V3 16 V R803
GND

1210 10nF X7R


1M
1206

56
42
31
20
64
37
12
9
4
K800 TPD3E001DRLR 3 1000 V
16
ADBUS0
17

VPLL
VPHY
ADBUS1 +1V8_FTDI
18

VCCIO4
VCCIO3
VCCIO2
VCCIO1
ADBUS2

VCORE3
VCORE2
VCORE1
19 GND GND GND GND GND GND
ADBUS3
21
ADBUS4
E 22 50 E
ADBUS5 VREGIN
23 +3V3
ADBUS6
24 49 C804 C805
ADBUS7 VREGOUT
R806 0805 10uF X7R 0402 100nF X7R
R808 is used to test the reset conditions with
26 6
ACBUS0 REF 0603 10 V 16 V flying probe.
27
ACBUS1 12k ±1%
28 R808
ACBUS2
29 GND GND GND
ACBUS3 4.7
0402

30 7 FTDI_INTERN_USB_DATA-
ACBUS4 DM P800
32 8 FTDI_INTERN_USB_DATA+
ACBUS5 DP Q800
33
ACBUS6
F 34 3 F
ACBUS7 >= 2.93V VCC
38 14 FTDI_RESET# 2 C807
DPM0_SPI_CLK [2] BDBUS0 RESET# RESET
39 0402 100nF X7R
DPM0_SPI_MOSI [2] BDBUS1
40
DPM0_SPI_MISO [2] BDBUS2 16 V
41 63 FTDI_CS 1
DPM0_SPI_CS# [2] BDBUS3 EECS GND

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


43 62 FTDI_CLK
DPM0_SPI_SIO2 [2] BDBUS4 EECLK
44 61 FTDI_DATA
DPM0_SPI_SIO3 [2] BDBUS5 EEDATA MIC803-30D2VM3

FT2232HQ
45
BDBUS6
46 GND
+5V_USB BDBUS7 G800
2
OSCI +3V3
G 48 1 4 +3V3
RSTIN_HIF# [2] BCBUS0 GND1
52 G
DPM0_SPI_DIRQ [2] BCBUS1 12MHz
53
DPM0_SPI_SIRQ [2] BCBUS2

Figure 23: NXHX-SDRSPM FTDI schematic diagram


R809 54 3 2
BCBUS3 GND2
55 3 R812
4.7K BCBUS4 OSCO

0402
57
BCBUS5 JXS32-12M 10k ±1%
0402

58
BCBUS6
FTDI_PWRSAV# 59 13 C808 C809
BCBUS7/PWRSAV# TEST
0603 15pF 0603 15pF R810 R811 R813 0402 2.2k
R814 60 PWREN# 50 V 50 V 10k ±1% 10k ±1%
0402
0402

36 +3V3
10k ±1% SUSPEND#

GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND
AGND
C810

0402
H H

5
1
FT2232HQ

51
47
35
25
15
11
65
10
3 4 +3V3
DI DO
GND 6
ORG
8
VCC
1
CS C811
2 CLK 0402 100nF X7R
GND GND GND GND
5 16 V
GND
I ST93C56 I
GND

Edited Name A. Lang © Copyright


J Date 07.08.2018 NXHX-SDRSPM J
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+3V3
4.1.2.2
R100
1 2 +1V8 +1V8 +1V8
1206 1 1 [1] [1] [1]
A +3V3 +3V3 +3V3 +3V3 A
Reference

Z=600 Ohm @100MHz C107 0805


0805 10uF
C108
100nF
2 2
1 1 1 1 1 1 1
+3V3 C100 0805 C101 0805 C102 0805 C103 C104 0805 C105 0805 C106 Host Interface
GND GND 0805 100nF 100nF 100nF 100nF 0805 100nF 100nF 100nF
R101 2 2 2 2 2 2 2
1 2 X400
1206 1 1
+5V C110 GND GND GND GND GND GND GND 1
Z=600 Ohm @100MHz C109 0805 +1V8 [1] +3V3_NXHX
0805 10uF 100nF 2
B X100 [1] +3V3 3 B
2 2
1 GND 4
VBUS
2 1 5
R1022
D- 0603
3 GND GND 6
D+ 22
4 +3V3 GND 7
ID
5 8

4
9
12
37
64
20
31
42
56
GND K1 [1] GPIOH0/RST_IN
6 1 9
1
R1032 X10118
SHIELD1 0603
7 16 2 17 10
SHIELD2 22 +1V8 ADBUS0
17 3 16 GND 11

VPLL
VPHY
XUSBB5BW-MINI 6 4 R105 [1] ADBUS1
+3V3 18 4 15 12

VCCIO1
VCCIO2
VCCIO3
VCCIO4
ADBUS2

VCORE1
VCORE2
VCORE3
19 5 14 13
NXHX-FTDI

A B ADBUS3
C 21 6 13 P1 14 C
ADBUS4
1 GND 50 22 7 12 15
R1042 P2 1 P3 1
X1

NXHX 90-JTAG | Device description


2010 VREGIN ADBUS5 L11185ST2
23 8 11 REFERENCE-DOT 16
0 2 5 1 ADBUS6 L11185012
C111 49 24 9 10 XXXXXXXXX XXXXXXXXX 17
na na 1210
VREGOUT ADBUS7 L11185022
3.3uF AOI-LABEL AOI-LABEL 18
na L11185032

SN65220DBVT
1 6 26 LABEL-AOI LABEL-AOI 19
+3V3
R1062
GND 2 1206 REF ACBUS0 L11185042
GND 27 X2 20
12k ACBUS1 L11185SB2
28 REFERENCE-DOT 21
1 ACBUS2 L1118502
29 22

R114
GND GND ACBUS3
7 30 23
1.5k DM ACBUS4

0603
8 32 P5 P4 24
Q1 DP ACBUS5
33 25
XXXXX

D 2 ACBUS6 1 1 X3 D
>= 3.00V VCC 4 +3V3 1 0603 2 R115 ACBUS7
34 UL XXXX.XXX X REFERENCE-DOT 26
1 only for bom MATRIX LABEL 27
C115 1k LABEL-LABEL_UL_ENTFERNEN LABEL-MATRIX
Vcc
14 38 28
0603 100nF RESET# BDBUS0 TCK/SK [1]
39 29
BDBUS1 TDI/DO [1]
2 40 X6 X7 X4 30
BDBUS2 TDO/DI [1]

20k
S100 GND
1 63
EECS BDBUS3
41
TMS/CS [1]
NDK-Drill NDK-Drill REFERENCE-DOT 31
62 43 1 1 32
EECLK BDBUS4 GPIOL0/SIO2 [1]
1 2 3 2 61 44 33
MR# Open-Drain RESET# EEDATA BDBUS5 GPIOL1/SIO3 [1] DRILL-NDK-MT265 DRILL-NDK-MT265

FT2232HQ
45 34
FSMSM 1 BDBUS6 GPIOL2 [1]
46 35
na MIC6315-30D2UY BDBUS7 GPIOL3 [1]
E 0603 1nF 2 36 E
VOLTAGE-RESET-MIC6315-30D2UY OSCI
GND 48 X5 37
2 BCBUS0 GPIOH0/RST_IN [1]
52 DK-Drill 38
C116 BCBUS1 GPIOH1/SPM_DIRQ [1]
53 1 39
G100 BCBUS2 GPIOH2/SPM_SIRQ [1]
GND 54 40
1 2 BCBUS3 GPIOH3 [1] DRILL-DK-MTG265_300
3 55 41
12MHz
OSCO BCBUS4 GPIOH4 [1]
57 42
BCBUS5 GPIOH5 [1]
58 GND 43
JXG75P2-12M BCBUS6 GPIOH6 [1]
13 59 44
TEST BCBUS7 GPIOH7 [1]
45
1 1
C113 C114 60 +5V 46
PWREN# PWREN# [1]
F +3V3 +3V3 0603 27pF 0603 27pF 36 47 F
SUSPEND# SUSPEND# [1]

AGND
GND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1 48
R1102
2 2 0805 Test Punkte 49

1
5
FT2232HQ 4.7k

10
65
11
15
25
35
47
51
50
1 na
GND GND 1 51
R108 1 [1] TCK/SK [1] GPIOL1/SIO3

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


10k DRIVER-USB-UART-FT2232HQ R111 X500 [1] GPIOL0/SIO2
52

0805
1 53
10k [1] TDI/DO [1] GPIOH2/SPM_SIRQ

0805
C112 2 na
X501 [1] GPIOH1/SPM_DIRQ
54
GND 1 55
2 [1] TDO/DI X502 [1] TCK/SK
3 4 1 56
R1092
DI DO 0805 [1] TMS/CS
1 57
2.2k [1] TMS/CS X503 [1] TDI/DO
G 6 GND 58
ORG [1] TDO/DI
8 1 59 G
VCC [1] GPIOL0/SIO2 X504
1 60
CS
2 1 61
CLK [1] GPIOL1/SIO3 X505
Alternative Spannungsversorgung 62

Figure 24: NXHX-FTDI Schematic Diagram (P1118501)


7 5 1 63
NC GND [1] GPIOL2 X506
+5V +3V3 64
1 65
ST93C56 [1] GPIOL3 X507
GND 66
EEPROM T200 [1] GPIOH0/RST_IN
1
[1] +3V3_NXHX
67
1
VIN1 VOUT1
5 X508 68
H 2 6 +3V3 1 H
VIN2 VOUT2 [1] GPIOH1/SPM_DIRQ X509 XSLP68BG-0.635
7
VOUT3
20 1 1
R3002
1 ENABLE [1] +3V3_NXHX 0805 [1] GPIOH2/SPM_SIRQ X510
C200 19 15
VS0 VSENSE 0
10uF 0805 18 16 1
VS1 VFB na [1] GPIOH3 X511
17
na 2 VS2
3 Verbindung zwischen Pads von R300 muss 1
GND1 1 [1] GPIOH4 X512
21 4 C201
AGND GND2
0805 10uF durchtrennt werden, wenn durch USB 1
[1] GPIOH5 X513
EN5312Q 2 na
gepowert werden soll. 1
na [1] GPIOH6 X514
I STEPDOWN-EN5312Q I
1
[1] GPIOH7 X515
1
[1] PWREN# X516
GND GND 1
[1] SUSPEND# X517

Edited Name B. Dollak © Copyright


J Date 14.03.14 L1118502 CONFIDENTIAL J
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P101
A P102 L17010ST1 A
4.1.2.3
L17010011
L17010031
XXXXXXXXX
L17010041
Reference

AOI-Label
L17010021
L17010SB1
NXHX-ENC L1701001

P103
B X105 B
REFERENCE-DOT
XXXXXXXXX

AOI-Label

+3V3

P104 X106
REFERENCE-DOT
XXXXX

C XXXX.XXX X
C
NXHX-ENC

mini SN-Label
POWER-SUPPLY
5V @ max. 500mA (NO SHORTCIRCUIT PROTECTION)

NXHX 90-JTAG | Device description


+3V3 5V

1
SHEET-4 F101
RXES200MV30-1210
D D

5
3
1
X102
E MALE-CONNECTOR-XJLZ6SG E

6
4
2
BUS-DRIVER RS485-DRIVER
5
3
1

RS485_RX RS485_RX_BUF RS485_RX_BUF DATA+


1 2
3 4
RS485_TX RS485_TX_BUF RS485_TX_BUF DATA- X103
F 5 6 F
7 8
RS485_TX_EN RS485_TX_EN_BUF RS485_TX_EN_BUF CLOCK+ MALE-CONNECTOR-XJLZ6SG
9 10
6
4
2

NXHX-AIF RS485_CLK RS485_CLK_BUF RS485_CLK_BUF CLOCK-

X101 SHEET-2 SHEET-3

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


Figure 25: NXHX-ENC master schematic diagram
G
G
GND

R101 R102 R103 R104


10k 10k 10k 10k

0402
0402
0402
0402
H H
GND GND

I I

Edited Name Dominik Große-Schulte © Copyright


J Date 16.01.2017 NXHX-ENC J
Hilscher Gesellschaft für
Checked Name C. Marquardt Systemautomation mbH Page 1
Date 31.01.2017 www.hilscher.com MASTER P1701002 Ver. 1 Page of 4
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A A
Bus Driver
Reference

+3V3
B B
+3V3

place blocking capacitor near K201

14 K201-A
VCC C201
POWER BOX 0402 100nF R201
C GND C
16 V 10k

0402
7 74LVC126T protection resistor for the case
that netx pin is configured as output K201-B

NXHX 90-JTAG | Device description


R202
GND 3 2
[1] RS485_RX 0402 1Y 1A RS485_RX_BUF [1,3]
0
1
1OE

74LVC126T
D D

K201-C

5 6
[1] RS485_TX 2A 2Y RS485_TX_BUF [1,3]
4
2OE
E 74LVC126T E

K201-D

9 8
[1] RS485_TX_EN 3A 3Y RS485_TX_EN_BUF [1,3]
F 10 F
3OE

74LVC126T

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


K201-E

12 11
[1] RS485_CLK 4A 4Y RS485_CLK_BUF [1,3]
G 13
4OE
G
74LVC126T

Figure 26: NXHX-ENC bus driver schematic diagram


H H

I I

Edited Name Dominik Große-Schulte © Copyright


J Date 16.01.2017 NXHX-ENC J
Hilscher Gesellschaft für
Checked Name C. Marquardt Systemautomation mbH Page 2
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5V [1,4]
+3V3
A A
RS485-Driver
VCC_RS485 [3]
Reference

R315 R316 VCC_RS485 [3]


0 0

0402
0402
na

B B

R301 K301
pick and place R315 if K301/K302 = SN65HVD78D 8
10k VCC

0402
pick and place R316 if K301/K302 = SN65ALS176D C301 [1] DATA+
0402 100nF
16 V R306 R307
5
GND 240 240

0402
0402
C 3 C
[1,2] RS485_TX_EN_BUF DE
4 R304
[1,2] RS485_TX_BUF D 0 R305 [1] DATA-
6
A 0402 0

NXHX 90-JTAG | Device description


2 RE# B 7 0402
1
[1,2] RS485_RX_BUF 0402 R
R302 R303
R314 0
65ALS176D C302 C303
10k 10k

0402
0402
0402 330pF 0402 330pF
D 50 V 50 V D

GND GND GND GND GND

E E
VCC_RS485 [3]

F K302 F
R308 R309 R310 R311 8
VCC
10k 10k 10k 10k

0402
0402
0402
0402
C304 [1] CLOCK+
0402 100nF

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


16 V
5
GND
3
DE
G 4 R312
[1,2] RS485_CLK_BUF D 0 R313
6 G
A 0402 0
2 RE# B 7 0402 [1] CLOCK-
1
R

65ALS176D

Figure 27: NXHX-ENC RS-485 driver schematic diagram


C305 C306
0402 330pF 0402 330pF
50 V 50 V
H H
GND GND GND

I I

Edited Name Dominik Große-Schulte © Copyright


J Date 16.01.2017 NXHX-ENC J
Hilscher Gesellschaft für
Checked Name C. Marquardt Systemautomation mbH Page 3
Date 31.01.2017 www.hilscher.com RS485-DRIVER P1701002 Ver. 1 Page of 4
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A A
Reference

Step-Up Converter 3.3V --> 5V

B B

Ripplecurrent on inductivity: 67mA @ Outputcurrent 100mA


R401
C Bestückung geändert: 10uH von Würth 74437336100 15µH R402 C
IND-LSFS15UA1.4
MBRS140T3

NXHX 90-JTAG | Device description


[1,2,3] +3V3 [1,3] 5V

1
2
2
1
Inputvoltage: 3.3V T401 R403 Outputvoltage: 5V
470 R405
max. Inputcurrent: 152mA 8 7 Outputcurrent: 100mA
SW BOOT 0603 150k

0603
D D
6
VDD
C401 2 C403
EN
1206 22uF X7R R404 0603 39pF
10 V 100k
C402 50 V
C404 C405 C406

0603
0402 100nF 1206 22uF X7R 1206 22uF X7R 1206 22uF X7R
16 V 10 V 10 V 10 V
5 3
SGND FREQ
1 4
PGND FB

LM2621 R406
E 49.9k E

0603
PWM-Frequency: 1,65MHz
Referencevoltage: 1.24V
GND GND GND GND GND GND GND

F F

DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public


G
G

Figure 28: NXHX-ENC power supply schematic diagram


H H

I I

Edited Name Dominik Große-Schulte © Copyright


J Date 16.01.2017 NXHX-ENC J
Hilscher Gesellschaft für
Checked Name C. Marquardt Systemautomation mbH Page 4
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© Hilscher 2018
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Reference 72/82

4.2 Bills of materials

4.2.1 NXHX 90-JTAG


Reference Description Quantity Manufacturer product description Manufacturer
schematics
C1014 Ceramic capacitor SMD1210 1 KKK12486 1210AC103KAT1A AVX
C1019 C1020 Ceramic capacitor SMD0603 2 30.71.56 15pF 50V SMD0603 Murata
C1021 EEPROM ser. 2kBit 2.5-5.5V 1 M93C56-WMN6TP M93C56-WMN6P ST
Microelectronics
C1202 C1203 Ceramic capacitor SMD1210 2 35.83.69 GRM32ER72A225KA35L Murata
C1204 C1208 Ceramic capacitor SMD0805 3 36.24.29 GRM21BR71C475KA73L Murata
C1209
C1205 Ceramic capacitor SMD0402 1 44.17.48 CC0402JRX7R7BB473 Yageo
C1206 Ceramic capacitor SMD0603 1 36.51.43 GRM188R71C105KA12D Murata
C1207 Ceramic capacitor SMD0402 1 33.35.03 GRM155R71H221KA01D Murata
C300 C301 C303 Ceramic capacitor SMD0402 35 33.88.34 GRM155R71C104KA88D Murata
C304 C305 C306
C309 C310 C311
C312 C315 C317
C402 C500 C501
C502 C503 C504
C700 C800 C801
C802 C1000
C1001 C1002
C1004 C1007
C1008 C1009
C1010 C1011
C1013 C1016
C1018 C1022
C302 C307 C308 Ceramic capacitor SMD0805 10 38.18.47 CL21B106KPQNNNG Samsung
C313 C314 C316
C318 C1003
C1012 C1015
C400 C405 C600 Ceramic capacitor SMD0402 5 35.00.48 GRM1555C1H102JA01D Murata
C803 C1017
C401 FLASh ser. 32MBit 1 W25Q32FVSSIG-T+R Winbond
C403 C404 C1005 Ceramic capacitor SMD0201 4 81-GRM0335C1E100JA1J Murata
C1006 GRM0335C1E100JA01J
C505 Ceramic capacitor SMD1808 1 843-1808YA250102JSU Syfer
1808YA250102JXTSPU
C701 C702 C703 Ceramic capacitor SMD0402 4 36.62.10 CL05B103KB5NNNC Samsung
C704
G1000 Quarz 12MHz SMD 1 231717 Q 12,0-JXS32-12-30/50-T1- Jauch
LF
G400 Quarz 25MHz SMD 1 12.86591 KX-6E, 25MHZ Quarz Geyer electronic
SMD
K1000 Dual High Speed USB to 1 FT2232HQ-REEL Future
Multipurpose Technology
Devices Int.
K300 netX 90 1 - -
K700 Bus driver 4Bit 1 74FLVC126APW118 Qualcomm
K800 K801 K802 MULTI/DEMULTIPLEXER 3 959-0862 SN74CBTLV3257PW Texas
2:1, 4X Instruments
P1205 LED green SMD0603 1 LED25107 19-213/G6C-BM1N2/3T Everlight
P400 LED yellow/green SMD 1 HSMF-C166 Avago
(Broadcom)

NXHX 90-JTAG | Device description © Hilscher 2018


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Reference Description Quantity Manufacturer product description Manufacturer


schematics
P500 P501 LED red/green SMD 2 HSMF-C165 Avago
(Broadcom)
P700 P701 P702 LED yellow SMD0603 4 LED11503 19-213/Y2C-CN1P2B/3T Everlight
P703
Q1000 Voltage supervision 3V 1 576-3808-6-ND MIC803-30D2VM3- Microchip
TR
R1001 R1002 Resistor SMD 0402 1% 2 47.86.89 RC0402FR-0710RL Yageo
R1003 ESD Array 3 Channel SOT-5 1 296-21885-6-ND TPD3E001DRLR Texas
Instruments
R1005 Resistor SMD 1206 1 48.12.73 RC1206FR-071ML Yageo
R1006 Resistor SMD 0603 1 31.30.09 12K, 1%, 100mW, Samsung
SMD0603
R1008 Resistor SMD 0402 1 CRCW04024R70FKED VISHAY
R1014 R1215 Resistor SMD 0402 2 47.89.21 RC0402FR-072K2L Yageo
R1200 Schottky Diode SMD 1 TSSW3U45 RVG Taiwan
Semiconductor
R1201 2.2µH, 0.7A, 200mOhm, 1 744 797 752 22A 2.2µH, 0.7A, Würth
50MHz 200mOhm, 50MHz
R1202 TVS-Diode, single bidir. 1 SM6T36CA ST
Microelectronics
R1203 Resistor SMD 0402 1 2140831RL CRCW04025K10FKED VISHAY
R1205 R1214 Resistor SMD 0402 2 RC1005F103AS Samsung
R1206 Zener diode 1 2319297 BZX84-C12,215 Nexperia
R1208 Zener diode 1 BZX84-C4V7 Qualcomm
R1210 Resistor SMD 0402 1 47.87.01 RC0402FR-0711KL Yageo
R1212 Resistor SMD 0402 1 47.88.07 RC0402FR-071K5L Yageo
R1213 Storage throttle SMD 1 744 373 242 20 22µF, 1A, 500mohm, Würth
14MHz
R200 R201 R1009 Resistor SMD 0402 3 36.88.62 RC0402FR-074K7L Yageo
R202 R203 R206 Resistor SMD 0201 29 667-ERJ-1GNF1002C Panasonic
R405 R410 R600 ERJ-1GNF1002C
R601 R602 R603
R604 R605 R606
R607 R608 R609
R610 R611 R612
R613 R614 R615
R616 R704 R800
R801 R1010
R1011 R1012
R1013
R205 Resistor SMD 0201 1 RC0201FR076K49L Yageo
R300 10µH, 0.6A, 733mohm, 1 744 383 231 00 Würth
25MHz
R301 R302 R1000 Ferrite suppressor choke 4 742 792 040 600 Ohm, 2A, Würth
R1004 SMD 0805 SMD0805
R400 R401 R501 Resistor SMD 0402 6 47.89.02 RC0402FR-07270RL Yageo
R505 R507 R509
R402 R403 R1007 Resistor SMD 0402 3 47.87.92 RC0402FR-071KL Yageo
R404 R406 R407 Resistor SMD 0201 3 CR0201-FW-4701GLF Bourns
R408 R409 Schottky Diode 2 MBR0520LT1G ON
Semiconductor
R411 R1211 Resistor SMD 0402 2 47.94.22 RC0402JR-070RL Yageo
R500 R504 R506 Resistor SMD 0402 4 32.19.24 120R 63mW 1% SMD 0402 Samsung
R508
R502 Diode SMD 1 BAS316,115 Qualcomm

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Reference Description Quantity Manufacturer product description Manufacturer


schematics
R503 Resistor SMD 0603 1% 1 WRC32599 RC0603FR-071KL Yageo
R700 R701 R702 Resistor SMD 0201 4 CR0201-FW-1001GLF Bourns
R703
R705 R706 R707 Resistor SMD 0402 5 47.91.60 RC0402FR-07680RL Yageo
R708 R1216
R709 R710 Resistor SMD 0603 1% 2 47.95.58 RC0603FR-071K3L Yageo
R711 R712 Resistor SMD 0603 2 47.98.01 RC0603FR-073K3L Yageo
S400 Slide switch SMD CHS-06 1 570110173 CHS-06TA Copal
S401 Push button SMD CB-AB32 1 Omron B3S1000-P Omron
S701 Slide switch SMD CHS-04 1 570110069 CHS-04TA Copal
T1200 Step Down regulator 40Vin 1 XR76205ELMTR-F Exar
5A
X400 Connector 20pol. 1 FTSH-110-01-L-DV-007-K Samtec
P100 PCB NXHX 90-JTAG 1 488045 L1627003 Würth
S700 DIP switch (4) 1 17G555 NDS–04, 4 Schalter, A Diptronics
11,68 mm
X1000 Mini USB jack 5pol. 1 054819-0519 Molex 0548190519 Molex
X1200 Power connector jack 1 CP-014C-ND CONN POWER JACK CUI INC.
1MM; PJ-014C
X500 RJ45 jack 2Ports, 2xLED 1 FETRA1374 JX80-0037NL Pulse
X600 Connector 68pol. 1 12C09-068SB SL-RM1,27-68pol. FJH Stecker-
(2x34) verbindung
GmbH
X900 X901 X902 Pin header 2*5pol. 3 102.126.010.26 12.6mm FJH Stecker-
verbindung
GmbH
X601 Pin header 2*8pol. 1 102.113.016.26 11.3mm FJH Stecker-
verbindung
GmbH
X700 Pin header 2*5pol. 1 102.113.010.26 11.3mm FJH Stecker-
verbindung
GmbH
X701 X702 X703 Jumper 2.54 mm 4 301.202.001.1 FJH Stecker-
X704 verbindung
GmbH
X900 X901 X902 Pin header 2*5pol. 3 102.126.010.26 12.6mm FJH Stecker-
verbindung
GmbH
Table 58: Bill of material NXHX 90-JTAG

NXHX 90-JTAG | Device description © Hilscher 2018


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Reference 75/82

4.2.2 NXHX-SDRSPM
Reference Description Quantity Manufacturer product Manufacturer
schematics description
C1, C3, C4, C5, C6, Ceramic capacitor SMD 0402 19 GRM155R71C104KA88D Murata
C7, C802, C805, 100nF 16V X7R SMD0402
C807, C811, C1011,
C1012, C1013,
C1014, C1015,
C1016, C1017,
C1021, C1025
C8, C9, C804, Ceramic capacitor SMD 0805 5 CL21B106KPQNNNG Samsung
C1020, C1024 10uF 10V X7R SMD0805
C800, C801 Ceramic capacitor SMD 0402 2 CL05C100JB5NNNC Samsung
10pF 50V SMD0402
C803 Ceramic capacitor SMD 1210 1 1210AC103KAT1A AVX
10nF 1000V X7R SMD1210
C808, C809 Ceramic capacitor SMD 0603 2 GRM1885C1H150JA01D Murata
15pF 50V SMD0603
C810 EEPROM ser. 2kBit 2.5-5.5V 1 M93C56-WMN6P ST
Microelectronics
G800 Quarz 12MHz SMD 1 Q 12,0-JXS32-12-30/50-T1-LF Jauch
K800 Dual High Speed USB to 1 FT2232HQ Future
Multipurpose Technology
Devices Int.
Q800 Voltage monitoring 3V 1 MIC803-30D2VM3-TR Micrel
R1016, R1018 Ferrite filter chokes 2 742 792 040 Würth
600Ohm@100 MHz, IR=2A, RDC:
0.15 Ohm
R800, R801 Resistor SMD 0402 2 10R, 1%, 63mW, SMD0402 Yageo
R802 ESD ARRAY 3 CHANNEL 1 IC ESD-PROT ARRAY 3CH SOT-5 Texas
SOT-5 Instruments
R803 Resistor SMD 1206 1 RC3216F105CS / Samsung
RC3216F1004CS
1M, 1%, 250mW, SMD1206
R806 Resistor SMD 0603 1 RC1608F1202CS / Samsung
RC1608F123CS
12K, 1%, 63mW, SMD0603
R808 Resistor SMD 0402 1 CRCW04024R70FKED VISHAY
4R7, 1%, 63mW, SMD0402
R809 Resistor SMD 0402 1 RC0402FR-074K7L Yageo
4K7, 63mW, SMD0402
R810, R811, R812, Resistor SMD 0402 4 RC1005F1002CS= Samsung
R814 RC1005F103CS / RC1005F103AS
10K, 1%, 63mW, SMD0402
R813 Resistor SMD 0402 1 RC0402FR-072K2L Yageo
2.2K, 1%, 63mW SMD0402
C2 SDRAM 64MBit FBGA54 3.3V 1 IS45S16400J-7BLA2 ISSI
X400 Socket terminal strip 68 pin 1 127ST-068SB BL "1.27x2.54" 68 FJH Stecker-
pin (2x34) verbindung
GmbH
X2 Mini USB socket 1 54819-0519 XUSBB5BW-MINI Molex
Table 59: Bill of material NXHX-SDRSPM (7703.080 Revision 1)

NXHX 90-JTAG | Device description © Hilscher 2018


DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public
Reference 76/82

4.2.3 NXHX-FTDI
Reference Description Quantity Manufacturer product description Manufacturer
schematics
C100, C101, C102, Ceramic capacitor SMD0805 9 31.63.85 100nF 25V SMD 0805 X7R Samsung
C103, C104, C105, 1%
C106, C108, C110
C107, C109 Ceramic capacitor SMD0805 2 37.65.36 10uF 10V SMD0805 X5R Samsung
15%
C111 Ceramic capacitor SMD1210 1 35.23.01 3,3uF, 50V, 20%, 1210 X7R Samsung
C113, C114 Ceramic capacitor SMD0603 2 31.17.25 27PF 50 V SMD 0603 Samsung
C115 Ceramic capacitor SMD0603 1 32.91.65 100nF 50V SMD 0603 X7R Samsung
10%
C116 Ceramic capacitor SMD0603 1 31.17.09 CL10B102KB8NNNC Samsung
C112 EEPROM ser. 2kBit 2.5-5.5V 1 M93C56-WMN6P M93C56-WMN6P ST
Microelectronics
G100 Quarz 12MHz SMD 1 221280 Q12.0-JXG75P2-12-30/50- Jauch
T1-LF
K1 Dual High Speed USB to 1 FT2232HQ Future
Multipurpose Technology
Devices Int.
Q1 Voltage monitoring 3V, 20ms 1 MIC6315-30D2UY-TR Micrel
R100, R101 Ferrite filter chokes 2 742 792 18R 600 Ohm, 1A, Würth
SMD1206, RoHS
R102, R103 Resistor SMD 0603 2 47.96.40 RC0603FR-0722RL Yageo
R106 Resistor SMD 1206 1 31.39.25 12k 250mW 1% SMD 1206 Samsung
R108 Resistor SMD 0805 1 48.02.83 RC0805FR-0710KL Yageo
R109 Resistor SMD 0805 1% 1 48.05.56 RC0805FR-072K2L Yageo
R114 Resistor SMD 0603 1 47.95.64 RC0603FR-071K5L Yageo
R115 Resistor SMD 0603 1% 1 47.95.47 RC0603FR-071KL Yageo
X100 Mini USB socket, 5 pol 054819-0519 Molex 54819-0519 Molex
X400 Socket terminal strip 68 pin 1 127ST-068SB BL "1.27x2.54" 68 pin FJH Stecker-
(2x34) verbindung
GmbH
Table 60: Bill of material NXHX-FTDI (7703.050 Revision 2)

NXHX 90-JTAG | Device description © Hilscher 2018


DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public
Reference 77/82

4.2.4 NXHX-ENC
Reference Description Quantity Manufacturer product description Manufacturer
schematics
C201 C301 C304 Ceramic capacitor SMD0402 4 GRM155R71C104KA88D Murata
C402 100nF 16V X7R SMD0402
C302 C303 C305 Ceramic capacitor SMD0402 4 35.12.47 330pF 50V SMD0402 Murata
C306 COG
C401 C404 C405 Ceramic capacitor SMD1206 4 885 012 208 019 Würth
C406 X7R1206226K010DFCT10000
C403 Ceramic capacitor SMD0603 1 31.17.31 39pF 50V SMD 0603, Samsung
C0G 5%
F101 Fuse Poly switch 1 1210L020WR 1210L020WR,; Littlefuse
200mA, 30V, SMD_1210 Litelfuse
K201 Bus driver 4 bit 1 74FLVC126APW118 Qualcomm
K301 K302 Driver RS485 SOIC 5V 1 SN65ALS176DRG4 SO8 Texas Instruments
35MB
R101 R102 R103 Resistor SMD 0402 14 RC1005F103AS Samsung
R104 R201 R202
R301 R302 R303
R308 R309 R310
R311 R314
R202 R304 R305 Resistor SMD 0402 1% 7 47.86.89 RC0402FR-0710RL Yageo
R312 R313 R316
R314
R306 R307 Resistor SMD 0402 1% 2 32.19.44 240R, 1%, 63mW, Samsung
SMD0402
R316 Resistor SMD 0402 1 47.94.22 RC0402JR-070RL Yageo
R401 Storage throttle SMD 1 744 373 361 00 Würth
10uH, 2.4A, 128mOhm, 16MHz
R402 Schottky diode SMD B14 1 MBRS140T3G ON Semiconductor
R403 Resistor SMD 0603 1 47.98.66 RC0603FR-07470RL Yageo
R404 Resistor SMD 0603 1 076689 RC0603 FR-07 200 K 0603 Yageo
1% 0,1 WATT
R405 Resistor SMD 0603 1 076686 RC0603 FR-07 150K 0603 Yageo
1% 0,1 WATT
R406 Resistor SMD 0603 1% 1 4224528 RESISTOR, SMD 49K9 Multicomp
T401 Step Up converter 1.24...14V 1 LM2621MM/NOPB National
Semiconductor
X101 Connector 2x5pol SMD RM 1 254AW-010GB-P Buchsenleiste FJH
2.54mm 10pol. RM 2.54 Steckerverbindung
GmbH
X102 X103 Jumper strip 2*3pol. 2 102.113.006.26 11.3mm FJH
Steckerverbindung
GmbH
Table 61: Bill of material NXHX-ENC (7924.000 Revision 2)

NXHX 90-JTAG | Device description © Hilscher 2018


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4.3 Matrix label


The NXHX 90-JTAG board is equipped with a matrix label. For identifying
the label on the board, see position (24) in section Positions of interfaces
and operating elements [} page 12].
The label indicates:
· Part number (1)
· Hardware revision (2)
· Serial number (3)

Figure 29: Matrix label NXHX 90-JTAG

In this example, the label shows part number 7833.000, hardware revision
2 and serial number 23457.

4.4 Technical data NXHX 90-JTAG


Item Value
Supply voltage +24 V DC
Processor netX 90 MP
Memory 4 MByte SQI Flash
LEDs SYS (system status)
PWR (power status)
COM0 (communication status)
COM1 (communication status)
4 x user LEDs (yellow)
2 x ACT (at RJ45 jack)
2 x LINK (at RJ45 jack)
Operating elements Reset push-button
Boot mode configuration slide switch
Console mode configuration slide switches
JTAG mode configuration slide switch
UART mode configuration slide switch
User LEDs configuration slide switch
User-defined input slide switches
USB (type Mini-B) JTAG-to-USB debugging and UART-to-USB diagnosis/
firmware download (via on-board FTDI)
2 x RJ45 Ethernet
Dimensions (L x W x D) 100 x 65 x 20 mm
Operating temperature 0 … 55 °C
Table 62: NXHX 90-JTAG technical data

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List of figures 79/82

List of figures
Figure 1: NXHX 90-JTAG block diagram............................................................................. 11
Figure 2: Positions on NXHX 90-JTAG................................................................................ 12
Figure 3: NXHX-SDRSPM ................................................................................................... 35
Figure 4: NXHX-FTDI printed circuit board.......................................................................... 38
Figure 5: NXHX 90-JTAG connected to NXPCA-PCI Board .............................................. 40
Figure 6: Fieldbus connector (dimensions in mm)............................................................... 42
Figure 7: NXHX-ENC printed circuit board .......................................................................... 46
Figure 8: NXHX-IOL............................................................................................................. 48
Figure 9: Software reset enabled (OUT_I/Q signal disabled) .............................................. 50
Figure 10: OUT_I/Q signal enabled (Software reset disabled) .............................................. 50
Figure 11: netX 90 CPU core schematic diagram ................................................................. 53
Figure 12: netX 90 power supply schematic diagram............................................................ 54
Figure 13: System schematic diagram .................................................................................. 55
Figure 14: Ethernet interface schematic diagram .................................................................. 56
Figure 15: Host interface schematic diagram ........................................................................ 57
Figure 16: IO/ADC schematic diagram .................................................................................. 58
Figure 17: Switching matrix schematic diagram .................................................................... 59
Figure 18: Extension boards schematic diagram................................................................... 60
Figure 19: FTDI to USB schematic diagram .......................................................................... 61
Figure 20: +24V Power supply schematic diagram ............................................................... 62
Figure 21: NXHX-SDRSPM connector schematic diagram ................................................... 64
Figure 22: NXHX-SDRSPM SDRAM schematic diagram...................................................... 65
Figure 23: NXHX-SDRSPM FTDI schematic diagram........................................................... 66
Figure 24: NXHX-FTDI Schematic Diagram (P1118501) ...................................................... 67
Figure 25: NXHX-ENC master schematic diagram................................................................ 68
Figure 26: NXHX-ENC bus driver schematic diagram........................................................... 69
Figure 27: NXHX-ENC RS-485 driver schematic diagram .................................................... 70
Figure 28: NXHX-ENC power supply schematic diagram ..................................................... 71
Figure 29: Matrix label NXHX 90-JTAG................................................................................. 78

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List of tables 80/82

List of tables
Table 1: List of revisions ....................................................................................................... 4
Table 2: Reference to hardware ........................................................................................... 4
Table 3: Additional documentation ....................................................................................... 5
Table 4: Positions on printed circuit board............................................................................ 12
Table 5: S400 for configuring console mode and alternative boot mode.............................. 15
Table 6: S401 – Reset button ............................................................................................... 16
Table 7: S700 for user-defined inputs................................................................................... 16
Table 8: S701 miscellaneous configuration .......................................................................... 16
Table 9: Pin assignments MIPI-20 JTAG connector............................................................. 17
Table 10: Ethernet RJ45 pin assignment................................................................................ 18
Table 11: Pin assignment of X600 according to HIF mode (1) ............................................... 20
Table 12: Pin assignment of X600 according to HIF mode (2) ............................................... 21
Table 13: Signal options of X600 pins – MMIO and internal interfaces (1)............................. 22
Table 14: Signal options of X600 pins – MMIO and internal interfaces (2)............................. 23
Table 15: Signal options of X600 pins – communication interfaces and digital I/O (1)........... 24
Table 16: Signal options of X600 pins – communication interfaces and digital I/O (2)........... 25
Table 17: Signal options of X600 pins – communication interfaces and digital I/O (3)........... 26
Table 18: Pin assignments X601 ............................................................................................ 26
Table 19: Pin assignments X700 ............................................................................................ 27
Table 20: Pin Assignment X900 ............................................................................................. 28
Table 21: Pin assignments X901 ............................................................................................ 29
Table 22: Pin assignments X902 ............................................................................................ 30
Table 23: Pin assignments of Mini-B USB connector ............................................................. 31
Table 24: Pin assignments X1001 .......................................................................................... 31
Table 25: Pin assignment power supply socket...................................................................... 32
Table 26: LEDs on the NXHX 90-JTAG.................................................................................. 33
Table 27: System Status LED................................................................................................. 34
Table 28: Positions in figure ................................................................................................... 35
Table 29: Technical data NXHX- SDRSPM device ................................................................ 36
Table 30: Pinning host interface of NXHX-SDRSPI device .................................................... 37
Table 31: Pinning of USB interface......................................................................................... 38
Table 32: Positions in figure ................................................................................................... 38
Table 33: Technical data NXHX-FTDI device......................................................................... 39
Table 34: Pinning host interface X400 of NXHX-FTDI device ................................................ 39
Table 35: Pinning of USB interface......................................................................................... 40
Table 36: Technical data CAB-NXPCA-PCI ........................................................................... 41
Table 37: Technical data CAB-NXEB5 ................................................................................... 41
Table 38: Technical data CON-NXHIF/M ............................................................................... 41
Table 39: Pins of connector to NXHX Fieldbus adapter ......................................................... 42
Table 40: NXHX-DP technical data ........................................................................................ 43

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List of tables 81/82

Table 41: PROFIBUS RS-485 pin assignment ....................................................................... 43


Table 42: NXHX-CO technical data ........................................................................................ 43
Table 43: CANopen pin assignment ....................................................................................... 43
Table 44: NXHX-DN technical data ........................................................................................ 44
Table 45: DeviceNet pin assignment ...................................................................................... 44
Table 46: NXHX-CC technical data ........................................................................................ 44
Table 47: CC-Link pin assignment.......................................................................................... 44
Table 48: NXHX-RS technical data ........................................................................................ 45
Table 49: RS-232 pin assignment D-Sub ............................................................................... 45
Table 50: Positions on NXHX-ENC ........................................................................................ 46
Table 51: Pin assignments X102 ............................................................................................ 47
Table 52: Pin assignments X103 ............................................................................................ 47
Table 53: Positions on NXHX-IOL .......................................................................................... 49
Table 54: NXHX-IOL technical data........................................................................................ 49
Table 55: Pin assignment IO Link connector .......................................................................... 49
Table 56: Pin assignment supply voltage ............................................................................... 49
Table 57: Technical data power supply NXAC-POWER ........................................................ 51
Table 58: Bill of material NXHX 90-JTAG .............................................................................. 72
Table 59: Bill of material NXHX-SDRSPM (7703.080 Revision 1) ......................................... 75
Table 60: Bill of material NXHX-FTDI (7703.050 Revision 2)................................................. 76
Table 61: Bill of material NXHX-ENC (7924.000 Revision 2) ................................................. 77
Table 62: NXHX 90-JTAG technical data ............................................................................... 78

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Contacts

HEADQUARTERS
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Support
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SUBSIDIARIES
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E-mail: info@hilscher.cn E-mail: info@hilscher.jp
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Support Support
Phone: +39 02 25007068 Phone: +1 630-505-5301
E-mail: it.support@hilscher.com E-mail: us.support@hilscher.com

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DOC170202HW02EN | Revision 2 | English | 2018-11 | Released | Public

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