LG 60pz750-Ug Chassis Pu12a

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
PLASMA TV
SERVICE MANUAL
CHASSIS : PU12A
MODEL : 60PZ750 60PZ750-UG
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67006104(1103-REV00) Printed in Korea

CONTENTS
CONTENTS ............................................................................................................................... 2
SAFETY PRECAUTIONS ...........................................................................................................3
SPECIFICATION.........................................................................................................................4
ADJUSTMENT INSTRUCTION ..................................................................................................6
BLOCK DIAGRAM ...................................................................................................................13
EXPLODED VIEW ...................................................................................................................14
CIRCUIT DIAGRAM .....................................................................................................................
Copyright ©2011 LG Electronics Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in
the Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to
prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the Do not use a line Isolation Transformer during this check.
servicing of a receiver whose chassis is not isolated from the AC Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
power line. Use a transformer of adequate power rating as this between a known good earth ground (Water Pipe, Conduit, etc.)
protects the technician from accidents resulting in personal injury and the exposed metallic parts.
from electrical shocks. Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
It will also protect the receiver and it's components from being Reverse plug the AC cord into the AC outlet and repeat AC
damaged by accidental shorts of the circuitry that may be voltage measurements for each exposed metallic part. Any
inadvertently introduced during the service operation. voltage measured must not exceed 0.75 volt RMS which is
corresponds to 0.5mA.
If any fuse (or Fusible Resistor) in this monitor is blown, replace it In case any measurement is out of the limits specified, there is
with the specified. possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
When replacing a high wattage resistor (Oxide Metal Film
Resistor, over 1W), keep the resistor 10mm away from PCB.
Keep wires away from high voltage or high temperature parts. Leakage Current Hot Check circuit
Due to high vacuum and large surface area of picture tube, AC Volt-meter
extreme care should be used in handling the Picture Tube.
Do not lift the Picture tube by it's Neck.
Good Earth Ground

Leakage Current Cold Check(Antenna Cold Check) such as WATER PIPE,
With the instrument AC plug removed from AC source, connect To Instrument's CONDUIT etc.
0.15uF
an electrical jumper across the two AC plug prongs. Place the exposed
AC switch in the on position, connect one lead of ohm-meter to METALLIC PARTS
the AC plug prongs tied together and touch other ohm-meter
lead in turn to each exposed metallic parts such as antenna
terminals, phone jacks, etc. 1.5 Kohm/10W
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATIONS
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application Range
(1) This spec sheet is applied all of PDP TV with PU12A chassis.
Model Name Market Brand
60PZ750-UG NORTH AMERICA LG
CANADA / MEXICO / PANAMA / COLOMBIA
2. Specification
Each part is tested as below without special appointment.
(1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 °C ± 5 °C
(2) Relative Humidity : 65 % ± 10 %
(3) Power Voltage : Standard input voltage (100 V - 240 V ~ 50 / 60 Hz)
* Standard Voltage of each product is marked by models
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test Method
(1) Performance : LGE TV test method followed.
(2) Demanded other specification
Safety : UL, CSA, IEC specification, CE
EMC : FCC, ICES, IEC specification, CE
Model Name Market Remark
60PZ750-UG NORTH AMERICA Safety : UL1492, CSA C22.2.No.1
EMC : FCC Class B, IC Class B
4. General Specification
No Item Specification Remark
1. Receiving System 1) ATSC / NTSC-M
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02~69
4) CATV : 01~135
5) CADTV : 01~135
3. Input Voltage 1) AC 100 V - 240 V ~ 50 / 60 Hz N.America Mark : 110V, 60Hz
4. Market NORTH AMERICA, KOREA
5. Screen Size 127 cm (50 inch) Wide(1920 × 1080) 50PZ950-UA, 50PZ950-UF
152 cm (60 inch) Wide(1920 × 1080) 60PZ950-UA, 60PZ950-UF
6. Aspect Ratio 16:9
7. Tuning System FS
8. PDP Module PDP50R3#### (1920 × 1080) 50PZ950-UA, 50PZ950-UF
PDP60R3#### (1920 × 1080) 60PZ950-UA, 60PZ950-UF
9. Operating Environment 1) Temp : 0 deg ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1) Temp : -20 deg ~ 60 deg
2) Humidity : ~ 85 %
ADJUSTMENT INSTRUCTION
1. Application Range 4. MAC Address and ESN Key Write

This spec. sheet applies to PU12A Chassis applied PDP TV
all models manufactured in TV factory. 4-1. Equipment & Condition
- Play file: Serial.exe
- MAC Address edit
- Input Start / End MAC address
2. Specification
(1) Because this is not a hot chassis, it is not necessary to use 4-2. Download method
an isolation transformer. However, the use of isolation (1) Communication Prot connection
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 cC ± 5 cC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep 100 V - 240 V,
50 / 60 Hz. Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over (2) MAC Address Download
15 cC - Com 1,2,3,4 and 115200(Baudrate)
- In case of keeping module is in the circumstance of 0 cC, - Port connection button click(1)
it should be placed in the circumstance of above 15 cC for
2 hours
- In case of keeping module is in the circumstance of below
-20 cC, it should be placed in the circumstance of above
15 cC for 3 hours.
Caution) When still image is displayed for a period of 20 minutes

or longer (especially where W/B scale is strong. Digital
pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area.
3. Adjustment items - Load button click(2) for MAC Address write.

- Start MAC Address write button(3)
- Check the OK Or NG
3-1. Board-level adjustment
(3) Input the ESN Key
- Mac address and Idfile(ESN) Download (Except Mexico/Canada Models)
- Adjust 480i Comp1 adj. - download Model sending Key file
- Adjust 1080p Comp1 adj. - input by 1 by SET so as not to be duplicated
- Adjust 1920*1080 RGB adj.
- EDID/DDC download
Above adjustment items can be also performed in Final
Assembly if needed. Both Board-level and Final assembly
adjustment items can be check using In-Start Menu 1.
Adjust Check.
3-2. Final assembly adjustment

- White Balance adjustment
- RS-232C functionality check
- Factory Option setting per destination
- Ship-out mode setting (In-Stop)
3-3. Etc.
- Ship-out mode
- Service Option Default
- USB Download(S/W Update, Option)
5. LAN PORT + ESN INSPECTION 6. ADC adjustment
5-1. Equipment & Condition 6-1. Overview
- Each other connection to LAN Port of IP Hub and Jig ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.
6-2. Equipment & Condition

(1) Jig (RS-232C protocol)
(2). Internal pattern is used. No external signal is needed.
6-3. Adjustment
(1) Adj. protocol
5-2. MAC Address & ESN Key & widevine
Key confirmation
MAC Address & ESN Key & widevine Key confirmation
MAC Address : All Models
widevine Key : All Models
ESN Key D/L : Except Mexico/Canada Models
- Push “IN-START” Key in service remote controller.
(2) Check adjust device

Pattern Generator : (MSPG-925FA)
Adjust 480i Comp1
(MSPG-925FA:model :209 , pattern :65)
Adjust 1080p Comp1
(MSPG-925FA:model :225 , pattern :65)
5-3. LAN PORT INSPECTION(PING TEST) Adjust RGB (MSPG-925FA:model :225 , pattern :65)
- LAN Port connection with PCB The PU02A have not ECHO.
- Network setting at MENU Mode of TV
- setting automatic IP
- Setting state confirmation
-> If automatic setting is finished, you confirm IP and MAC
Address. 7. EDID(The Extended Display
Identification Data) / DDC(Display
Data Channel) download
7-1. Overview
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity
of user input. It is a realization of °∞Plug and Play°±.
7-2. Equipment
- Adj. R/C
- remove LAN CABLE - Since embedded EDID data is used, EDID download jig,
HDMI cable and D-sub cable are not need.
7-3. Download method

(1) Press Adj. key On the Adj. R/C, press Adj. key then select
EDID D/L. By pressing Enter key, EDID download will
begin.
(2) If Download is successful, OK is displayed.
(3) If Download is a failure, NG is displayed.
(4) Re-try download
7-4. EDID DATA(PCM) 7-5. EDID DATA(AC-3)
- Reference: Download is only possible in POWER ON - Reference: Download is only possible in POWER ON
MODE. MODE.
- HDMI - HDMI
EDID Block 0, Bytes 0-127 [00H-7FH] EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type : EDID 1.4 Block Type : EDID 1.4
EDID Block 1, Bytes 128-255 [80H-FFH]

Block Type: CEA EDID Timing Extension Version 3
EDID Block 1, Bytes 128-255 [80H-FFH]

Block Type: CEA EDID Timing Extension Version 3
Vender ID C/S1 C/S2

HDMI1 10 9C 60
Vender ID C/S1 C/S2 HDMI2 20 9C 50
HDMI1 10 9C D2 HDMI3 30 9C 40
HDMI2 20 9C C2 HDMI4 40 9C 30
HDMI3 30 9C B2
HDMI4 40 9C A2
RGB [C/S: 1C]
EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type: EDID 1.3
RGB [C/S: 1C]

EDID Block 0, Bytes 0-127 [00H-7FH]
Block Type: EDID 1.3
8. White Balance adj. Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
8-1. Overview jb 00 c0
(1) W/B adj.: Objective & How-it-works ...
1) Objective: To reduce each Panel’s W/B deviation ...
2) How-it-works: When R/G/B gain in the OSD is at 192, it wb 00 1f -> Gain adj. complete
means the panel is at its Full Dynamic *(wb 00 20(Start), wb 00 2f(End)) -> Off-set adj.
Range. In order to prevent saturation of wb 00 ff -> End white balance auto-adj.
Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is
lowered to find the desired value. 8-5. Auto Adj. method
(1) Set TV in adj. mode using POWER On Key
8-2. Equipment (2) Zero calibrate probe then place it on the center of the
(1) Color Analyzer : CA-210 (NCG: CH 9 / WCG: CH12 /PDP Display
Module:CH10) (3) Connect Cable(RS-232C)
(2) Adj. Computer (4) Select mode in adj. Program and begin adj.
(During auto adj., RS-232C protocol is needed) (5) When adj. is complete (OK Sign), check adj. status per
(3) Adj. R/C mode
(4) Video Signal Generator MSPG-925F 720p/216Gray (Warm, Medium, Cool)
(Model:217, Pattern:78) (6) Remove probe and RS-232C cable to complete adj.
-> Only when internal pattern is not available - Adj. must begin w/ command “wb 00 00”, and end “wb 00
ff” and adj. offset if needed.
- Color Analyzer Matrix should be calibrated using CS-1000 - Offset adjust limit value.
Offset Min = 34 (Decimal)
8-3. Equipment connection map Offset Max = 94 (Decimal)
8-6. Manual adj. method

Dynamic contrast : off
Dynamic color : off
OPC : Off
Energy saving mode : Off
(1) Set TV Picture Mode to Standard and in Advanced
Control, set Dynamic Contrast and Color ‘ Off ’ .
(2) Set TV in adj. mode using POWER On Key
(3) Press ADJ key -> EZ adjust using adj. R/C
(4) Using CH + / - KEY, select 10.TEST PATTERN then press
Enter to place in HEAT RUN mode and wait for 30
8-4. Adj. Command (Protocol) minutes.
(4) Zero calibrate the probe of Color Analyzer, then place it on
O Protocol
the center of LCD module within 10 cm of the surface.
<Command Format>
(5) Press ADJ key -> 7. White-Balance then press the cursor
to the right (KEY G)
(When G is pressed Full White internal pattern will be
- LEN: Number of Data Byte to be send displayed)
- CMD: Command (6) One of R Gain / G Gain / B Gain should be fixed at 192,
- VAL: FOS Data and the rest will be lowered to meet the desired value.
- CS: Checksum of sent Data (7) Adj. is performed in COOL, MEDIUM, WARM 3 modes of
- A: Acknowledge color temperature
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] (8) Offset Adjust in MEDIUM, WARM 2 modes of color
temperature ( Only THX Model )
O RS-232C Command used during auto-adj.
V If internal pattern is not available, use HDMI input. In EZ

Adj. menu 7.White Balance, you can select one of 3
options: None, Inner, HDMI. Default is inner. By selecting
HDMI, you can adjust using HDMI signal.
V Adj. condition and cautionary items
(1) Lighting condition in surrounding area
10. Ping TEST
* This test is to check Network operation.
Surrounding lighting should be lower than 10 lux. Try
to isolate adj. area into dark surrounding.
(2) Probe location
- PDP : Color Analyzer (CA-100, CA-100+, CA210)
probe should be firmly attached to the Module
- LCD : Color Analyzer (CA-210) probe should be within
10cm and perpendicular of the module surface
(80°~ 100°) 10-1. Equipment Setting
- In case of LCD, B/L on should be checked using no (1) Play the LAN Port Test PROGRAM.
signal or Full white Pattern (2) Input IP set up for an inspection to Test
*IP Number : 12.12.2.2
8-7. Reference (White Balance adj.
coordinate and color temperature)
O Standard color coordinate and temperature using CS-1000
O Luminance: Full white 216 Gray
11. LAN PORT inspection
(PING TEST)
* In this case Network setting is on Manual Setting.
(1) Play the LAN Port Test Program.
(2) connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) remove LAN CABLE
O Standard color coordinate and temperature using CA-210(CH
10)
- Gain color coordinate
O Pattern : Full white 216 Gray
- Offset color coordinate : Only THX model

O Pattern : Full white 50 Gray
O Luminance : 5 ± 4 cd
12. Check Wireless function.

(1) Connect set and Dongle of Wireless to Cable of HDMI &
TTA 20Pin
(2) At OSD of SET, check the message like Fig 3.
(3) Detach Cable of Wireless Dongle
9. Checking the EYE-Q Operation.

(1) Press the EYE Key on the adjustment remote controller.
(2) Check the Sensor DATA ( It must be under 10) and keep
the data longer than 1.5s
(3) Check ‘OK’
(Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)

* IF you press IN-STAP Button, change Green Eye-check OSD.
Copyright ©2011 LG Electronics Inc. All rights reserved. - 10 - LGE Internal Use Only
13. Magic Motion Remote Controller (4) Put on the 3D Glasses, And block the right side of Glasses
(LEFT:CLOSED, RIGHT:OPEN[TEST])
test And check the middle sides of picture , BLUE -> normal ,
Required Equipment others -> abnormal
- RF Remote Controller for test, IR-KEY-Code Remote
Controller for test
* You must confirm the battery power of Remote Controller
before test
(Recommend that change the battery per every lot)
(1) If you select the ‘start key(Mute)’ on the controller, you can
pairing with the TV SET.
(2) You can check the cursor on the TV Screen, when select
the ‘OK Key’ on the controller
(3) You must remove the pairing with the TV Set by select
‘Vol+(STOP) Key’ on the controller
15. Check RF Emitter.

14. 3D Function Test Required Equipment
- Pattern Generator : 3D-GT002, MSHG-600,
(Pattern Generator MSPG-3233, HDMI mode NO. 371 , MSPG-6100 [SUPPORT HDMI1.4])
pattern No. 81) MODE : HDMI mode NO. 872
Pattern No.83
(1) Please input 3D test pattern like below
(1) On 3D Mode, Check the picture like below.
(2) Enter 3D mode , then select side by side (2) If RF Emitter is correctly working, you can see that the
(If you don’t wear a 3D Glasses, you will see the picture lamp of RF tester turns on.
like below)
16. Option selection per country

(3) Put on the 3D Glasses, And block the right side of Glasses
(LEFT:OPEN[TEST], RIGHT:CLOSED)
And check the middle sides of picture , RED -> normal , 16-1. Overview
others -> abnormal O Option selection is only done for models in Non-USA North
America due to rating
O Applied model: PU02A Chassis applied USA Model(Not
Canada, Mexico)
16-2. Method
(1) Press ADJ key on the Adj. R/C, then select Country Group
Menu
(2) Depending on destination, select KR or US, then on the
lower option, select US, CA, MX. Selection is done using
+, - KEY
16-3. Ship-out (Default) mode check (3) Show the message “Copying files from memory”
(Instop)
O After final inspection, press In-Stop key of the Adj. R/C and
check that the unit goes to Stand-by mode.
16-4. POWER Supply Unit PCB Ass'y Va/Vs

Voltage adjustment.
[ Caution ] (4) Updating is staring.
Both Vs and Va voltage adjustment are necessary.
(1) Model name: 50/60PK750-UA, 50/60PK950-UA

(2) Va/Vs Adjustment Procedure
1) Connect positive(+) terminal of DMM to Vs/Va pin,
connect negative(-) terminal to GND.
2) Turning ‘ Vs/Va ’ and adjust Vs/Va voltages to a value
which is written on a right/top label of a module.
( deviation ; ± 0.5V)
(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
[ Caution ] TV can lost all channel data. In this case, you have to
Each Power Supply Unit PCB assembly must be checked by channel recover. if all channel data is cleared, you didn’t
check JIG set. have a DTV/ATV test on production line.
(Because power PCB Ass’y damages to PDP Module, especially
be careful)
[Caution] * After downloading, have to adjust TOOL OPTION again.
Set up "RF mode(noise)" before a voltage adjustment.
(1) Push "IN-START" key in service remote controller.
(2) Select "Tool Option 1" and Push “OK” button.
(3) Punch in the number. (Each model has their number.)
17. USB Download (S/W Update, (4) Completed selecting Tool option.
*.epk File Download)

* After downloading, have to adjust TOOL OPTION again.
(1) Put the USB Stick to the USB socket 1. Push "IN-START" key in service remote controller.
2. Select "Tool Option 1" and Push “OK” button.
(2) Automatically detecting update file in USB Stick 3. Punch in the number. (Each model has their number.)
- If your downloaded program version in USB Stick is Low,
Model Tool Tool Tool Tool Tool Tool
it didn’t work.
But your downloaded version is High, USB data is Name Value 1 Value 2 Value 3 Value 4 Value 5 Value 6
automatically detecting 50PZ950-UA 32777 65 7519 7560 14929 857
60PZ950-UA 32781 65 7519 7560 14921 857
50PZ570-UG 32793 65 7519 7560 14921 857
60PZ570-UG 32797 65 7519 7560 14921 857
4. Completed selecting Tool option.
BLOCK DIAGRAM
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
400
601
604
520
240
910
602
209
200
590
208
900
206
201
580
205
501
303
301
204
207
A12
202
203
LV1
300
302
304
120
A24
A10
A23
560
A4
305
540
A2
570
- 14 - LGE Internal Use Only

Strap Setting
NAND FLASH MEMORY 8Gbit Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)

+3.3V_Normal
+3.3V_Normal +3.3V_Normal 0000: ST Micro M25P or compatible Serial Flash R154 R157 R160 R164 R167 R170 R175 R177 R179 R181 R183 R187 R192
TOSHIBA_8GBIT 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices OPT OPT OPT OPT OPT OPT OPT OPT OPT OPT
IC102
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
TC58DVG3S0ETA00
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
R113 R117 R122 R127 1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
10K 10K 10K 10K 1010: 8-bit 8Gbit, 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O) NAND_DATA[0]
NC_1 NC_28 OPT OPT 0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices CI_ADDR[7]
1 48 CI_ADDR[4] 0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices NAND_DATA[6]
NC_2 NC_27 NAND_DATA[7] 0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
2.7K
2 47 CI_ADDR[6]
NAND_DATA[2] 0111: 3B dual IO Serial Flash
NC_3 NC_26 1001: BB dual IO Serial Flash NAND_CLE
3 46 NAND_DATA[1] 1011: fast Serail Flash > 50Mhz
NAND_DATA[0-7] R114 R118 R123 R128 NAND_DATA[4]
NC_4 NC_25 10K 10K 10K 10K 1100: OneNAND Flash (always 16-bit)
4 45 CI_ADDR[9]
R107
OPT OPT 1110: Reserved

NC_5 I/O8 1101, 1111: Reserved CI_ADDR[11]
5 44 NAND_DATA[7]
OPT CI_ADDR[12]
R1900 0 NC_6 I/O7
6 43 NAND_DATA[6] CI_ADDR[13]
RY/BY I/O6 CI_ADDR[8]
NAND_RBb 7 42 NAND_DATA[5]
NAND_DATA[3]
RE I/O5
NAND_REb 8 41 NAND_DATA[4] NAND_DATA[5]
CE NC_24 +3.3V_Normal NAND ECC (FA3, FA2, FALE) R155 R158 R161 R165 R168 R171 R176 R178 R180 R182 R184 R188 R193
NAND_CEb 9 40 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
OPT OPT OPT OPT
OPT NC_7 PSL +3.3V_Normal
NAND_CEb2 0 10 39 0
C102
R1901 4700pF NC_8 NC_23 R1902
11 38 C104 10uF
10V
VCC_1 VCC_2 R111 R115 R119
C101 12 37 C103 10K 10K 10K
0.1uF OPT 000 = ECC disabled
VSS_1 VSS_2 0.1uF OPT NAND_DATA[0]:
13 36 CI_ADDR[3] 001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O) 0: System is LITTLE endian (O) CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
NC_9 NC_22 CI_ADDR[2] 1: System is BIG endian TVM Crystal oscillator bias/gain control
14 35 011 = ECC 8-bit BCH, 27 byte spare
NAND_ALE 100 = ECC 12-bit BCH, 27 byte spare 0000: 210uA
NC_10 NC_21 CI_ADDR[7]: 0001: 390uA
15 34 R112 R116 R120 101 = ECC 8-bit BCH, 16 byte spare
10K 10K 10K 110, 111 = Reservedd 0: Disable EDID automatic Downloading from Flash (O) 0010: 570uA
CLE NC_20 OPT 1: Enable EDID automatic Downloading from Flash 0011: 730uA
NAND_CLE 16 33
0100: 890uA (O)
ALE I/O4 NAND_DATA[6] : 0111: 1290uA
NAND_ALE 17 32 NAND_DATA[3]
0: Disable OSC clock output on chip Pin (O) 1000: 1416uA
WE I/O3 1: Enable OSC clock output on chip pin. 1111: 2196uA
NAND_WEb 18 31 NAND_DATA[2] 0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
+3.3V_Normal WP I/O2 CI_ADDR[6]:
Write Protection 19 30 NAND_DATA[1]
0: Host MIPS run at 500 MHz (O) CI_ADDR[8]:
NC_11 I/O1 1: Host MIPS run at 250 MHz 0: RESETOUTb (in On/Off only) stay asserted until software releases them.
- High : Normal Operation 20 29 NAND_DATA[0] 1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
R103
4.7K
- Low : Write Protection

OPT
NC_12 NC_19 NAND_CLE: at end of RESETb pulse (O)

21 28
M100 0: Differential Oscillators TVM not bypassed (O)
NC_13 NC_18 1: Differential Oscillators TVM bypassed NAND_DATA[3]:
22 27 MED62210801
FLASH_WP 0: MIPS will boot from external flash (O)
NC_14 NC_17 OPT NAND_DATA[4]: 1: MIPS will boot from ROM
23 26
0: 27MHz TVM Crystal Frequency
NC_15 NC_16 1: 54MHz TVM Crystal Frequency (O) NAND_DATA[5]:
24 25
0: FLASH MODE (0)
1: BSC_SLAVE(BBS) MODE
NVR_256K
+3.3V_Normal
NVRAM A0
IC103-*1
AT24C256C-SSHL-T
1 8
VCC
R151 A1 WP
10K +3.3V_Normal 2 7
RGB_DDC_SDA A2 SCL
S
B
D
3 6
+3.3V_Normal
GND SDA
4 5
IC101 IC101
LGE35230 LGE35230
Q101 NVR_1M
G
BSS83 NAND_DATA[0-7] C116
4.7K
4.7K
IC103
OPT
R173
R174
M24M01-HRMN6TP 0.1uF
C118
B5 AE27 0.1uF AG6 AB1 NVR_256K
HDMI_CLK- HDMI0_CLKN TXOUT0_L0N TXA0N NAND_DATA[7] R152
C5 AE28 16V 54MHz_XTAL_P TVM_XTALIN FAD_7
HDMI_CLK+ HDMI0_CLKP TXOUT0_L0P TXA0P AB3 NAND_DATA[6] 0 NC VCC
AF27 FAD_6 1 8 Write Protection
TXA1N AF6 AC1 NAND_DATA[5]
TXOUT0_L1N 54MHz_XTAL_N TVM_XTALOUT FAD_5 R169
A4 AF28 AC2
HDMI_RX0- HDMI0_D0N TXOUT0_L1P TXA1P NAND_DATA[4] 0 E1 WP - Low : Normal Operation
B4 AG27 FAD_4 2 7
+3.3V_Normal HDMI_RX0+ TXA2N AC3 NAND_DATA[3] A8’h - High : Write Protection
+5V_Normal HDMI0_D0P TXOUT0_L2N FAD_3
AG28 V5 AD2
TXOUT0_L2P TXA2P NAND_DATA[2] E2 SCL
+3.3V_Normal IRRXDA FAD_2 3 6 R190 33
A3 AE26 AD3 SCL3_3.3V
4.7K
HDMI_RX1- HDMI0_D1N TXCLK_LN TXACLKN NAND_DATA[1]
OPT
R172
B3 AF26 FAD_1
HDMI_RX1+ HDMI0_D1P TXCLK_LP TXACLKP AE2 NAND_DATA[0] VSS SDA
FAD_0 4 5 R191 33
AH27 AB4 SDA3_3.3V
TXOUT0_L3N TXA3N R198
A2 AG26 FP_IN0 C115 C117
HDMI_RX2- TXA3P 10K Y4
HDMI0_D2N TXOUT0_L3P RGB_DDC_SCL
4.7K
R197 8pF
4.7K
R101 B2 AF25 FP_IN1 8pF

4.7K AG1
S
B
D
4.7K HDMI_RX2+ TXA4N

R105
HDMI0_D2P TXOUT0_L4N OPT

R104
AE25 FALE NAND_ALE OPT

TXA4P AA4 AF1
TXOUT0_L4P SPARE_ADC1 FCEB_0 NAND_CEb
Y5 AC5
W2 SPARE_ADC2 FCEB_1 NAND_CEb2
CEC Q102 AE6
G
AH26 BSS83 FCEB_2

TXB0N AB2 AG5
TXOUT0_U0N FS_IN1 FCEB_3
V4 AG25 AB5
DDC0_SCL TXOUT0_U0P TXB0P C119
W4 AE24 0.1uF FS_IN2
DDC0_SDA TXOUT0_U1N TXB1N R149
AD24 16V 0
TXOUT0_U1P TXB1P AF3
NFWPB FLASH_WP
V3
V2
HDMI0_HTPLG_IN TXOUT0_U2N
AH25
AF24
TXB2N R133 OPT 33 U3
VGA_SDA FWE
AG2
NAND_WEb 54MHz X-TAL
TXB2P +3.3V_Normal R134 OPT 33 U2 AE3
HDMI0_HTPLG_OUT TXOUT0_U2P VGA_SCL FRD NAND_REb C113
AE23 AA5
TXCLK_UN TXBCLKN 12pF
R195 0 D13 AD23 FRDYB
HDMI_ARC TXBCLKP R185 0
HDMI0_ARC TXCLK_UP SUNNY_54MHz 54MHz_XTAL_N
E6 AG24 Y2
HDMI0_RESREF TXOUT0_U3N TXB3N R121 R126 R129 R131 BCM_RX 3 2
AF23 RDA
TXB3P +3.3V_Normal 2.2K 2.2K 2K 2K Y1 AF2 CI_ADDR[2-14] X-TAL_2 GND_1
R106 TXOUT0_U3P OPT BCM_TX TDA FA_0 NAND_CLE R189
AC22 AE1 4 1
3K TXOUT0_U4N TXB4N NAND_RBb GND_2 X-TAL_1 1M
AD22 P101 FA_1
TXB4P R135 33 AA3 AC4 CI_ADDR[2] 54MHz OPT
TXOUT0_U4P TJC2508-4A SDA0_3.3V BSCDATAA FA_2
R136 33 AA2 AD5 X101 R186 0
SCL0_3.3V BSCCLKA CI_ADDR[3] 54MHz_XTAL_P
FA_3
AD4 CI_ADDR[4] 12pF X101-*1
AG23 FA_4 C114 54MHz
VCC R137 0 H3 AE4 CI_ADDR[5] X-TAL_1 GND_2
TXOUT1_L0N SCL2_3.3V RDB/GPIO FA_5
AH23 1 C106 R109 R110 H2 AE5 1 4
TXOUT1_L0P 4.7uF 1.5K 1.5K R138 0 CI_ADDR[6]
AE22 SDA2_3.3V TDB/GPIO FA_6 GND_1 X-TAL_2
TXOUT1_L1N AD6 CI_ADDR[7] 2 3
AE21 SCL FA_7
2 H4 AH3 CI_ADDR[8] KDS_54MHz
TXOUT1_L1P BSC_S_SCL FA_8
AF22 H5 AF4
TXOUT1_L2N CI_ADDR[9]
AH22 OPT BSC_S_SDA FA_9
OPT OPT OPT AH4
TXOUT1_L2P SDA +3.3V_Normal CI_ADDR[10]
AG22 3 C110 FA_10
C107 C108 C109 AG4 CI_ADDR[11]
TXCLK1_LN 33pF FA_11
AF21 33pF 33pF 33pF
TXCLK1_LP 50V 50V R141 4.7K F25 NMIB
AF5 CI_ADDR[12]
AG21 GND 50V 50V FA_12
4 AG3 CI_ADDR[13] +3.3V_Normal
TXOUT1_L3N FA_13
AF20 W5 AH2
TXOUT1_L3P CI_ADDR[14]
AD21 POWER_CTRL FA_14
TXOUT1_L4N AH5
AC21 5V_HDMI_1 FA_15
R142 22 U5 R147 R150 R153 R156 R159 R162 R166
TXOUT1_L4P AON_HSYNC R146 10K
5V_HDMI_2 U4 1K 1K 1K 1K 1K 1K 1K P102
R143 OPT 22
BBS CONNECT FOR HDMI STANDARD 5V_HDMI_3 OPT
AON_VSYNC
AD15
OPT OPT OPT OPT OPT OPT OPT
/TRST
12505WS-10A00
1
OPT
CI_ADDR[5] R100 22
AG20 TRSTB
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO R144 22 W3 AF14 TDI
CI_ADDR[10] R102 22
TXOUT1_U0N AON_GPIO_36 TDI/GPIO
2
AH20 5V_HDMI_4 W1 AH14
R130 R145 OPT 22 R148 22
OPT
TDO
TXOUT1_U0P AON_GPIO_37 TDO
3
CI_ADDR[14]
AD19 2K OPT AD14 TMS
TXOUT1_U1N +3.3V_Normal TMS/GPIO
4
AE19 AB6 AG14 TCK
TXOUT1_U1P AON_RESETOUTB TCK/GPIO
5
AF19 Y6 AC16
TXOUT1_U2N R132 4.7K /RST
6
AH19 OPT TVM_BYPASS DINT/GPIO
DINT
TXOUT1_U2P R139 0
7
**JTAG OPT
AE18
TXCLK1_UN JTAG_RESET R163
VIO
8
AD18 Y3 AH7 1K
TXCLK1_UP +3.3V_Normal SOC_RESET RESETB
JTAG_RESET OPT
GND
9
R139, R147, R150, R153, R156, R159,
AG19 AVS_VFB
G24 AG7 GND
TXOUT1_U3N RESETOUTB AVS_VSENSE
10
AF18 AD7 11
R162, R163, R166, P102
TXOUT1_U3P R124 AVS_RESETB
AG18 1K J6 AF7 GND
TXOUT1_U4N TMODE AVS_NDRIVE_1
AF17 OPT W6 AH8
TXOUT1_U4P TESTEN AVS_PDRIVE_1
R125 +3.3V_Normal
1K
AC18 F7 C6
LT0VCAL_MONITOR C111 0.01uF
AH16 VDAC_VREG VDAC_1
E7 D7
GPIO_BL_ON C112 0.1uF VDAC_RBIAS VDAC_2
AG16 R108 12K
BL_PWM/GPIO R140
560
BCM REFRENCE is 562ohm 1%
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN & NAND FLASH 1 31
Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
+3.3V_Normal
POWER 2.5V
+2.5V_BCM35230 ADAC_AVDD25 CORE 0.9V
+2.5V_BCM35230 AADC_AVDD25
+0.9V_CORE HDMI_AVDD +0.9V_CORE USB_AVDD +0.9V_CORE VAFE2_DVDD
+0.9V_CORE L202 L205 L209
BLM18PG121SN1D BLM18PG121SN1D L214 L219
NVR_1M
BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D

C233 C204
R228
R238
R244
R246
R251
R253
R255
R257
6.3V 6.3V
OPT
OPT
OPT
OPT
OPT
NFM18PS105R0J NFM18PS105R0J C249 C253 C256 C258

1K
1K
1K
1K
1K
1K
1K
1K
C247 10uF 10uF 0.1uF 0.1uF C280 C284 C285 C288 C292 C296 C299
16V C261 C263 C267 C271 C274 22uF 22uF 4.7uF 0.1uF
IN OUT IN OUT 22uF 10uF 4.7uF 0.1uF 0.01uF 22uF 0.1uF 4.7uF 0.1uF
MODEL_OPT_0
GND GND
MODEL_OPT_1 R259 0
MODEL_OPT_1 /3D_ASIC_RESET
MODEL_OPT_2 R260 0
MODEL_OPT_3 REMOTE_SW_CTRL +2.5V_BCM35230 EPHY_VDD25 +2.5V_BCM35230
MODEL_OPT_3 +3.3V_Normal +0.9V_CORE PLL_AUD_AVDD +0.9V_CORE VAFE3_DVDD +0.9V_CORE PLL_MAIN_AVDD
C244 L203
6.3V BLM18PG121SN1D L210 L215 L217
MODEL_OPT_4 NFM18PS105R0J
BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_5 C251 C252 C255 C259 C260 C262 C266 C270 C272
C232 C234 C236 C238 IN OUT C248 10uF 4.7uF 10uF 4.7uF 0.1uF 0.01uF C277 C281
4.7uF 0.1uF 0.1uF 4.7uF 10uF 0.1uF 4.7uF 0.1uF C294 C297
MODEL_OPT_6 GND 16V 4.7uF 0.1uF C287 C290 4.7uF 0.1uF
4.7uF 0.1uF
NVR_256K
MODEL_OPT_7
R229
R239
R245
R247
R252
R254
R256
R258
OPT
OPT
1K
1K
1K
1K
1K
1K
1K
1K
+0.9V_CORE
+2.5V_BCM35230 VAFE2_VDD25
+0.9V_CORE PLL_MIPS_AVDD
L206 +0.9V_CORE PLL_VAFE_AVDD
C225 BLM18PG121SN1D L211 L218
C221 C223 BLM18PG121SN1D BLM18PG121SN1D
0.22uF 0.1uF 0.01uF
6.3V
C295 C298
C265 C269 C279 C282 4.7uF 0.1uF
MODEL OPTION 4.7uF 0.1uF 4.7uF 0.1uF
BCM
external
NO_FRC internal LG FRC2
URSA5 +1.5V_DDR
FRC
MODEL_OPT_0 0 0 1 1
+2.5V_BCM35230 VAFE3_VDD25 +2.5V_BCM35230 PLL_VAFE_AVDD25
MODEL_OPT_1 0 1 0 1
C203 C205 C207 C209 C211 C213 C215 C220 C222 L204 L207
BLM18PG121SN1D BLM18PG121SN1D
10uF 10uF 4.7uF 4.7uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF
C254 C257 C264 C268 POWER 3.3V
HIGH LOW C250
4.7uF 4.7uF 0.1uF 4.7uF 0.1uF
+3.3V_Normal USB_AVDD33 +3.3V_Normal HDMI_AVDD33
MODEL_OPT_4 DDR speed 1333 1600
L212 L216
MODEL_OPT_5 T2 Tuner Support Not Support BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_6 S Tuner Support Not Support IC101 C283

C291 C293
+0.9V_CORE 0.1uF
LGE35230 4.7uF 0.1uF
MODEL_OPT_7 PHM Enable Disable IC101 close to soc
LGE35230 0.1uF R231
C217 100 V12 K10
+3.3V_Normal
IF_P_MAIN VDDC_1 VSS_1
NON_CHB 1% V7 K11
R212 L201 VDDC_2 VSS_2
F26 C17 1K R232 M10 K12
EPHY_VREF VI_IFP0 0.1uF100 BLM18PG121SN1D VDDC_3 VSS_3 +3.3V_Normal VDAC_AVDD33
D26 B17 N10 L12
EPHY_RDAC VI_IFM0 IF_N_MAIN VDDC_4 VSS_4
D15 C218 1% P10 M12 L213
R211
6.04K VDDR_AGC VDDC_5 VSS_5 BLM18PG121SN1D
F27 R10 N12
EPHY_TDP EPHY_TDP closed to soc C229
F28 B16 VDDC_6 VSS_6
0.1uF T10 P12
EPHY_TDN EPHY_TDN AGC_SDM_2 VDDC_7 VSS_7 C286 C289
E27 A16 R213 2K U10 R12
EPHY_RDP EPHY_RDP AGC_SDM_1 IF_AGC_MAIN VDDC_8 VSS_8 4.7uF 0.1uF
E26 C216 0.01uF V10 T12
EPHY_RDN EPHY_RDN VDDC_9 VSS_9
A15 W10 U12
GPIO_0 VDDC_10 VSS_10
C16 +3.3V_Normal V13 W12
GPIO_1 VDDC_11 VSS_11
F5 G28 L11 K13
USB_MONCDR GPIO_2 VDDC_12 VSS_12
E5 G26 M11 L13
C201 USB_RREF GPIO_3 VDDC_13 VSS_13
R210 +3.3V_Normal R233 R234 N11 M13
100pF 4.87K 1.2K 1.2K VDDC_14 VSS_14
1% C2 R209 P11 N13
OPT USB_DM2 USB_PORT1DN 0 VDDC_15 VSS_15
USB_DP2
D1 W14 SDA1_3.3V R11 P13 IC101
USB_PORT1DP PCI_VIO_0 VDDC_16 VSS_16
W15
0
SCL1_3.3V T11 R13 LGE35230
PCI_VIO_1 R217 VDDC_17 VSS_17
E1 W13 C227 C231 U11 T13
/USB_OCD2 USB_PWRFLT_1/GPIO PCI_VIO_2 VDDC_18 VSS_18 AADC_AVDD25
D2 33pF 33pF V11 U13
USB_CTL2 USB_PWRON_1/GPIO 50V 50V VDDC_19 VSS_19
OPT OPT W11 W16 F19 F20
B1 J5 VDDC_20 VSS_20 ADAC_AVDD25 AADC_AVDD25 AADC_AVSS
V14 K14
USB_DM1 USB_PORT2DN GPIO_4 REMOTE_OR_MODULE_RX VDDC_21 VSS_21
C1 R5 R240 0 L18 L14 D25 G22
USB_DP1 USB_PORT2DP GPIO_5 MODEL_OPT_0 VDDC_22 VSS_22 ADACA_AVDD25 ADACA_AVSS
V6 R207 0 M18 M14 D24 G21
GPIO_6 DEMOD_RESET VDDC_23 VSS_23 ADACC_AVDD25 ADACC_AVSS
C3 H6 R204 0 N18 N14 E24 F22
/USB_OCD1 USB_PWRFLT_2/GPIO GPIO_7 M_RFModule_RESET VDDC_24 VSS_24 ADACD_AVDD25 ADACD_AVSS
C4 AE15 R214 0 P18 P14 EPHY_VDD25
USB_CTL1 USB_PWRON_2/GPIO GPIO_70 EPHY_LINK VDDC_25 VSS_25
AF15 R237 0 R18 R14 F24 F23
GPIO_71 EPHY_ACTIVITY VDDC_26 VSS_26 EPHY_BVDD25 EPHY_AVSS
AG15 T18 T14 E25
GPIO_72 3V3 VDDC_27 VSS_27 EPHY_AVDD25
M4 AF16 R215 22 U18 U14
TCLKA/GPIO GPIO_73 RF_SWITCH_CTL_2 VDDC_28 VSS_28
L5 AD16 R236 0 V18 K15
TDATA_0/GPIO GPIO_74 MODEL_OPT_1 VDDC_29 VSS_29 HDMI_AVDD
M5 AE16 R261 22 R208 W18 L15
TDATA_1/GPIO GPIO_75 MODEL_OPT_2 OPT 3.3K VDDC_30 VSS_30 HDMI_AVDD33
L6 AG17 R216 0 V15 M15 D5 F6
TDATA_2/GPIO GPIO_76 MODEL_OPT_3 VDDC_31 VSS_31 HDMI0_AVDD HDMI0_AVSS_1
N3 AH17 R250 0 L19 N15 D4 G6
TDATA_3/GPIO GPIO_77 L/R_INDICATOR VDDC_32 VSS_32 +2.5V_BCM35230 HDMI0_AVDD33 HDMI0_AVSS_2
N1 AE17 M19 P15
N2
TDATA_4/GPIO GPIO_78
AD17
TP200 V_Sync_Out N19
VDDC_33 VSS_33
R15 AE20 AB22
TDATA_5/GPIO GPIO_79 VDDC_34 VSS_34 LT0VDD25_1 LT0VSS_1
M3 R230 22 P19 T15 AD20 AB21
TDATA_6/GPIO VDDC_35 VSS_35 LT0VDD25_2 LT0VSS_2
M2 R19 U15 AC20 AB19
TDATA_7/GPIO VDDC_36 VSS_36 +2.5V_BCM35230 LT0VDD25_3 LT0VSS_3
L4 AB13 T19 K16 AB20 AC19
TSTRTA/GPIO PCI_AD05 VDDC_37 VSS_37 LT0VDD25_4 LT0VSS_4
N4 AC15 U19 L16 AB18
TVLDA/GPIO PCI_AD06 VDDC_38 VSS_38 LT0VSS_5
AB12 V19 M16 AB17
OPT PCI_AD07 C275
FE_TS_CLK K6 AB11 VDDC_39 VSS_39 LT0VSS_6
R203 0 W19 N16 0.1uF AC17
TCLKD/GPIO PCI_AD08 VDDC_40 VSS_40 LT0VSS_7
R200 0 J4 AE14 V16 P16
FE_TS_SERIAL TDATD_0/GPIO PCI_AD09/GPIO SC_DET/COMP2_DET +1.5V_DDR VDDC_41 VSS_41
CHBO_TS_CLK R241 KOR75 OPT K5 AG13
CHB_RESET Place Cap V17 R16 USB_AVDD D14 SPDIF_IN_AVDD25 F15
TDATD_1/GPIO PCI_AD10/GPIO R249 Very close to L22 Ball L220 VDDC_42 VSS_42
CHBO_TS_SERIAL R242 KOR75 J2 AH13 0 AMP_RESET_N T16 SPDIF_IN_AVSS
TDATD_2/GPIO PCI_AD11/GPIO MLG1005S22NJT VSS_43 USB_AVDD33
CHBO_TS_SYNC R243 KOR75 J3 AF13
TW9910_RESET
OPT OPT L10 U16 E4 G7
TDATD_3/GPIO PCI_AD12/GPIO POR_VDD VSS_44 USB_AVDD USB_AVSS_1
CHBO_TS_VAL_ERR R248 KOR75 K2 AE13
AV2_CVBS_DET C226 C228 K17 VDAC_AVDD33 D3 G8
OPT TDATD_4/GPIO PCI_AD13/GPIO VSS_45 USB_AVDD33 USB_AVSS_2
OPT K1 AD12 R218 22 1uF 0.1uF L17
C2000 C2001 C206 TDATD_5/GPIO PCI_AD14/GPIO RF_BOOSTER_CTL 25V VSS_46
C202 K3 AF12 16V L22 M17 D6 G9
100pF 100pF 100pF DSUB_DET VAFE2_DVDD
100pF TDATD_6/GPIO PCI_AD15/GPIO VDDR1_1 VSS_47 VDAC_AVDD33 VDAC_AVSS
Close to LG1140 50V 50V 50V L1 AG10 R219 0 AA28 N17
KOR 50V OPT TDATD_7/GPIO PCI_AD16/GPIO VAFE2_VDD25
KOR L3 AF10 VDDR1_2 VSS_48
R201 0 R220 22 V28 P17 D18 G20
FE_TS_SYN TSTRTD/GPIO PCI_AD17/GPIO MODEL_OPT_4 VDDR1_3 VSS_49 RGB/CVBS_EMI_Improve VAFE2_DVDD VAFE2_VSS_1
R202 0 L2 AE10 R28 R17 E17 E18
FE_TS_VAL TVLDD/GPIO PCI_AD18/GPIO DC_MREMOTE
AD10 VDDR1_4 VSS_50 VAFE2_AVDD25_1 VAFE2_VSS_2
OPT M28 T17 C219 OPT D16 G18
PCI_AD19/GPIO DD_MREMOTE VDDR1_5 VSS_51 OPT VAFE2_AVDD25_2 VAFE2_VSS_3
AE9 J28 U17 390pF C224 D17 G17
R221 0 OPT VAFE3_DVDD
PCI_AD20/GPIO VDDR1_6 VSS_52 50V 390pF VAFE2_DVDD25 VAFE2_VSS_4
Close to Main SoC P4 AE8 R222 0 OPT K23 W17 F18
MPEG_CLK/GPIO PCI_AD21/GPIO VDDR1_7 VSS_53 50V VAFE3_VDD25 VAFE2_VSS_5
T2 AC10 M22 K18 D9 G16
MPEG_D_0/GPIO PCI_AD22 VDDR1_8 VSS_54 VAFE3_DVDD VAFE2_VSS_6
R3 AC11 T22 K19 D8 F16
MPEG_D_1/GPIO PCI_AD23 VDDR1_9 VSS_55 C208 VAFE3_AVDD25_1 VAFE2_VSS_7
R2 AC8 T23 H7 E8
MPEG_D_2/GPIO PCI_AD24 VDDR1_10 VSS_56 390pF C214 VAFE3_AVDD25_2
P3 AB8 very close U22 G14 50V F9 G13
MPEG_D_3/GPIO PCI_AD25 VDDR1_11 VSS_57 390pF VAFE3_AVDD25_3 VAFE3_VSS_1
P2 to SOC R22 pin Y22 AB16 E9 G12
50V
MPEG_D_4/GPIO VDDR1_12 VSS_58 VAFE3_DVDD25 VAFE3_VSS_2
P1 AC14 C242 R7 F8 F12
MPEG_D_5/GPIO PCI_CBE00 0.1uF VSS_59 POR_VDD25 VAFE3_VSS_3
R6 AG12 R22 M6 PLL_AUD_AVDD G11
MPEG_D_6/GPIO PCI_CBE01/GPIO COMP1_DET DDR_LDO_VDDO VSS_60 VAFE3_VSS_4
N5 AH10 R262 22 AB23 G10
MPEG_D_7/GPIO PCI_CBE02/GPIO MODEL_OPT_5 VSS_61 PLL_MAIN_AVDD VAFE3_VSS_5
T4 AB7 +3.3V_Normal P7 G25 F10
MPEG_SYNC/GPIO PCI_CBE03 VSS_62 PLL_MIPS_AVDD PLL_AUD_AVDD VAFE3_VSS_6
P5 G15 W7 RGB_EMI_Improve K4
MPEG_DATA_EN/GPIO VDDR3_1 VSS_63 PLL_VAFE_AVDD PLL_MAIN_AVDD
AG11 R223 0 H22 J7 AD25
PCI_DEVSELB/GPIO 3D_GPIO_0 VDDR3_2 VSS_64 PLL_MIPS_AVDD
AD11 R263 22 G23 N7 PLL_VAFE_AVDD25 D11 AD26
PCI_FRAMEB/GPIO MODEL_OPT_6 VDDR3_3 VSS_65 PLL_MIPS_AVSS
R287 0 R4 AE11 AB9 AB10 C212 D12 PLL_VAFE_AVDD
PDP_MODEL_OPT_2 R224 22 MODEL_OPT_7 +0.9V_CORE
MCIF_RESET/GPIO PCI_IRDYB/GPIO VDDR3_4 VSS_66 C210 390pF PLL_VAFE_AVDD25
R288 0 U1 AD13 R205 0 K7 AC23
PDP_MODEL_OPT_3 MCIF_SCLK/GPIO PCI_PAR/GPIO PDP_MODEL_OPT_0 L208 390pF 50V
T3 AE12 VDDR3_5 VSS_67 BLM18PG121SN1D
R235 0 AB15 AC6 50V AE7 AC7
MCIF_SCTL/GPIO PCI_PERRB/GPIO PDP_MODEL_OPT_1 VDDR3_6 VSS_68 TVM_OSC_AVDD TVM_OSC_AVSS
T1 AC12 R225 0 OPT L7 G19
+3.3V_Normal MCIF_SDI/GPIO PCI_REQ1B C273 C276 +3.3V_Normal
T5 AC13 VDDR3_7 VSS_69
R226 22 AB14 AA22 0.1uF 0.01uF U6
MCIF_SDO/GPIO PCI_SERRB/GPIO RF_SWITCH_CTL VDDR3_8 VSS_70 AUX_AVDD33
AH11 R206 0 M7 J23
PCI_STOPB/GPIO 3D_GPIO_1 VDDR3_9 VSS_71
AF11 R227 0 N6 J22
PCI_TRDYB/GPIO 3D_GPIO_2 VDDR3_10 VSS_72
P6 K22 C278
VDDR3_11 VSS_73 0.1uF
+0.9V_CORE J25
DVR_READY
RF_Emitter
VSS_74
N22
1K
R289
1K
R290
VSS_75
OPT
OPT
1K
R293
1K
R295
+3.3V_Normal AA6 N23

AON_VDDC_1 VSS_76
AA7 M25
AON_VDDC_2 VSS_77
Y7 P22
PDP_MODEL_OPT_0 AON_POR_VDD VSS_78
R25
PDP_MODEL_OPT_1 VSS_79
U7 V22
AON_VDDR3 VSS_80
W22
NON_RF_Emitter
PDP_MODEL_OPT_2
VSS_81
NON_DVR_READY
T7 W23
PDP_MODEL_OPT_3 AON_VDDR10_1 VSS_82
T6 V25
AON_VDDR10_2 VSS_83
AA25
R291
1K
1K
VSS_84
1K
R292
R294
1K
R296
HIGH LOW
MODEL_OPT_0 DVR READY Support Not Support
MODEL_OPT_1 MOTION R/C Support Not Support
MODEL_OPT_2
MODEL_OPT_3

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 2 31
MAIN POWER

IC101
C320 0.1uF LGE35230
DSUB_R+
INCM_R C321 0.1uF
R311 DSUB_G+ C327 0.1uF
36 C328 0.1uF B6
INCM_G VI_R
R317 A6
36 VI_INCM_R
C7
VI_G
A7
VI_INCM_G
C322 0.1uF B7
DSUB_B+ VI_B
C323 0.1uF C8
INCM_B VI_INCM_B
R312
36 C13
DSUB_HSYNC HSYNC_IN
A13
DSUB_VSYNC VSYNC_IN
C329 0.1uF C9
COMP1_Y VI_Y1
COMP1_Pr C330 0.1uF A9
VI_PR1
VIDEO INCM
C331 0.1uF B9
COMP1_Pb VI_PB1
C332 0.1uF B8
INCM_VID_COMP1 VI_INCM_COMP1
R310
0 C11
C333 0.1uF Run Along DSUB_R Trace
SC_R/COMP2_Pr
A10
VI_SC_R1 Near P801 INCM_R
SC_G/COMP2_Y C334 0.1uF
VI_SC_G1
C335 0.1uF B10 Run Along DSUB_G Trace
SC_B/COMP2_Pb
C10
VI_SC_B1 Near P801 INCM_G
INCM_VID_SC/COMP2 C336 0.1uF
VI_INCM_SC1
R318 Run Along DSUB_B Trace
0 D10 Near P801 INCM_B
VI_FB_1/GPIO
F13 Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
VI_FS1 Near JK1101 INCM_VID_COMP1
A12 Run Along AV2_CVBS Trace
C12
VI_SC_R2 Near JK1104 INCM_VID_AV2
VI_SC_G2
B12 Run Along TUNER_CVBS_IF_P Trace
B11
VI_SC_B2 Near TU2101/2
TU2201/2/3
INCM_TUNER
VI_INCM_SC2
Run Along AV1_CVBS Trace
E12 Near JK1102 INCM_VID_AV1
VI_FB_2/GPIO
E14 JK1103 Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace
VI_FS2 Near INCM_VID_SC/COMP2
JK2501
E15
VI_L1
F17
VI_C1_1
E16
VI_INCM_LC1_1
F14
VI_C1_2
E11
C303 0.1uF VI_INCM_LC1_2
AV2_CVBS_IN
INCM_VID_AV2 C304 0.1uF C18
R303 R331 0 VI_CVBS1
36 C325 0.1uF B18
VI_INCM_CVBS1
TU_CVBS C326 0.1uF A18
INCM_TUNER VI_CVBS2
1/10W R306 R316 C19
OPT 75 36 VI_INCM_CVBS2
1% A19
VI_CVBS3
B19
VI_INCM_CVBS3
C317 0.1uF C20
AV1_CVBS_IN VI_CVBS4
C318 0.1uF B20
INCM_VID_AV1 VI_INCM_CVBS4
R304 +2.5V_BCM35230
36 E19
VI_SIF1_1
D19
R313 VI_INCM_SIF1_1
10K E10
VI_SIF1_2
C319 0.1uF F11
TU_SIF VI_INCM_SIF1_2
R305 R314 +2.5V_BCM35230
240 12K
OPT
R319
10K
OPT
INCM_SIF C324 0.1uF
R315 R320
120 12K
OPT OPT
IC101
LGE35230
B15 AF8
SPDIF_INC_P I2SSCK_OUTA/GPIO AUD_SCK
C15 AF9
+3.3V_Normal SPDIF_INC_N I2SWS_OUTA/GPIO AUD_LRCK +3.3V_Normal
AG9
I2SSD_OUTA0/GPIO AUD_LRCH
C14 AC9
SPDIF_IND_P I2SSOSCK_OUTA/GPIO AUD_MASTER_CLK
B14 AD8
SPDIF_IND_N I2SSD_OUTA1/GPIO TU_RESET_SUB
R301 R302 AD9 R329 R330
2.2K 2.2K I2SSD_OUTA2/GPIO 1.2K 1.2K
REMOTE_OR_MODULE_TXR307 0 G4
I2SSCK_IN/GPIO
R308 0 F4 E2 R325 33
SCL3_3.3V I2SWS_IN I2SSCK_OUTC/GPIO MOD_SCL
R309 0 G5 F2 R326 33
SDA3_3.3V I2SSD_IN/GPIO I2SWS_OUTC/GPIO MOD_SDA
C301 C302 E3 C339 C340
I2SSD_OUTC/GPIO TU_RESET
33pF 33pF F3 R328 0 33pF 33pF
50V 50V I2SSOSCK_OUTC/GPIO AV1_CVBS_DET 50V 50V
OPT OPT C305 1uF 10V C25
AV1_L_IN AADC_LINE_L1 OPT OPT
B24 G2 R332 0
AV1_R_IN C306 1uF 10V
AADC_LINE_R1 I2SSCK_OUTD/GPIO 0
C307 1uF 10V A24 G3 R333
INCM_AUD_AV1 AADC_INCM1 I2SWS_OUTD/GPIO
I2SSD_OUTD/GPIO
G1 AUDIO INCM
C308 1uF 10V E22 H1
PC_L_IN AADC_LINE_L2 I2SSOSCK_OUTD/GPIO
C309 1uF 10V E23
PC_R_IN AADC_LINE_R2 R300 5.1 INCM_AUD_COMP1
C310 1uF 10V D23
INCM_AUD_PC AADC_INCM2
B13 Route Between AV1_L_IN & AV1_R_IN Trace
C24
SPDIF_OUTA/GPIO SPDIF_OUT Near JK1102 R321 5.1 INCM_AUD_AV1
SC/COMP2_L_IN C311 1uF 10V
AADC_LINE_L3
C312 1uF 10V C23 AG8 Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
SC/COMP2_R_IN AADC_LINE_R3 AUDMUTE_0/GPIO Near JK1103 R322 5.1
B23 E13 INCM_AUD_SC/COMP2
C313 1uF 10V JK2501
INCM_AUD_SC/COMP2 AADC_INCM3 AUDMUTE_1
R323 5.1 Route Between AV2_L_IN & AV2_R_IN Trace
E21 C28 Near JK1104 INCM_AUD_AV2
AV2_L_IN C314 1uF 10V
AADC_LINE_L4 ADAC_AL_N
C315 1uF 10V D21 C27 Route Between PC_L_IN & PC_R_IN Trace
AV2_R_IN
D22
AADC_LINE_R4 ADAC_AL_P Near JK801 R324 5.1 INCM_AUD_PC
INCM_AUD_AV2 C316 1uF 10V
AADC_INCM4
D28
ADAC_AR_N
C300 1uF 10V B22 D27
COMP1_L_IN AADC_LINE_L5 ADAC_AR_P
C337 1uF 10V C22
COMP1_R_IN AADC_LINE_R5
A22 C26
INCM_AUD_COMP1 C338 1uF 10V
AADC_INCM5 ADAC_CL_N Near TU2101/2
TU2201/2/3
Route Along With TUNER_SIF_IF_N
INCM_SIF
A27
ADAC_CL_P
F21
AADC_LINE_L6
D20 B27
AADC_LINE_R6 ADAC_CR_N
E20 B28
AADC_INCM6 ADAC_CR_P
A21 B25
AADC_LINE_L7 ADAC_DL_N
C21 A25
AADC_LINE_R7 ADAC_DL_P
B21
AADC_INCM7
A26
ADAC_DR_N
B26
ADAC_DR_P

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN AUDIO/VIDEO 3 31

DDR STRAP DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
JEDEC Types : DDR_DQ[0:4]

R401 R403 R405 R407 R409
4.7K 4.7K 4.7K 4.7K 4.7K 00001 : DDR3-1333H (CasL=9)
OPT 10101 : DDR3-1600K (CasL=11) (O)
+1.5V_DDR +1.5V_DDR
NFM18PS105R0J
NFM18PS105R0J
C410 C432
6.3V 6.3V
DDR_DQ[10] C403 C405 C407 C417 C421 C423 C425

2.2uF 10uF 2.2uF IN OUT 470pF 2.2uF 10uF 10uF IN OUT
DDR_DQ[9]
DDR_DQ[7] GND GND
DDR_DQ[8]
DDR_DQ[6]
DDR_DQ[5]
+1.5V_DDR +1.5V_DDR
NFM18PS105R0J NFM18PS105R0J
C402 C433
R402 R432 R404 R406 R408 R410 Bus Width : DDR_DQ[10:9] +1.5V_DDR 6.3V 6.3V
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 0 - 16b
OPT OPT OPT OPT 1 - 32b (O) C412 C426
HYNIX_DDR DDR Voltage : DDR_DQ[7] IN OUT 1uF IN OUT 1uF
0 - 1.35V for DDR3 GND GND
1 - 1.5V for DDR3 (O)
Chip Width : DDR_DQ[8] C455
C453 C454
0 - 8b 1uF
1uF 1uF
1 - 16b (O) 6.3V
6.3V 6.3V
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
10 - 1Gbit
11 - 512Mbit
+1.5V_DDR
+1.5V_DDR +1.5V_DDR
IC401 IC402
R422 R430
K4B2G1646C R416 K4B2G1646C 4.99K 4.7K
4.99K 1% OPT
1% R429
82
DDR_RESETb
N3 M8 N3 M8 R423
DDR_AA0 A0 C415 R417 DDR_AA0 A0 VREFCA C435 4.99K C442
IC101 VREFCA 4.99K P7
P7 0.01uF 1% DDR_AA1 A1 0.01uF 1% 100pF
LGE35230 DDR_AA1 A1 P3
P3 DDR_AA2 A2
DDR_AA2 A2 N2 H1 R428
DDR_DQ[0-7] N2 H1 DDR_AA3 A3 DDR_VREFA 82
DDR_AA3 A3 VREFDQ DDR_VREFA VREFDQ C436
P8 C416 P8 DDR_CKE
DDR01_AA4 0.01uF DDR23_AA4 A4 0.01uF C437 R431
U26 V23 A4 P2
DDR_DQ[0] DDR_DQA_0 DDR_AA0 P2 DDR23_AA5 100pF 4.7K
DDR_ADA_0 DDR01_AA5 A5 A5 OPT
DDR_DQ[1] R26 AB27 R8 L8 R8 L8 R421 240
DDR_DQA_1 DDR_ADA_1 DDR_AA1 DDR01_AA6 R415 240 DDR23_AA6 A6 ZQ
U27 Y23 A6 ZQ R2
DDR_DQ[2] DDR_DQA_2 DDR_AA2 R2 1% +1.5V_DDR DDR_AA7 1% +1.5V_DDR
DDR_ADA_2 DDR_AA7 A7 A7
DDR_DQ[3] R27 Y26 T8 T8
DDR_DQA_3 DDR_ADA_3 DDR_AA3 DDR_AA8 A8 DDR_AA8 A8
DDR_DQ[4] V27 R3 B2 R3 B2
DDR_DQA_4 DDR_AA9 A9 VDD_1 DDR_AA9 A9 VDD_1 DDR_AA13 R424 56
DDR_DQ[5] P26 AB26 L7 D9 L7 D9
DDR_DQA_5 DDR_ADA_4 DDR01_AA4 DDR_AA10 DDR_AA10 A10/AP VDD_2 DDR_AA14 R425 56 OPT
U25 Y24 A10/AP VDD_2 R7 G7
DDR_DQ[8-15] DDR_DQ[6] DDR01_AA5 R7 G7 DDR_AA11 C438 1uF
DDR_DQA_6 DDR_ADA_5 DDR_AA11 A11 VDD_3 A11 VDD_3
DDR_DQ[7] P27 AC26 N7 K2 N7 K2 AR401 56
DDR_DQA_7 DDR_ADA_6 DDR01_AA6 DDR_AA12 DDR_AA12 A12/BC VDD_4 DDR_AA2
R24 A12/BC VDD_4 T3 K8
DDR_DQ[8] T3 K8 DDR_AA13 C404 0.1uF
DDR_DQA_8 DDR_AA13 A13 VDD_5 A13 VDD_5 DDR_AA11
DDR_DQ[9] N24 AB24 N1 N1
DDR_DQA_9 DDR_ADA_ALT_4 DDR23_AA4 VDD_6 VDD_6 DDR_AA3
DDR_DQ[10] T25 AC25 M7 N9 M7 N9
DDR_DQA_10 DDR_ADA_ALT_5 DDR23_AA5 NC_5 VDD_7 DDR_AA7 C406 0.1uF
M23 AC24 NC_5 VDD_7 R1
DDR_DQ[11] DDR23_AA6 R1 AR402 56
DDR_DQA_11 DDR_ADA_ALT_6 VDD_8 VDD_8
DDR_DQ[12] R23 M2 R9 M2 R9
DDR_DQA_12 DDR_BAA0 BA0 VDD_9 DDR_BAA0 BA0 VDD_9 DDR_AA9
DDR_DQ[13] N25 AB25 N8 N8 C450 0.1uF
DDR_DQA_13 DDR_ADA_7 DDR_AA7 DDR_BAA1 BA1 DDR_BAA1 BA1 DDR_AA8
DDR_DQ[14] T24 AD28 M3 M3
DDR_DQ[16-23] DDR_DQA_14 DDR_ADA_8 DDR_AA8 DDR_BAA2 BA2 C408 0.1uF
N26 Y25 DDR_BAA2 BA2 A1 DDR_AA0
DDR_DQ[15] DDR_AA9 A1 AR403 56
DDR_DQA_15 DDR_ADA_9 VDDQ_1 VDDQ_1 DDR_AA1
DDR_DQ[16] L26 AA27 J7 A8 J7 A8 C439
DDR_DQA_16 DDR_ADA_10 DDR_AA10 DDR01_CLK DDR23_CLK CK VDDQ_2 DDR_BAA0 1uF
H27 AC27 CK VDDQ_2 K7 C1
DDR_DQ[17] DDR_AA11 K7 C1 DDR23_CLKb
DDR_DQA_17 DDR_ADA_11 DDR01_CLKb CK VDDQ_3 CK VDDQ_3 DDR_BAA2
DDR_DQ[18] L27 AA26 K9 C9 K9 C9
DDR_DQA_18 DDR_ADA_12 DDR_AA12 DDR_CKE R418 R419 DDR_CKE CKE VDDQ_4 DDR_BAA1 C409 0.1uF
J26 AA24 R412 R413 CKE VDDQ_4 D2
DDR_DQ[19] DDR_AA13 56 56 D2 56 56 AR404 56
DDR_DQA_19 DDR_ADA_13 VDDQ_5 1% 1% VDDQ_5 DDR_AA10
DDR_DQ[20] M27 AD27 1% 1% +1.5V_DDR L2 E9 +1.5V_DDR L2 E9 C451 0.1uF
DDR_DQA_20 DDR_ADA_14 DDR_AA14 CS VDDQ_6 DDR_AA12
G27 CS VDDQ_6 K1 F1
DDR_DQ[21] R414 10K K1 F1 C419 R420 10K
DDR_DQA_21 C401 ODT VDDQ_7 ODT VDDQ_7 DDR_WEb
DDR_DQ[22] M26 Y27 J3 H2 1000pF J3 H2
DDR_DQ[24-31] DDR_DQA_22 DDR_BAA_0 DDR_BAA0 1000pF DDR_RASb RAS VDDQ_8 C411 0.1uF
H26 AB28 DDR_RASb RAS VDDQ_8 K3 H9
DDR_DQ[23] DDR_BAA1 K3 H9 DDR_CASb CAS AR405 56
DDR_DQA_23 DDR_BAA_1 DDR_CASb CAS VDDQ_9 VDDQ_9 DDR23_AA6
DDR_DQ[24] L23 W24 L3 L3 C440
DDR_DQA_24 DDR_BAA_2 DDR_BAA2 DDR_WEb DDR_WEb WE DDR23_AA4 1uF
H25 WE J1
DDR_DQ[25] J1
DDR_DQA_25 NC_1 NC_1 DDR23_AA5
DDR_DQ[26] L24 V24 T2 J9 T2 J9
DDR_DQA_26 DDR_RASA_N DDR_RASb DDR_RESETb RESET DDR_RESETb RESET NC_2
J24 W25 NC_2 L1
DDR_DQ[27] DDR_CASb L1 AR406 56 C452 0.1uF
DDR_DQA_27 DDR_CASA_N NC_3 NC_3 DDR01_AA6
DDR_DQ[28] M24 V26 L9 L9
DDR_DQA_28 DDR_WEA_N DDR_WEb NC_4 DDR01_AA4
H23 NC_4 F3 T7
DDR_DQ[29] F3 T7 DDR_QS2 DDR_AA14
DDR_DQA_29 DDR_QS0 DQSL NC_6 DDR_AA14 DQSL NC_6 DDR01_AA5
DDR_DQ[30] L25 U24 G3 G3
DDR_DQA_30 DDR_CKEA DDR_CKE DDR_QS0b DDR_QS2b DQSL R426 56
H24 DQSL DDR_CASb
DDR_DQ[31]
DDR_DQA_31 R427 56 C441 1uF
W27 C7 A9 C7 A9 DDR_RASb
DDR_DM[0-3] DDR_CKA01_P DDR01_CLK DDR_QS1 DDR_QS3 DQSU VSS_1
W28 DQSU VSS_1 B7 B3
DDR01_CLKb B7 B3 DDR_QS3b DQSU
DDR_CKA01_N DDR_QS1b DQSU VSS_2 VSS_2
DDR_DM[0] T26 E1 E1
DDR_DMA_0 VSS_3 VSS_3
DDR_DM[1] P25 N28 E7 G8 E7 G8
DDR_DMA_1 DDR_CKA23_P DDR23_CLK DDR_DM[0] DML VSS_4 DDR_DM[2] DML VSS_4
DDR_DM[2] J27 N27 D3 J2 D3 J2
DDR_DMA_2 DDR_CKA23_N DDR23_CLKb DDR_DQ[0-7] DDR_DM[1] DDR_DQ[16-23] DDR_DM[3] DMU VSS_5
K24 DMU VSS_5 J8
DDR_DM[3] J8
DDR_DMA_3 VSS_6 VSS_6
U23 E3 M1 DDR_DQ[16] E3 M1
DDR_VREFA DDR_VREFA DDR_DQ[0] DQL0 VSS_7
DQL0 VSS_7 F7 M9
DDR_DQ[1] F7 M9 DDR_DQ[17] DQL1
DQL1 VSS_8 VSS_8
T27 AA23 F2 P1 DDR_DQ[18] F2 P1
DDR_QS0 DDR_DQSA_P_0 DDR_RST_N DDR_RESETb DDR_DQ[2] DQL2 VSS_9
T28 DQL2 VSS_9 F8 P9
DDR_QS0b DDR_DQ[3] F8 P9 DDR_DQ[19]
DDR_DQSA_N_0 DQL3 VSS_10 DQL3 VSS_10
W26 R411 240 H3 T1 DDR_DQ[20] H3 T1
DDR_ZQ DDR_DQ[4] DQL4 VSS_11
P24 DQL4 VSS_11 H8 T9
DDR_QS1 1% DDR_DQ[5] H8 T9 DDR_DQ[21]
DDR_DQSA_P_1 DQL5 VSS_12 DQL5 VSS_12
P23 G2 DDR_DQ[22] G2
DDR_QS1b DDR_DQSA_N_1 DDR_DQ[6] DQL6
DQL6 H7
DDR_DQ[7] H7 DDR_DQ[24-31] DDR_DQ[23]
DDR_DQ[8-15] DQL7 DQL7
K27 B1 B1
DDR_QS2 DDR_DQSA_P_2 VSSQ_1 VSSQ_1
K28 D7 B9 DDR_DQ[24] D7 B9
DDR_QS2b DDR_DQSA_N_2 DDR_DQ[8] DQU0 VSSQ_2
DQU0 VSSQ_2 C3 D1
DDR_DQ[14] C3 D1 DDR_DQ[30]
DQU1 VSSQ_3 DQU1 VSSQ_3
K25 C8 D8 DDR_DQ[29] C8 D8
DDR_QS3 DDR_DQSA_P_3 DDR_DQ[13] DQU2 VSSQ_4
K26 DQU2 VSSQ_4 C2 E2
DDR_QS3b DDR_DQ[12] C2 E2 DDR_DQ[28]
DDR_DQSA_N_3 DQU3 VSSQ_5 DQU3 VSSQ_5
A7 E8 DDR_DQ[25] A7 E8
DDR_DQ[9] DQU4 VSSQ_6
DQU4 VSSQ_6 A2 F9
DDR_DQ[10] A2 F9 DDR_DQ[26]
DQU5
DQU5 VSSQ_7 VSSQ_7
B8 G1 DDR_DQ[31] B8 G1
DDR_DQ[15] DQU6 VSSQ_8
DQU6 VSSQ_8 A3 G9
DDR_DQ[11] A3 G9 DDR_DQ[27]
DQU7
DQU7 VSSQ_9 VSSQ_9

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR 4 31

P500
SMAW200-H18S1 CURRENT: MAX 3A
L503 P_17V
0LCML00003B
MLB-201209-0120P-N2
P_+5V +5V_Normal
P_+5V
CURRENT: MAX 6A
L501
EAM38058401
1
3
5
2
4
6 C526 C527
Stand-by (5VST --> +3.3V)
MAX 1A CB4532UK121E +3.3V_Normal
0 R516 0.1uF 33uF
7 8 50V 25V
9 10
OPT
C508 C512 C514 11 12 R518
10uF 100uF 0.1uF 10K +5V_ST
L514 6.3V 16V 16V 13 14 CURRENT: MAX 3A
CB3216PA501E
OPT L504 PSU_ERR_DET
EAM44020101
BLM18PG121SN1D 15 16 +5V_ST +3.3V_ST
+5V_USB 17 18 0LCML00003B
+5V_ST MLB-201209-0120P-N2
IC503
MAX 1.9A OPT EAN58801701
L507
19
R512 C521 C528 C529 AP2121N-3.3TRE1
10K R514 0.1uF 10uF 100uF
100 16V 6.3V 16V VIN 3 2 VOUT
L513 RL_ON OPT
BLM18PG121SN1D OPT R517 1
R513 R515 100
10K 100 AC_DET C531 C534 GND C535 C541
MOD_ON 47uF 0.1uF 10uF 0.1uF
C520 16V 16V 6.3V 16V
0.1uF
16V
+1.5V_DDR +3.3V_NORMAL
+5V_Normal
POWER_ON/OFF2_2
+1.5V_DDR
+3.3V_NORMAL
R550
2K
R524
0.1uF
C584
OPT
16V
0
P_+5V
R541
IC504
0
R551 R554
AZ1085S-ADJTR/E1
0 22
EP[GND]
+3.3V_Normal
C587
VIN_3
PWRGD
INPUT 3 2 OUTPUT
BOOT
0.1uF 3V3
50V
EN
1 L518
ADJ/GND MLB-201209-0120P-N2 L519
16
15
14
13
R523
R536 C505 C516 3.6uH
0
C533 22uF 16V VIN_1 1 12 PH_3
1% 100uF 10V 0.1uF THERMAL
R534
C503 1K 16V VIN_2 PH_2 1/10W

150
2 11
1%
10uF 17 5%
10V R1 GND_1 PH_1
3 IC505 10 C588 C589 C590 C591 R1
R2 SN1007054RTER 22uF 22uF 22uF 100pF
GND_2 SS 16V 16V 16V
R535
4 9 50V C592
75
1%
1%
51K
R555
OPT 0.1uF C509 C510
0.01uF
C582 C583 16V 22uF 0.1uF
C586
22uF 0.1uF 10V 16V
16V 50V
AGND
VSENSE
COMP
RT/CLK
V0 = 1.25(1+R2/R1)
R552 R553
13K 330K
R556
1%
16K
C585
3300pF R2
50V
Vout=Vref*(1+R1/R2)|Vref=3.35V
*MUST BE OPTIMAZE COMP (10.08.16)
+2.5V_BCM35230
+0.9V_CORE_BCM35230(AOZ1038PI) +2.5V_BCM35230
Max 960 mA
P_+5V IC502
AZ1085S-ADJTR/E1 L508
MAX 4000 mA 0LCML00003B
INPUT OUTPUT MLB-201209-0120P-N2
3 2
1 OPT
OPT
ADJ/GND R521 C536 C537
+0.9V_CORE
C530 C532 1K 10uF 0.1uF C539 C542
100uF 100uF C544
10uF 0.1uF 6.3V 16V 100uF
R519
16V
MLB-201209-0120P-N2
16V
910
P_+5V 1%
6.3V 16V
1%
R1
16V
L505 R2
1%
IC501 2uH
R520
66.5
*NOTE 17 V0 = 1.25(1+R2/R1)
AOZ1038PI [EP]LX
L502
PGND NC_2
R545
1 8 OPT
5%
Placed on SMD-TOP OPT

THERMAL
R542 0 C517 C518 C519 C522 C523 C524

VIN NC_1 C525
9
10uF 10uF 10uF

0
10uF 10uF
1000pF
2 7
10uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V OPT
C515
R546
AGND EN
50V
50V
1%
3 6
R543 3300pF R1
+5V_TU
2K
16K
C506
10uF
C507
10uF
C511
FB
4
5A 5
COMP
0.1uF
16V 16V
50V
OPT +5V_TU
R547
OPT
10K
1%
R544
4.7K R2
0.1uF
C513
10K
OPT
16V
R540
IC506
+7V AZ1117BH-ADJTRE1
L511
22.0uH R539
INPUT ADJ/GND 330
3 1
POWER_ON/OFF2_2
R531 2 1/10W
10K C564 C565
1%
1/10W
C551 D500 C556 C559 C561 1% 22uF 0.1uF OUTPUT
R537
0.1uF IC500 MBRA340T3G 10uF 10uF 10uF
110
50V 40V 10V 10V 10V 10V 16V
1%
TPS54231D OPT
R1
R538
P_17V 1.2K 0
Switching freq: 555K BOOT PH 1%
1 8 R532
1/10W
5% C566
R533
VIN GND 100uF
75
2 7 16V
C555
820pF
R526 50V R2
C545 C547 C549 16K EN COMP C558
4.7uF 4.7uF 0.01uF 3 2A 6 47pF
50V 50V 50V R530 50V
27K
1%
SS VSENSE
R527 4 5
3.6K
C552
0.015uF
50V
6ms R529 0

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 5 31

FLMD0
GND
10Mhz Crystal
+5V_Normal
100K
R638
C600 C602 R639
13pF 13pF MICOM_DOWNLOAD
0
L600
OPT
BLM18PG121SN1D
P602 X600
OPT 12507WS-04L 10MHz
+3.3V_Normal
C605 C606
1
WIRELESS_PWR_EN
15pF 15pF
50V 50V
WIRELESS_DET
R680
KDS +3.3V_ST +3.3V_ST
MICOM_RESET
OPT
2 4.7K X601 OPT

32.768KHz IC602
R637
4.7K
R630
680
AZ7029RTRE1
3
R635
OPT R640 R625 OUT VCC 0
MICOM_RESET 3 1
C OPT
4 R679 4.7M 006:H20;006:AA24 22
4.7K 2
Q604 B
2SC3875S(ALY) LED_LOGO 5 GND
5 1/16W
E 5% 4 3 C607 C609
C610 OPT 0.1uF 10uF
10uF 16V 16V
2 1
10V
P122/X2/EXCLK/OCD0B
OPT GND SKHMPWE010
SW600
+3.3V_ST
P120/INTP0/EXLVI
P124/XT2/EXCLKS
0.1uF
P121/X1/OCD0A
C603
0.1uF
C604
for Debugger
P123/XT1
120K
P600 +3.3V_ST
YFDW254-16S +3.3V_ST 1/16W
FLMD0
RESET
1% R662
REGC
1/10W
R648
100K
VDD
VSS
P40
P41
1 2
1%
R620 4.7K
MICOM_RESET
R621 4.7K
NEC_ISP_Tx 3 4
NEC_ISP_Rx 5 6
7 8
10K
48
47
46
45
44
43
42
41
40
39
38
37
OCD1A 9 10
R617 11 12
OCD1B 13 14
FLMD0 R622 22
P60/SCL0 1 36 P140/PCL/INTP6 EDID_WP
15 16 SCL2_3.3V RL_ON
R623 22
P61/SDA0 2 35 P00/TI000 R664 0
SDA2_3.3V C
P62/EXSCL0 3 34 P01/TI010/TO00 R666 22 B Q3205
EEPROM_SCL 2SC3052
P63 4 33 P130 R682 0 E
R600 10K
EEPROM_SDA
P33/TI51/TO51/INTP4 IC600 P20/ANI0 +3.3V_ST
LED_LOGO
R626 0 5 32 MICOM_DOWNLOAD
R627 22 P75 6 uPD78F0514 31 ANI1/P21

AMP_RESET_N MODEL1_OPT_3
OPT +5V_Normal
R641
P74 ANI2/P22
10K
AC_DET
7 30 MODEL1_OPT_2
+3.3V_ST NEC CONFIGURATION
R615 10K
P73/KR3 8 29 ANI3/P23 R683 22
NEC_ISP_Tx MODEL1_OPT_0 DISP_EN R642
R616 10K
NEC_ISP_Rx R628 22 P72/KR2 9 28 ANI4/P24 R681 0
10K
R613 OPT 10K SOC_RESET
OCD1A
R663 TOUCH_Version_CHECK
R614 OPT 10K
OCD1B R631 22 P71/KR1 10 27 ANI5/P25 10K
MOD_ON
P70/KR0 ANI6/P26
R643
11 26
20K
MODEL1_OPT_1 KEY2
P32/INTP3/OCD1B 12 25 ANI7/P27
OCD1B KEY1
22 R633
13
14
15
16
17
18
19
20
21
22
23
24
SUB_SCL
EEPROM for Micom +3.3V_ST
P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS
+3.3V_ST
R618
4.7K
IC601
M24C16-WMN6T
NC/E0
1 8
VCC
+3.3V_ST
WIRED-IR
R601 +3.3V_ST
47K C601 R668
NC/E1 WC 0.1uF
2 7 4.7K
R667 +3.3V_ST
IR_MICOM R674
22
R671 IR_OUT 0
NC/E2 SCL R632 +3.3V_ST 47K
3 6 EEPROM_SCL KR_BR
R669 R673
22 C 10K
Q602 3.3K
VSS SDA 2SC3052 B
R634
4 5 EEPROM_SDA E R672
22 C 47K
B
Q603 R675 R676
C608 1uF
E
2SC3052 0 0
US US
+3.3V_ST
OPT R677
22
R670 0
R619
R624
0
100
4.7K US
MICOM MODEL OPTION
R636
R678
MODEL PWM OPTION 0
Model option will be changed for GP3 +3.3V_ST
US
PIN NAME PIN NO. HIGH LOW
10K
10K
10K
10K
SUB_SDA
MODEL1_OPT_0 8 ATSC DVB IR
T_TERMINAL1
B_TERMINAL1
B_TERMINAL2
T_TERMINAL2
950
570
R605
R607
R609
R611
E_SPRING
R_SPRING
T_SPRING
MODEL1_OPT_1
NEC_ISP_Rx
NEC_ISP_Tx
11 570 750/950
NEC_RXD
LED_Power_On
NEC_TXD
POWER_ON/OFF2_2
HDMI_CEC
OCD1A
IR_MICOM
LED_RED
MODEL1_OPT_2 30 950 750/570

PSU_ERR_DET R602 33 MODEL1_OPT_0
6A
7A
7B
6B
BLUE_LED_ON R603 33 MODEL1_OPT_1 MODEL1_OPT_3 31 PDP LCD
R604 33 MODEL1_OPT_2
AMP_MUTE R629 33 MODEL1_OPT_3
OPT_1 OPT_2
10K
10K
10K
10K
750/570
750/950
PZ570
OPT
OPT
1 0 RED_LED ONLY
R606
R608
R610
R612
PZ750 0 0 wHITE_LED
PEJ027-01
PZ950 0 1 GALAXY
JK600
US

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 6 31

For Side ESD
* HDMI CEC
M103
5V_HDMI_1 5V_HDMI_4
MDS62110209
BODY_SHIELD BODY_SHIELD
20 HDMI_4_PORT
20
R707 HDMI_HPD_1 R717
HDMI_HPD_4
19 OPT 19 OPT M104
0 C744 HOT_PLUG_DETECT 0 R748 OPT OPT
HOT_PLUG_DETECT R711 R712 C747 R749
0.1uF 1K 18 0.1uF 1K MDS62110209
18 VDD[+5V] HDMI_4_PORT OPT OPT
VDD[+5V] OPT OPT OPT OPT R747 D719 +3.3V_ST
R710 D712 17 R718 3.6K 5.5V
17 R708 3.6K 5.5V HDMI_4_PORT
DDC/CEC_GND 0 DDC/CEC_GND 0
DDC_SDA_1 DDC_SDA_4
16 16
SDA SDA
DDC_SCL_1 15 DDC_SCL_4 R732 M105
15 R719
G
SCL R709 SCL 22K
0 0 MDS62110209
14 14
RESERVED RESERVED
120K
CEC_REMOTE CEC_REMOTE
13
R739
13 CEC
CEC
D
B
S
Q710
BSS83
CK-_HDMI1 CK-_HDMI4 D714
12 12
TMDS_CLK- TMDS_CLK- BAT54
11 11
TMDS_CLK_SHIELD TMDS_CLK_SHIELD
CK+_HDMI1 CK+_HDMI4
10 10
TMDS_CLK+ CEC_REMOTE HDMI_CEC
TMDS_CLK+
D0-_HDMI1 D0-_HDMI4
9 9
8
TMDS_DATA0-
ARC 8
TMDS_DATA0-
TMDS_DATA0_SHIELD
TMDS_DATA0_SHIELD D0+_HDMI4
D0+_HDMI1 7
7 TMDS_DATA0+
TMDS_DATA0+
D1-_HDMI1 HDMI_ARC D1-_HDMI4
6 6
TMDS_DATA1- TMDS_DATA1-
5 5
R729 TMDS_DATA1_SHIELD
TMDS_DATA1_SHIELD
1%
D1+_HDMI1 C730 D1+_HDMI4

150 4
4 0.1uF TMDS_DATA1+
TMDS_DATA1+
D2-_HDMI1 D2-_HDMI4
3 3
1%
R738 TMDS_DATA2-
TMDS_DATA2-
63.4 2
2 TMDS_DATA2_SHIELD
TMDS_DATA2_SHIELD
D2+_HDMI1 D2+_HDMI4
1 1
TMDS_DATA2+ TMDS_DATA2+
RSD-105156-100 RSD-105156-100 HDMI_4_PORT

JK703 JK704 +3.3V_Normal
HDMI1 HDMI4
C731 C732 C733 C734 C735 C736 C737

10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF
10V 10V 10V 16V 16V 16V 16V HDMI1 HDMI S/W OUTPUT
BODY_SHIELD 5V_HDMI_2
D0+_HDMI1
D0-_HDMI1
D2-_HDMI1
D1+_HDMI1
D1-_HDMI1
CK+_HDMI1
CK-_HDMI1
D2+_HDMI1
HDMI_CLK-
HDMI_RX0-
HDMI_RX0+
HDMI_RX1-
HDMI_RX1+
HDMI_RX2-
HDMI_RX2+
HDMI_CLK+
20
R703
HDMI_HPD_2
19 OPT
HOT_PLUG_DETECT 0 R744 C746 R746
0.1uF 1K +5V_Normal +5V_Normal
18 OPT OPT OPT OPT 5V_HDMI_2
VDD[+5V] 5V_HDMI_1
R722 D718
17 R704 3.6K 5.5V
DDC/CEC_GND 0
DDC_SDA_2
A1
A2
A1
A2
16
SDA
15 DDC_SCL_2 D713 D715
SCL R705
C
0
14
RESERVED
CEC_REMOTE
13
CEC R731 R733 R734 R735
CK-_HDMI2
12 4.7K 4.7K 4.7K 4.7K
TMDS_CLK-
11
TMDS_CLK_SHIELD DDC_SDA_1 DDC_SDA_2 +3.3V_Normal
CK+_HDMI2
10
TPWR_CI2CA
TMDS_CLK+ DDC_SCL_1 DDC_SCL_2
D0-_HDMI2
9
TMDS_DATA0-
[EP]GND
VCC33_3
8
4.7K
4.7K
TMDS_DATA0_SHIELD OPT
R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
D0+_HDMI2 R713 R750 0
7 SCL2_3.3V
TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
4.7K
OPT
OPT
TMDS_DATA0+
D1-_HDMI2 OPT
6 SDA2_3.3V
TMDS_DATA1-
R714
0 R751
R715
5 +5V_Normal +5V_Normal
TMDS_DATA1_SHIELD 5V_HDMI_3
D1+_HDMI2 5V_HDMI_4
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
4
TMDS_DATA1+ R752
D2-_HDMI2 HDMI2 R1XCN 1 54 CSCL 0
A1
A2
3
A1
A2
SCL3_3.3V
TMDS_DATA2- CK-_HDMI2 R753
2
R1XCP 2 53 CSDA 0
D716 D717 SDA3_3.3V
TMDS_DATA2_SHIELD CK+_HDMI2 THERMAL
D2+_HDMI2 R1X0N INT
C
3 52
C
1
TMDS_DATA2+ D0-_HDMI2
73
R1X0P 4 51 CEC_D
D0+_HDMI2
R736 R737 R740 R741 R1X1N 5 50 CEC_A +5V_Normal
RSD-105156-100 4.7K 4.7K D1-_HDMI2
4.7K 4.7K
JK701 R1X1P 6 49 R4PWR5V R716
HDMI2 DDC_SDA_4 D1+_HDMI2
R1X2N 0
C738
7 IC700 48 DSCL4
DDC_SDA_3 1uF
DDC_SCL_4 D2-_HDMI2 5V_HDMI_4
R1X2P DSDA4 10V
DDC_SCL_3 D2+_HDMI2
8 SII9287B 47
R720
VCC33_1 9 46 R3PWR5V 10
C739
RSVD_1 10 45 CBUS_HPD3
HDMI_HPD_4
1/16W
R721
HDMI3 R2XCN 11 44 DSCL3
1%
1K
EDID Pull-up CK-_HDMI3 DDC_SCL_4 5V_HDMI_3
1uF
R2XCP 12 43 DSDA3
CK+_HDMI3 DDC_SDA_4 R723
5V_HDMI_3
R2X0N 13 42 R2PWR5V 10
BODY_SHIELD D0-_HDMI3
C740
R2X0P 14 41 CBUS_HPD2
HDMI_HPD_3
1/16W
20 D0+_HDMI3
DSCL2
R724
R2X1N 15 40
1%
R706
1K
HDMI_HPD_3 D1-_HDMI3 DDC_SCL_3
1uF
19
HOT_PLUG_DETECT 0 OPT OPT OPT R2X1P 16 39 DSDA2
R743 C745 R745 D1+_HDMI3 R730 DDC_SDA_3
18 0.1uF 1K R2X2N SBVCC 0
VDD[+5V] OPT OPT 17 38
C741
R742 D711 D2-_HDMI3
17 R701 3.6K 5.5V R2X2P MICOM_VCC33 OPT
DDC/CEC_GND 0
D2+_HDMI3
18 37
DDC_SDA_3
16
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SDA
1uF
15 DDC_SCL_3
SCL R702
0 +3.3V_Normal
14
R3XCN
R3XCP
R3X0N
R3X0P
R3X1N
R3X1P
R3X2N
R3X2P
VCC33_2
RSVD_2
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
RESERVED
CEC_REMOTE 5V_HDMI_2
13
CEC
CK-_HDMI3 R725
12 10
TMDS_CLK-
C742
11
TMDS_CLK_SHIELD
1/16W
CK+_HDMI3
10
R726
1%
TMDS_CLK+
1K
D0-_HDMI3
1uF
9
TMDS_DATA0-
8
TMDS_DATA0_SHIELD
D0+_HDMI3 5V_HDMI_1
7
TMDS_DATA0+
D1-_HDMI3 R727
6 10
TMDS_DATA1-
C743
5
TMDS_DATA1_SHIELD
1/16W
D1+_HDMI3
R728
4
1%
TMDS_DATA1+
1K
D2-_HDMI3
1uF
3
TMDS_DATA2-
2
TMDS_DATA2_SHIELD
DDC_SDA_1
DDC_SDA_2
DDC_SCL_2
DDC_SCL_1
HDMI_HPD_1
HDMI_HPD_2
D2+_HDMI4
CK-_HDMI4
CK+_HDMI4
D0-_HDMI4
D1-_HDMI4
D1+_HDMI4
D2-_HDMI4
D0+_HDMI4
D2+_HDMI3
1
TMDS_DATA2+
RSD-105156-100
JK702
HDMI4
HDMI3

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 7 31

RGB/ PC AUDIO/ SPDIF/ EARPHONE/ RS232C
R816
47K
US
US
R828
0
+5V_Normal
RGB PC D810
ENKMC2838-T112 US C
A1 US 47K 10
C B Q801
5
A2
RS232C PHONE JACK IR_OUT
R818
E
2SC3052
9
+3.3V_ST R837KR_BR 100
4
+5V_Normal
IC801
74F08D
8
IC802
100 R833 JP809
C811 3
D0A VCC AT24C02BN-SH-T R814 0.1uF
1 14 R815 R817
16V 7
2.7K 2.7K 10K
A0 VCC
D0B
2 13
D3B C806 1 8
100 JP810
DSUB_VSYNC 22 R801 0.1uF R834
2
16V A1
2 7
WP
Q0 D3A EDID_WP
3 12 6
A2 SCL R848 22 IC803
DSUB_HSYNC 22 R802 3 6
RGB_DDC_SCL C820 KR_BR100 R838
R826 D1A Q3 MAX3232CDR
4 11
R847 22 0.1uF 1
0 GND SDA
4 5
RGB_DDC_SDA
D1B D2B R827
OPT 5 10
0 C809 C810 C1+ VCC +3.3V_ST D814
0.1uF C812 1 16 D813 CDS3C30GTH SPG09-DB-009
Q1 D2A 18pF 18pF
6 9 OPT 50V 50V CDS3C30GTH 30V
30V OPT P802
GND
7 8
Q2
C813 V+ GND OPT
0.1uF 2 15
R807 C1- DOUT1

22 R810 3 14
10K RGB Compiance Test Improve by BCM
D804 C807
22pF 0.1uF C814 C2+ RIN1
4 13 R829
30V 50V R832 +3.3V_ST
4.7K
4.7K
C2- ROUT1
5 12
0 R841
22 R809 D811
R808 D809 V- DIN1
D805 0.1uF C815 6 11
10K 5.6V
30V C808 5.6V OPT C827
IC805
22pF OPT
50V 0.1uF
MC14053BDR2G
L803 DOUT2 DIN2
7 10 UART_TXD_3D
BLM18PG600SN1D
VDD Y1 R845 0
OPT RIN2 ROUT2 16 1
DSUB_B+ 8 9 BCM_RX
R821
D808 UART_RXD_3D
R812 C821 OPT
30V Y Y0
4.7pF R846 0
0
75 EAN41348201 15 2
50V NEC_RXD
X Z1
14 3
R836
0
R830 0 X1 Z
L804 BCM_TX 13 4
R822
BLM18PG600SN1D
+5V_Normal
X0 Z0
0
R831 0
DSUB_G+ NEC_TXD 12 5
OPT +3.3V_Normal
R811 D806
75 C822 30V R835
2.7K A INH
4.7pF 11 6
50V R819
2.7K
B VEE
10 7
DSUB_DET
1K R820 R800
100K C VSS
L805 9 8
BLM18PG600SN1D D812 C828
5.6V 100pF
50V
DSUB_R+
OPT D807
HIGH : SELECT X1, Y1, SELECT MAIN TX/RX
R813 C823 30V
75
LOW : SELECT X0, Y0, SELECT MICOM TX/RX
4.7pF
50V
GREEN_GND
DDC_CLOCK
DDC_DATA
BLUE_GND
SYNC_GND
RED_GND
DDC_GND
H_SYNC
V_SYNC
GND_2
GREEN
GND_1
BLUE
RED
NC
SPG09-DB-010
SHILED
11
12
13
14
15
16
10
6
9
P801
PC AUDIO
CDS3C30GTH
JK800
CDS3C30GTH
PEJ027-01
D816
D815
3 E_SPRING
6A T_TERMINAL1
OPT
30V
BLM18PG121SN1D
B_TERMINAL1
50V
270pF
7A L802
OPT
PC_R_IN
C819
ZD8001
5.1V
50V
270pF
4 R_SPRING C802 C805

R805
C817
560pF 560pF +3.3V_Normal

ZD8002
470K
10
10
50V 50V
5.1V
R825
R823
5 T_SPRING
C818 OPT
B_TERMINAL2 R824
50V
82pF
7B BLM18PG121SN1D
50V
82pF
OPT
L801 1K
C816
PC_L_IN
ZD8003
6B T_TERMINAL2
5.1V
C801 C804 032:H20

R804
470K 560pF 560pF
PC_SER_DATA
ZD8004
50V 50V
5.1V
PC_SER_CLK
032:H20
JK802
+3.3V_Normal JST1223-001
GND
SPDIF OUT
1
Fiber Optic
R806 VCC
2
2.7K
R803
0 VINPUT
3
SPDIF_OUT
C803
4
D803
5% 30V 0.1uF
OPT 16V FIX_POLE

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. COMMON JACK 8 31

SUB Board I/F
P900
+3.3V_ST 12507WS-15L
R905
0 IR
IR 1
R919 R920 R900 C908
10pF
10K 10K 4.7K GND
1% 1% 2
L902
R915 MLB-201209-0120P-N2
100 KEY1
KEY1 3
R916 L901 C906

100 MLB-201209-0120P-N2 10pF KEY2
KEY2 4
C903
R909 10pF
22 LED-RED
5
LED_RED C905 D902
+3.3V_ST 10pF GND
6
R903 R904
** IR OPT LIST R925
4.7K 4.7K SCL
22
SUB_SCL 7
570 : L900 -> JUST INPUT TOUCH KEY VOLTAGE 3.3V D900
OPT R924 CDS3C05HDMI1
SDA
750/950 : L904 -> GALAXY INPUT VOLTAGE 5V C901 22 5.6V
8
SUB_SDA 10pF
750/570 : R906 -> GALAXY CTRL PIN GND D901
R901
C900 CDS3C05HDMI1 0 GND
905 : R901 -> GALAXY GTRL PIN - BLUE_LED_ON PATH +5V_Normal +3.3V_Normal 10pF
+3.3V_ST 5.6V 9
OPT 950 0
L903 R906
MLB-201209-0120P-N2
750/570 3.3V_ST 10
+3.3V_Normal C902
L904 L900 570
750/950
0.1uF
16V 3.3V_MULTI
R902 11
4.7K C904
0.1uF
LED-WHITE
16V 12
LED_Power_On
C907
10pF
13
14
TOUCH_Version_CHECK 15
BLUE_LED_ON 16

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR/KEY 9 31

WIRELESS READY MODEL
JK1001
KJA-PH-3-0168
Wireless power VCC(24V/20V/17V)_1

1
VCC(24V/20V/17V)_2
2
VCC(24V/20V/17V)_3
3
VCC(24V/20V/17V)_4
4
VCC(24V/20V/17V)_1
5
P_17V
VCC(24V/20V/17V)_1
6
DETECT
+3.3V_Normal 7
C1001 INTERRUPT
0.1uF R1002 C1002 8
50V 22K 2.2uF GND_1
S R1008 9
10K RESET
G 10
R1003 Q1002 R1007 1K GND_2
D L1000 WIRELESS_DET 11
2.2K AO3407A
MLB-201209-0120P-N2 I2C_SCL
WIRELESS_SCL 12
R1001 C
I2C_SDA
WIRELESS WIRELESS_PWR_EN 10K B MMBT3904(NXP) WIRELESS_SDA 13
Q1001 C1003 GND_3
14
50V
E UART_RX
0.01uF 15
+3.3V_ST
UART_TX
16
+3.3V_ST GND_4
R1012 17
47K IR
R1013 IR_PASS 18
22
R1010 IR_PASS GND_5
19
SIGN52200
47K
R1011
10K C Q1004 GND_6 20
B 2SC3052
R1009 E
21
47K C
IR_OUT B SHIELD
E Q1003
2SC3052
OPT
R1014
0
Wireless I2C connection with I2C_1

Address : 0X20
R1005 33
WIRELESS_SCL SCL2_3.3V
R1006 33
WIRELESS_SDA SDA2_3.3V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. WIRELESS 10 31

+3.3V_Normal
R1128
2.7K
AV2_CVBS_DET
R1129
1K
D1111 C1112
0.1uF
COMPONENT1/2,AV1 5.6V 16V
OPT
JK1100
PPJ237-01 REAR AV 1 R1101
0
R1142
10
6C [RD1]E-LUG
+3.3V_Normal
SIDE_AV 2 ZD1115
AV1_CVBS_IN
5.1V
BLM18PG121SN1D R1132
COMPONENT2 ZD1116
R1109
75
C1106
47pF +3.3V_Normal
5C [RD1]O-SPRING 0 5.1V 50V
L1105 R1127
AV2_R_IN 2.7K
5A [YL]E-LUG
ZD1114 R1112
5.6B 1K R1130 2.7K
[RD1]CONTACT R1116 SC_DET/COMP2_DET
R1140
C1118 C1123
4C
12K
OPT
470K 560pF 560pF 4A [YL]O-SPRING R1113
ZD11213 1K
50V 50V D1114
5.6B C1111 AV1_CVBS_DET
5.6V 0.1uF 3A [YL]CONTACT
5B [WH1]O-SPRING 16V
BLM18PG121SN1D OPT D1105
R1131 5.6V
0 4B [WH]O-SPRING BLM18PG121SN1D R1152 C1105
L1106 0 0.1uF
AV2_L_IN L1101
[YL1]CONTACT ZD11211 BLM18PG121SN1D R1144 AV1_L_IN 16V
4A 5.6B L1103 0 3C [RD]CONTACT
5.6B
OPT
R1117 SC/COMP2_R_IN ZD11218
R1139
C1119 C1124 R1110

12K
ZD11216
OPT
R1154
ZD11212 470K 560pF 560pF C1107 C1109
12K
5.6B 5.6B R1122 4C ZD11219 470K
50V 50V [RD]O-SPRING 560pF 560pF
OPT
[YL1]O-SPRING
R1146
5A 470K C1121
12K
5.6B
OPT
C1113 50V 50V
560pF 560pF
R1143 ZD11217 5C
50V 50V [RD]E-LUG
R1115 0 10 5.6B
AV2_CVBS_IN
6A [YL1]E-LUG PPJ235-01 BLM18PG121SN1D R1153
ZD1101 C1120 JK1101 0
R1118 L1102
5.1V 75 47pF BLM18PG121SN1D R1145 AV1_R_IN
50V L1104 0 ZD11220
ZD1102 SC/COMP2_L_IN
6H [RD2]E-LUG 5.6B
R1155
5.1V ZD11214 R1111 C1110
12K
5.6B R1123 C1114 C1122 470K C1108 560pF
ZD11221
OPT
R1147
560pF 560pF
12K
470K 560pF 5.6B 50V
OPT
50V 50V
5H [RD2]O-SPRING_2 ZD11215 50V
5.6B
[RD2]CONTACT L1108
4H 270nH 1% R1133
10
SC_R/COMP2_Pr
ZD1103 C1101 C1102
5G [WH2]O-SPRING 5.1V 27pF 27pF
R1124
ZD1104 50V 50V 75
5.1V
5F [RD2]O-SPRING_1
L1109
270nH 10 1% R1134
+3.3V_Normal COMPONENT1
7F [RD2]E-LUG-S SC_B/COMP2_Pb
ZD1105 C1103 C1115
5.1V 27pF 27pF R1125 R1114
2.7K
[BL2]O-SPRING ZD1106 50V 50V 75
5E 5.1V 1K R1141
COMP1_DET
D1102
7E [BL2]E-LUG-S C1100
5.6V 0.1uF
16V
OPT
4D [GN2]CONTACT BLM18PG121SN1D R1148

L1107 0
COMP1_R_IN
L1110 ZD1117
[GN2]O-SPRING 270nH 1% 5.6B R1108
R1150
5D 10 470K C1127
12K
R1135 SC_G/COMP2_Y C1125
OPT
560pF 560pF
ZD1107 ZD1120
C1116 C1117 5.6B 50V 50V
5.1V
[GN2]E-LUG 27pF 27pF R1126
6D ZD1108 50V 50V 75
5.1V
6N [RD3]E-LUG BLM18PG121SN1D R1149

L1100 0
COMP1_L_IN
ZD1118
R1107 C1126
[RD3]O-SPRING_2 5.6B C1104
R1151
5N 560pF
12K
470K 560pF
OPT
ZD1119 50V 50V
5.6B
4N [RD3]CONTACT
L1113
[WH3]O-SPRING 270nH 10 1% R1138
5M COMP1_Pr
ZD1112 C1128 C1129
5.1V 27pF 27pF
5L [RD3]O-SPRING_1 50V 50V R1106
ZD1113 75
5.1V
7L [RD3]E-LUG-S
L1112
5K [BL3]O-SPRING 270nH 10
1%
R1137
COMP1_Pb
ZD1111 C1130 C1131
5.1V R1105
[BL3]E-LUG-S 27pF 27pF 75
7K ZD1110 50V 50V
5.1V
4J [GN3]CONTACT
L1111
5J [GN3]O-SPRING 270nH 10
1%
R1136
COMP1_Y
ZD1109 C1132 C1133
5.1V
[GN3]E-LUG 27pF 27pF R1104
6J ZD1100 50V 50V 75
5.1V
CLOSE TO JUNCTION

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. COMP/AV 11 31

+3.3V_Normal
USB 1 USB 2 +3.3V_Normal
IC1200 +5V_USB
AP2191DSG
R1201 IC1201
L1200 NC 8 +5V_USB
1 GND 4.7K AP2191DSG
MLB-201209-0120P-N2 OPT R1204
OUT_2 7 L1201
2 IN_1 NC 8 1 GND 4.7K
MLB-201209-0120P-N2 OPT
120-ohm OUT_1 6 3 IN_2 OUT_2 7 2 IN_1
C1201
C1206 FLG 5 C1202 120-ohm
C1200 4 EN 10uF OUT_1 6 3 IN_2
100uF R1202 0.1uF C1204
100uF 2.7K 10V FLG 5 C1205
16V
16V
EAN61849601 C1207 C1203 4 EN 10uF
USB_CTL1 100uF R1205 0.1uF
100uF EAN61849601 2.7K 10V
16V 16V
R1200 0 /USB_OCD1 USB_CTL2

3AU04S-305-ZC-(LG)
3AU04S-305-ZC-(LG)
1
P1200
R1203 0 /USB_OCD2
P1201
USB DOWN STREAM
USB DOWN STREAM

2
USB_DM1
2
USB_DM2
RCLAMP0502BA
RCLAMP0502BA
3
USB_DP1
3
USB_DP2
4
D1201
4
D1200
5
OPT
OPT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB 12 31

Motion Remote controller
TI solution M_REMOTE OPTION
+3.3V_Normal
+3.3V_Normal
P1302
12507WS-12L
120-ohm
L1303
1
R1322
R1323
2.7K
2.7K
R1321
2.7K
R1315
100
3 M_REMOTE_RX
R1316
100
4 M_REMOTE_TX
R1317
100
5 M_RFModule_RESET
R1318
100
6 DC_MREMOTE
R1319
100
7 DD_MREMOTE
R1320
22
9 3D_GPIO_0
R1325
22
10 3D_GPIO_1
R1326
22
11 3D_GPIO_2
R1324
22
12 3D_SYNC
13
ALL M_REMOTE OPTION

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. M_REMOCON 13 31

Ethernet Block
+2.5V_BCM35230
+2.5V_BCM35230
CIS21J121
CIS21J121
L1400
L1401 JK1401
43-10013AD11-1
TDP
EPHY_TDP 1
ADLC 5S 03 015
002:H20
5.5V
D1400
TD_CT
2
TDN
EPHY_TDN 3
ADLC 5S 03 015
C1400
5.5V
D1401
002:H20
RDP
EPHY_RDP 4
0.1uF 002:H19
ADLC 5S 03 015
5.5V
D1404
RD_CT
5
RDN
EPHY_RDN 6
002:H19
ADLC 5S 03 015
NC
5.5V
D1405
7
C1401
0.1uF
GND
8
+3.3V_Normal
R1401
510 D1
D1
ADLC 5S 03 015
LINK_LED
EPHY_LINK D2
5.5V
D1403
R1400
510 D2
D3
ACTIVE_LED
ADLC 5S 03 015
EPHY_ACTIVITY D4
002:N16
5.5V
D1402
GND
R1402
0
1/10W
5%
R1403
0
1/10W
5%
R1404
0
1/10W
5%
R1405
0 MDS62110209
M1401
1/10W
5%

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETHERNET 14 31

LVDS

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS 15 31

P_17V
+17V_AMP
L1604
0LCML00003B
+3.3V_AMP MLB-201209-0120P-N2
19 18
+3.3V_AMP EAPD/OUT4B OUT3A/FFX3A C1627
0.1uF C1628
50V 0.1uF
OPT 50V
R1601
10K
OPT
20 17
C 0 TWARN/OUT4A OUT3B/FFX3B
0 R1612
R1600 B
Q1600
AMP_MUTE
10K 2SC3052 50V R1617 21 16
OPT E
OPT 0.1uF
C1604
VDD_DIG_1 CONFIG
22 15 50V
0.1uF
+3.3V_Normal
GND_DIG_1 VDD C1606
+3.3V_AMP
AC_DET
0 R1611 23 14 L1605
PWRDN GND_REG MLB-201209-0120P-N2
SPK_L+
24 13 10.0uH
L1600 C1629 C1630
VDD_PLL OUT1A C1619 C1623 0.1uF
50V
10uF
16V
20 0.22uF 1000pF
R1619
Close-by 25 12 Close-by 1uF 25V

C1617
50V 50V
Near-by AMP
FILTER_PLL GND1 C1608
C1616
330pF
0.22uF
50V
50V
C1620 C1624
26 11 0.22uF 1000pF
GND_PLL 10 OUT1B
VCC1 0.1uF 50V
50V 50V
C1609 SPK_L-
AUD_MASTER_CLK
100
R1605 27 10.0uH
XTI 9 OUT2A L1601
AUD_SCK SPK_R+
100
R1606 28 1uF 25V 10.0uH
BICKI 8 VCC2 Close-by C1610

C1615
330pF
L1602
C1621 C1625
AUD_LRCK 50V 0.22uF 1000pF
100
R1607 29 50V 50V
LRCKI 7 GND2 0.1uF 50V C1618

0.22uF
C1611 20 R1618 50V
AUD_LRCH
C1622 C1626
100
R1608 30 0.22uF 1000pF
SDI 6 OUT2B 50V 50V
AMP_RESET_N SPK_R-
0
31 10.0uH
R1609
RESET 5 VCC_REG L1603
+17V_AMP
32 50V
1%
1/16W
INT_LINE 4 VSS 0.1uF
C1607 WAFER-ANGLE
THERMAL
SDA3_3.3V
100
R1616 33
1% SDA 3 TEST_MODE SPK_L+ 4
37
1/16W
SCL3_3.3V
100
R1614 34 35V 35V
SPK_L- 3
+3.3V_AMP R1610
2K
+3.3V_AMP
SCL 2 SA 50V
0.1uF
68uF 68uF
Close-by C1613 C1614
SPK_R+
C1612 OPT 2
R1604
35
2K
10K GND_DIG_2 1 GND_SUB SPK_R- 1
R1603 P1600
R1615
2.2
36
50V 50V VDD_DIG_2
0.1uF 0.1uF
16V 50V C1603 C1605
R1613
0.1uF
C1600
680pF
[EP]GND
2K
50V C1602
4700pF
C1601 STA368BWG
R1602
0 IC1600

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MSD3368EV Platform
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AUDIO 6 10
AUDIO[STM]

H/NIM & CHB_H/NIM (KOR/USA/Brazil) +5V_TU
+3.3V_Normal +3.3V_TU
+3.3V_S_TU
L2103 L2102
CIC21J501NE BLM18PG121SN1D
BR L2101
R2159
BLM18PG121SN1D
1K
C2144 C2149 C2163 KOR C2169
A1[GN]
A2[RD]
C2140 C2141 0.1uF KOR
0.1uF C2116 10uF 0.1uF
0.1uF 22uF 16V
16V 47uF 10V KOR
16V 16V
16V
+3.3V_S_TU BR
D2100
SAM2333
R2127
+3.3V_M_TU
C
10K
Q2102
OPT R2107 ISA1530AC1
100K E L2105
BR R2118
R2104 0 BLM18PG121SN1D
RF_SWITCH_CTL_2
B 2.2K
KOR BR C C2161 C2167
C R2129 KOR 10uF 0.1uF
R2105 0 Q2103 B 10K 10V
RF_BOOSTER_CTL KOR KOR
2SC3052
BR C2114 BR
BR
Close to Tuner BR 0.01uF E +3.3V_DE
50V
KOR L2106
US BR +3.3V_S_TU BLM18PG121SN1D
0 R2155
TU2103 TU2101 TU2102 KOR C2117

C2162
10uF
C2168
0.1uF
close to TUNER C2111 4.7uF 10V
UDA55AL TDTR-T036F TDSB-H001F R2102 0 OPT 0.1uF KOR 10V
16V
RF_SWITCH_CTL
+5V_TU
C2101 Close to Tuner +1.8V_S_TU
0.1uF
+5V_TU
NC_1 RF_S/W_CTL SW_CTL1[NC] 16V CLOSE TO TUNER PIN
1 1 1 L2100
+3.3V_TU
NC_2 BST_CTL SW_CTL2[NC] R2134
2 2 2 C2107 C2115 C2120
C2108C2137 C2138
4.7uF 0.1uF 470 R2138
1200pF 22uF 82
+B[+5V] +B1[5V] SW_5V 50V 10V 16V
0.1uF 16V
E
TU_SIF L2110
3 3 3 KOR KOR C2129 KOR
4.7uF
NC[RF_AGC] NC_1[RF_AGC] S_3.3V R2108 R2141 120-ohm
close to TUNER IC2102
OPT
0 B
4 4 4 SCL0_3.3V 100pF 0 AZ1117BH-1.8TRE1
R2133 Q2104
50V C MMBT3906(NXP)
AS NC_2 S_1.8V R2109 4.7K
KOR
5 5 5 0 IN ADJ/GND +1.8V_S_TU
SDA0_3.3V 3 1
C2118 C2122
SCL SCLT TU_SCL 18pF 2
18pF +1.8V_M_TU KOR
6 6 6 OPT 50V OPT 50V BLM18PG121SN1D
KOR OUT L2108
OPT
SDA SDAT TU_SDA C2130 close to TUNER C2119
0.1uF
7 7 7 16V +5V_TU 0.1uF 120-ohm C2160 C2166
C2124 C2125 KOR 10uF 0.1uF
4.7uF
+3.3V_M_TU KOR
NC(IF_TP) NC_3 M_1.8V 0.1uF R2145
C2152
10V
KOR KOR
8 8 8 10V 16V 47uF
KOR 16V 0.1uF
KOR
SIF SIF M_SIF C2131
9 9 9 C2128
KOR 4.7uF 0.1uF R2139
10V 16V 1K R2142 R2143
NC_3 NC_4 M_3.3V KOR 220 220
+1.8V_M_TU
10 10 10 OPT 1/8W 1/8W
KOR
VIDEO VIDEO M_CVBS OPT 0
BLM18PG121SN1D
L2104
11 11 11 TU_CVBS
+1.26V_TU C2159 C2165
GND GND GND_1 +3.3V_DE +3.3V_TU R2136 E 120-ohm
10uF 0.1uF
0
12 12 12 10V KOR KOR
OPT R2137 B
+1.2V +B2[1.2V] SD_1.2V R2120 Q2105
C2103 C2105 R2117 100K 1K R2140 MMBT3906(NXP)
13 13 13 4.7uF 0.1uF C2112
C2113
100 C
0.1uF TU_RESET OPT
10V 16V 4.7uF
+3.3V +B3[3.3V] SD_3.3V 10V 16V C2123
14 14 14 0.1uF
16V
RESET RESET TU_RESET
15 15 15
IF_AGC_CNTL IF/AGC M_IF_AGC R2160
1K
16 16 16 IF_AGC
Close to the tuner
IC2103 +1.26V_TU
DIF_1 DIF_1[N] M_DIF[N] C2150 +3.3V_TU AZ1117BH-ADJTRE1
17 17 17 0.1uF
16V IF_N
OPT C2110
DIF_2 DIF_2[P] M_DIF[P] 22pF
18 18 18 50V IF_P L2112 L2114
OPT C2109 120-ohm
BLM18PG121SN1D
19
SD_ERROR 0
22pF
50V
INPUT 3 2 OUTPUT
19 19 R2101
SD_SYNC KOR
20 CHB_TS_SYNC 1 R1 C2181 C2106
C2182 C2179
R2158
SHIELD SHIELD 33 47uF 22uF 0.1uF
220
R2130 22uF 10V
SD_VALID 16V 50V
21 KOR
CHB_TS_VAL
C2180 C2178
2.2uF
ADJ/GND
33 2.2uF R2
R2132 16V
SD_MCL KOR
16V
R2167
22 CHB_TS_CLK 4.7
33 R2146
SD_D0 KOR
23 CHB_TS_DATA
33 R2156
NC
24 VOUT = VREF *(1+R2/R1)
GND_2 KOR
25
0 R2125 PIN 25~30 MUST BE SEPARATED TUNER GND
GND_3 KOR CLOSE TO PIN 25
26
0 R2123 R2131
GND_4 KOR 0
27
0 R2119 KOR
GND_5 KOR
28
0 R2124 R2144
GND_6 KOR
0
29 KOR
0 R2115
GND_7 KOR CLOSE TO PIN 29
30
0 R2122
SD_2.5V[OPT]
31
SD_RESET
32
SIF/NC +3.3V_S_TU
33 +5V_TU
S_CVBS R2121 R2128
34 100K
100 OPT
TU_RESET_SUB
SD_SCL R2147 KOR C2126
0
35 SCL1_3.3V R2114 R2116
0.1uF
0
16V R2100
R2148 200 200
KOR
IF_AGC_MAIN
SD_SDA 0 KOR KOR
36 IF_AGC
SDA1_3.3V R2112
37 C2102 C2104 1K OPT
18pF 18pF
50V OPT CHB_CVBS
OPT 50V
E
R2135 0
R2106 0 Q2101 ISDB_IF_AGC
SHIELD close to TUNER MMBT3906(NXP) OPT
KOR B
KOR R2103 0
C IF_N_MAIN
R2113 OPT
1K IF_N
R2111 0
TUNER_IF_N
OPT
R2126 0
IF_P_MAIN
IF_P
R2110 0
TUNER_IF_P
OPT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER DUAL 21 31

CHANNEL BROWSER C2707
27pF
R2707
X2700
27MHz
C2708
27pF
1M
R2708
100
+3.3V_ADC +3.3V_ADC
+1.8V_ADC
+1.8V_ADC
POWER for CHB

VD[0]/SIAD0
VSSE_2
VD[1]
VSS_2
VD[2]
VD[3]
VD[4]
VD[5]
VD[6]
NC_4
XTO
XTI
CLOSE TO SOC
+3.3V_Normal TW9910_DATA[0-7]
48
47
46
45
44
43
42
41
40
39
38
37
C2701 0.1uF VDDE_1 1 36 VD[7]

AR2700 22
R2700 R2703 100 SCLK 2 35 VD[8] TW9910_DATA[0]
SCL1_3.3V
2.7K R2704 100 SDAT 3 34 VD[9] TW9910_DATA[1]
SDA1_3.3V +3.3V_Normal +3.3V_CHB
PDN 4 33 VD[10] TW9910_DATA[2]
R2702 100 RSTB 5
IC2700 32 VDD C2718 TW9910_DATA[3]
TW9910_RESET
TMODE NC_3 0.1uF
6 TW9910DANB2-GR 31 L2702
4.7K
R2705
NC_1 VD[11] BLM18PG121SN1D

7 30 AR2701 22
C2702 0.1uF AVD_1 8 29 VD[12] TW9910_DATA[4]
C2703 0.1uF YMUX3 9 0x88 28 VD[13] TW9910_DATA[5]
KOR KOR C2721
10uF
KOR C2724
0.1uF
C2704 0.1uF YMUX2 VD[14] TW9910_DATA[6] 10V 16V
10 27
YGND 11 26 VD[15] TW9910_DATA[7]
C2705 0.1uF YMUX1 12 0IPRP00630E 25 VDDE_2 C2719
0.1uF
13
14
15
16
17
18
19
20
21
22
23
24
+3.3V_ADC
YMUX0
AVS_1
CIN0
AVD_2
AVS_2
NC_2
VSS_1
VS
HS
MPOUT
CLKX2
VSSE_1
L2701
BLM18PG121SN1D
C2700
R2706 0
CHB_CVBS
C2710 KOR C2722 KOR C2725
0.1uF KOR
10uF 0.1uF
10V
16V
0.1uF
R2714
TW9910_CLK
22
C2712
0.1uF
+3.3V_CHB
IC2702 KOR
CHB_RESET
AZ1117BH-1.8TRE1
IN 3 1 ADJ/GND
2
C2714 C2717
30pF 30pF +1.8V_CHB
KOR C2720 OUT
0.1uF
X2701 16V
CLOSE TO SOC 27MHz
R2722 0
+3.3V_Normal KOR
R2713 C2727
1M KOR
KOR KOR 10uF C2729
R2709 10V 0.1uF
2.7K C2723 KOR C2726
47uF 0.1uF
16V 16V
R2710
12
+1.8V_ADC
TW9910_DATA[0-7]
TW9910_DATA[5]
TW9910_DATA[6]
TW9910_DATA[7]
R2723 0
KOR
0.1uF
0.1uF
C2715
C2716
+3.3V_CHB C2728 KOR

KOR 10uF C2730
10V 0.1uF
+1.8V_CHB
EXT_RESET_N
VDDIO_XTAL
VSSCORE_3
VDDCORE_4
SPLL_AVDD
SPLL_AVSS
D1_DATA5
D1_DATA6
D1_DATA7
XTAL27O
XTAL27I
TRST
TMOD
TCK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
C2709 VDDIO_1 TS Output

1 42 IRQ_CHB_N
TW9910_DATA[4] 0.1uF D1_DATA4 2 41 TSVO0_DATA
TW9910_DATA[3] D1_DATA3 3 40 TSVO0_SOP CHBO_TS_SERIAL
TW9910_DATA[2] D1_DATA2 4 39 VSSIO_3
CHBO_TS_SYNC
R2701 VSSIO_1 5 38 TSVO0_CLK
CHBO_TS_CLK
0 D1_CLK 37 PA4/FIFOADR0
TW9910_CLK 6 CHBO_TS_VAL_ERR
TW9910_DATA[1] D1_DATA1 7 IC2701 36 VSSCORE_2
C2706 VDDCORE_1 LG1140 C2732
8 35 VDDCORE_3
0.1uF VSSCORE_1 9 34 PA1/INT1# 0.1uF
CHB TS Input D1_DATA0
TW9910_DATA[0] 10 33 PA0/INT0#
CHB_TS_CLK
CI0_CLK 11
0xF2 32 VCC_4
CI0_DATA 12 31 CTL2/FLAGC
CHB_TS_DATA
CI0_VALID 13 30 SPI_MODE[1]
CHB_TS_VAL
CI0_SOP 14 29 VDDIO_3
CHB_TS_SYNC EAN60750501
C2731
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0.1uF
VDDIO_2
CI1_DATA
CI1_VAILD
CI1_CLK
CI1_SOP
SDA0
SCL0
VDDCORE_2
SCK
SS
VSSIO_2
MISO
MOSI
SPI_MODE[0]
C2711
0.1uF
0.1uF
C2713
100
100
R2711
R2712
SDA1_3.3V
SCL1_3.3V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. GCHB 27 31

< PANASONIC Demod.>
22 R3011
OPT FE_TS_VAL
+1.2V_SBTVD
22 R3012
FE_TS_SYN
+3.3V_SBTVD 22 R3009
0.1uF C3014
C3015
C3019
C3020
C3023
FE_TS_SERIAL +1.26V_TU +1.2V_SBTVD
C3010 22 R3010
0.1uF FE_TS_CLK
0.01uF
16V 25V 25V 50V 16V
16V
1uF
1uF
0.1uF
L3001
BLM18PG121SN1D
+3.3V_Normal C3030 C3033

0.1uF 0.1uF
HDVDDL1
VDDH_5
VDDL_7
VSS_11
HDVDDH
VSS_10
VDDH_4
AGC_S
TEST0
HDVPP
TEST2
TEST1
GPO2
DENB
PCKB
SDOB
SCKB
NC_4
NC_3
DENA
PCKA
SDOA
GPI2
SCKA
RON
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VSS_1 1 75 VSS_9 R3016

AVDD_S INTB OPT R3017
2 74
AII_S INTA 2.2K 2.2K
0.1uF 3 73
C3008 OPT
AIQ_S 4 72 SADR
AVSS_S 5 71 VDDH_3
VRT_S SCL C3027 0.1uF 22R3015
6 70 SCL1_3.3V
VRB_S SDA
7 69
22 SDA1_3.3V +3.3V_TU +3.3V_SBTVD
TCPO_S VSS_8 R3014
VDDL_1
8
9
IC3000 68
67 HDVDDL0
0.1uF R3003 2.2K MSCL_S SADR_S C3026 0.1uF
C3007 10 66
R3004 2.2K MSDA_S 11 MN884433 65 NC_2
L3000
BLM18PG121SN1D
VSS_2 12 64 SADR_T
VSSH 13 63 VDDL_6
0.1uF PSEL VSS_7 C3025 0.1uF C3029 C3031
C3005 14 62 C3032
ZSEL ERRB 0.1uF 0.1uF 10uF
15 61 10V
VDDL_2 16 60 SYNCB
0.1uF ACKI ERRA
C3006 17 59
R3002 TCPO_T 18 58 SYNCA
10K 1% IR_T TDO
19 57
VRT_T 20 56 CSEL1
0.1uF
C3000
C3003 0.1uF VRB_T CSEL0

21 55
16V
C3004 0.1uF AVDD_T TMS

22 54
R3000 100 C3002 0.1uF AIN_T TRST
TUNER_IF_N 23 53
AIP_T 24 52 VDDL_5
TUNER_IF_P C3024 0.1uF
C3001
R3001 100 AVSS_T 25 51 VSS_6

16V
0.1uF
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+3.3V_Normal
VSS_3
MSCL_T
MSDA_T
VDDH_1
GPO1
AGCI_T
AGCR_T
GPO0
VDDL_3
VSS_4
XO
XI
VDDH_2
GPI1
GPI0
TEST4
SHVPP
SHVDDH
NC_1
VSS_5
VDDL_4
TCK
TDI
NRST
TEST3
Close to the demod

R3013
OPT
2.7K
R3007 2.2K
R3006 2.2K
DEMOD_RESET
C3028
0.1uF
C3011 C3013 C3017 C3021 C3022 16V
0.1uF 0.1uF 0.1uF
0.1uF
0.1uF
16V 16V 16V 16V 16V
C3018
0.1uF
R3008 16V
1M
ISDB_IF_AGC
R3005 10K X3000

25MHz
C3009
0.1uF C3012 C3016
30pF 30pF
50V 50V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ATSC demod 31 31

OPT +3.3V_Normal
R3260 0 3V3
OPERATIONAL MODE TMODE[3:0]
IC3203
MC14053BDR2G
M_REMOTE & MOD_ROM_DL Normal Mode 0000
SSPLL Test Mode 0001

Y1 VDD
R3295
R3287
OPT R3290
OPT R3292
M_REMOTE_TX 1 16 0010
OPT 3.3K
3.3K
3.3K
OPT 3.3K
DISP PLL Test Mode
C3205
Y0 Y 0.1uF LVDS_RX Test Mode 0011
+5V_3D P_+5V 2 15 R3283 0
MOD_ROM_TX REMOTE_OR_MODULE_TX WIRELESS_SW_CTRL SELECT PIN STATUS TMODE[3]
R3284 0 LVDS_TX Test Mode 0100
TMODE[2]
Z1 X R3285 0
EAM38058401 3 14 TMODE[1]
REMOTE_OR_MODULE_RX HIGH X1/Y1/Z1 M_REMOTE CONNECT --> BCM UART R3286 0 MBIST Mode 0101
L3200 TMODE[0]
CB4532UK121E Scan Test Mode (Normal)
Z X1 0110
R3293
R3288
R3291
R3296
4 13
LOW X0/Y0/Z0 MODULE ROM DL CONNECT --> BCM UART
3.3K
3.3K
3.3K
3.3K
M_REMOTE_RX
R3261 +3.3V_Normal Scan Test Mode (Adaptive) 0111
C3200 C3201 C3202 Z0 X0 0 OPT
10uF 0.1uF 100pF 5 12 MOD_ROM_RX DDR2PHY Test Mode 1001
10V 16V 50V
4.7K
INH A Function Test Mode 1011
R3262
6 11
R3259 0 VEE B
7 10 REMOTE_SW_CTRL
EJTAG
VSS C
47K
OPT
R3263
8 9
FLASH_WP_3D
3V3
L/R_INDICATOR
/JTAG_TRST
JTAG_TCLK
JTAG_TDO
JTAG_TDI
JTAG_TMS
UART_TXD_3D
UART_RXD_3D
OPT R3223
2.7K
MOD_SCL
MOD_SCL
MOD_SDA
MOD_SDA
/SPI_CS
R3204
2Mb(256KB) serial Flash
SPI_DO
SPI_CK
SPI_DI
0
3V3
Serial FLASH MEMORY 3V3 1/16W
for BOOT 5%
IC3201
W25X20BVSNIG RS232C 3V3
R3240
R3241
TMODE[0]
TMODE[1]
TMODE[2]
TMODE[3]
C3204
4.7K
4.7K
FLASH_WP_3D
0.1uF
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22 R3208
22 R3210
22 R3211
22 R3207
22 R3209
16V
22
22
CS VCC
R3264
/SPI_CS 1 8
OPT
10K
R3247
R3252
R3250
R3253
R3243
R3244
R3245
R3246
R3248
R3249
R3251
R3254
R3255
R3256
R3257
R3258
R3205
R3206
DO HOLD R3242
SPI_DO 2 7
R3239
10K 3.3K
BOOT_SEL BOOT MODE
R3265
WP CLK
3 6
10K
SPI_CK High WITHOUT SPI Flash ROM
C
A16
B16
C16
D16
A15
B15
C15
D15
A14
B14
C14
D14
A13
B13
C13
D13
A12
B12
C12
D12
A11
B11
C11
D11
A10
B10
C10
D10
B Q3204 GND DIO
4 5 Low WITH SPI Flash ROM
A9
B9
C9
D9
A8
B8
C8
D8
A7
B7
C7
D7
A6
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
D4
A3
KRC103S SPI_DI
OPT
E
UART_TXD
UART_RXD
SPI_CS
SPI_SCLK
SPI_DO
SPI_DI
SCL
SDA
SCL_M
SDA_M
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
TDI
TMS
TRST
TDO
TCK
TEST_SE
TMODE[0]
TMODE[1]
TMODE[2]
TMODE[3]
BOOT_SEL
B2 U18 EJTAG
3V3
R3272
R3238 TE4+
TE4P RA1N TXA0N
100
0
B1 U17
TE4-
TE4N RA1P TXA0P
B3 T18
R3273
3D_SYNC_OUT
TD4+
TD4P RB1N TXA1N
100
R3236
OPT C3 T17 R3217
3.3K
3V3
22K TD4-
TD4N RB1P TXA1P R3222
R3213 R3215 R3216
OPT
C1 R18 3.3K OPT
3.3K 3.3K 3.3K
3.3K
P3201
YFDW254-14S
S
R3274
TCLK4+
TCLK4P RC1N TXA2N OPT R3212
100
3.3K R3221
G C2 R17 R3214
3.3K OPT
R3301
TCLK4-
TCLK4N RC1P TXA2P
3.3K
R3237 Q3203 nTRST GND

OPT
220 1 2
OPT AO3407A D D2 P18 /JTAG_TRST
JTAG_TDI
TDI 3 4 GND
R3277
OPT TC4+
TC4P RCLK1N TXACLKN
100
R3235 C JTAG_TDO TDO 5 6 GND
10K
3D_SYNC D1 P17 JTAG_TMS
TMS 7 8 GND
OPT B MMBT3904(NXP)
Q3202
TC4-
TC4N RCLK1P TXACLKP
TCK 9 10 GND
OPT D3 N18 JTAG_TCLK
0 R3218
R3275
OPT nRST NC
C3203 11 12
E 0.01uF
TB4+
TB4P RD1N TXA3N
100
DINT 13 14 VIO
E3 N17
TB4-
TB4N RD1P TXA3P
1K
E1 M18 R3219
R3276
TA4+
TA4P RE1N TXA4N
100
E2 M17
TA4-
TA4N RE1P TXA4P
F2 L18
R3266
TE3+
TE3P RA2N TXB0N
100
F1 L17
TE3-
TE3N RA2P TXB0P
F3 K18
R3267
TD3+
TD3P
IC3202 RB2N TXB1N
100
G3 K17
TD3-
TD3N RB2P TXB1P
G1 J18
R3268
TCLK3+
TCLK3P RC2N TXB2N
100
G2 J17
LVDS OUTPUT TCLK3-
H2
TCLK3N RC2P
H18
TXB2P
R3269
TC3+
TC3P RCLK2N TXBCLKN
100
H1 H17
3V3
TC3-
H3
TC3N
LG8300 RCLK2P
G18
TXBCLKP
R3270
3V3 TB3+
TB3P RD2N TXB3N
100
J3 G17
TB3-
TB3N RD2P TXB3P
J1 F18
R3271
C3206
TA3+
TA3P RE2N TXB4N
27pF
100
R3228 R3229 R3232
J2 F17
TA3-
TA3N RE2P TXB4P
OPT
OPT
81
OPT
R3200 R3201 R3203 4.7K 0 4.7K
1%
K2
OPT
OPT
80
OPT
G
OPT
4.7K
25MHz
X3200
4.7K 0 PC_SER_CLK 79
R3282
TE2+
TE2P
1M
PC_SER_DATA
78
K1 A17
G
OPT
MOD_SCL 77
S
DISP_EN
TE2-
TE2N CLK_XIN 3V3
MOD_SDA
2N7002(F)Q3201
R3230
76
K3 B18
75
S
0
TD2+
TD2P CLK_XOUT
Q3200 74
L3 B17
C3207
27pF
2N7002(F) 73 TD2-
TD2N PO_RST_N
R3202
0
72
L1
71 TCLK2+
TCLK2P
R3300
3.3K
R3278
TA1-
70
L2 V2 0
/3D_ASIC_RESET_SWITCH
69 TCLK2-
TCLK2N LR_SYNC
OPT
TA1+
TB1-
68
M2 V3 0 R3279
67
TB1+
TC2+
TC2P EMITTER_PULSE /3D_ASIC_RESET
TC1-
66
M1
65
TC1+
TC2-
TC2N R3280
64
63
M3 0
3D_SYNC_OUT
TCLK1-
TB2+
TB2P
TCLK1+
62
61
N3 0 R3281
TB2-
TB2N
R3220
OPT
2.7K
TD1-
60
59
N1
TD1+
TA2+
TA2P
TE1-
58
57
N2
TE1+
56
TA2-
TA2N
55
TA2-
54
53
P2
TA2+
TE1+
TE1P
TB2-
52
51
P1
TB2+
TE1-
TE1N
TC2-
50
49
P3
TC2+
TD1+
TD1P
48
47
R3
TCLK2-
TD1-
TD1N
TCLK2+
46
45
R1
TCLK1+
TCLK1P
TD2-
44
43
R2
TD2+
TCLK1-
TCLK1N
TE2-
42
41
T2
TE2+
TC1+
TC1P
40
39
T1
TC1-
TC1N
TA3-
38
37
T3
TA3+
TB1+
TB1P
TB3-
36
35
U3
TB3+
TB1-
TB1N
TC3-
34
33
U1
TA1+
TA1P
DDR_ADDR[10]
DDR_ADDR[11]
DDR_ADDR[12]
DDR_DQS_N[0]
DDR_DQS_N[1]
DDR_TDOUT[0]
DDR_TDOUT[1]
TC3+
32
U2
DDR_ADDR[0]
DDR_ADDR[1]
DDR_ADDR[2]
DDR_ADDR[3]
DDR_ADDR[4]
DDR_ADDR[5]
DDR_ADDR[6]
DDR_ADDR[7]
DDR_ADDR[8]
DDR_ADDR[9]
31 TA1-
TA1N
DDR_DQS[0]
DDR_DQS[1]
DDR_DQ[10]
DDR_DQ[11]
DDR_DQ[12]
DDR_DQ[13]
DDR_DQ[14]
DDR_DQ[15]
TCLK3-
30
DDR_BA[0]
DDR_BA[1]
DDR_RAS_N
DDR_CAS_N
DDR_DM[0]
DDR_DM[1]
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[6]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[9]
DDR_TAOUT
TCLK3+
29
DDR_CK_N
DDR_CS_N
DDR_WE_N
28
DDR_CKE
DDR_ODT
TD3-
DDR_CK
27
TD3+
26
TE3-
25
TE3+
24
23
22
TA4-
21
TA4+
20
U5
V8
V5
U8
R6
T8
T6
R8
R7
U7
R9
T7
V7
U9
T9
V6
U6
V9
R5
U4
V4
T5
R10
V14
V12
U14
U12
R15
T12
V15
T15
U16
T16
R16
V16
T14
U15
T13
V11
U13
U11
T11
V13
R12
R13
U10
T10
V10
TB4-
19
TB4+
18
TC4-
17
TC4+ 3V3
16
15
TCLK4-
TCLK4+
14
13
N.C.
MAIN_SDDR_DQ[10]
MAIN_SDDR_DQ[11]
MAIN_SDDR_DQ[12]
MAIN_SDDR_DQ[13]
MAIN_SDDR_DQ[14]
MAIN_SDDR_DQ[15]
R3294
R3299
12
MAIN_SDDR_DQ[0]
MAIN_SDDR_DQ[1]
MAIN_SDDR_DQ[2]
MAIN_SDDR_DQ[3]
MAIN_SDDR_DQ[4]
MAIN_SDDR_DQ[5]
MAIN_SDDR_DQ[6]
MAIN_SDDR_DQ[7]
MAIN_SDDR_DQ[8]
MAIN_SDDR_DQ[9]
4.7K
MAIN_DDR_A[10]
MAIN_DDR_A[11]
MAIN_DDR_A[12]
3V3 TD4-
MAIN_DDR_A[0]
MAIN_DDR_A[1]
MAIN_DDR_A[2]
MAIN_DDR_A[3]
MAIN_DDR_A[4]
MAIN_DDR_A[5]
MAIN_DDR_A[6]
MAIN_DDR_A[7]
MAIN_DDR_A[8]
MAIN_DDR_A[9]
11
1K
IC3204
TD4+ OPT
10 KIA7029AF
TE4- SW3200
9 JTP-1127WEM R3289
MAIN_DDR_BA[0]
MAIN_DDR_BA[1]
TE4+
/MAIN_DDR_DQS[0]
/MAIN_DDR_DQS[1]
8 330
/MAIN_DDR2_CLK
MAIN_DDR_DQS[1]
MAIN_DDR_DQS[0]
R3231 R3233 1 2 I 1 3 O
MAIN_DDR2_CKE
/MAIN_DDR_RAS
/MAIN_DDR_CAS
MAIN_DDR2_CLK
MAIN_DDR_DM[0]
MAIN_DDR_DM[1]
/3D_ASIC_RESET_SWITCH
/MAIN_DDR_CS
/MAIN_DDR_WE
MAIN_DDR2_ODT
7
2
4.7K 4.7K 6 3 4
C3208 G C3210
5
MOD_ROM_TX 10uF 0.1uF
4 MAIN_DDR_A[12-0] 16V 16V
MOD_ROM_RX R3234 22 3
3D_SYNC_IN 2
1
104060-8017 MAIN_SDDR_DQ[15-0]
P3200

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 3D_ASIC 32 33

1V0
DDR_VREF0_3D C1762 C1763 C1764 C1765 C1766 C1768 C1777 C1788 C1789 C1799 C1805 C1812 C1813 C1815 C1817 C1820 C1821
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
C1709 C1711 IC1702

0.1uF 470pF AR306
MAIN_SDDR_DQ[15-0]
16V 50V W9725G6JB-25 22
SDDR_DQ[5] MAIN_SDDR_DQ[5]
SDDR_DQ[2] MAIN_SDDR_DQ[2]
1V8
VREF DQ0 SDDR_DQ[0] SDDR_DQ[0] MAIN_SDDR_DQ[0]
DDR_A[12-0] J2 G8
SDDR_DQ[1] SDDR_DQ[7] MAIN_SDDR_DQ[7]
DDR_A[0] A0
G2
H7
DQ1
DQ2 SDDR_DQ[2] AR307 IC3202
M8 SDDR_DQ[3] 22
DDR_A[1]
DDR_A[2]
A1
A2
M3
H3
H1
DQ3
DQ4 SDDR_DQ[4]
SDDR_DQ[13]
SDDR_DQ[10]
MAIN_SDDR_DQ[13]
MAIN_SDDR_DQ[10]
1V0
LG8300 C1767
0.1uF
C1776
0.1uF
C1786 C1787
0.1uF
C1798
0.1uF
C1804
0.1uF
C1810 C1811
0.1uF
C1814
0.1uF
C1816 C1818 C1819
M7 DQ5 SDDR_DQ[5] 0.1uF 0.1uF 0.1uF 10uF 10uF
DDR_A[3] H9 SDDR_DQ[8] MAIN_SDDR_DQ[8]
SDDR_DQ[15-0]
A3 N2 SDDR_DQ[6] 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
DDR_A[4] F1 DQ6 SDDR_DQ[15] MAIN_SDDR_DQ[15]
A4 N8 SDDR_DQ[7]
DDR_A[5] F9 DQ7
DDR_A[6]
A5 N3
C8 DQ8 SDDR_DQ[8]
AR308
A2
DDR_A[7]
A6 N7
C2 DQ9 SDDR_DQ[9]
22
GND_0
DDR_A[8]
A7 P2
D7 DQ10 SDDR_DQ[10] SDDR_DQ[14] MAIN_SDDR_DQ[14] F6 F5
DDR_A[9]
A8 P8
D3 DQ11 SDDR_DQ[11] SDDR_DQ[9] MAIN_SDDR_DQ[9] VDD10_1 GND_1
DDR_A[10]
A9 P3
D1 DQ12 SDDR_DQ[12] SDDR_DQ[11] MAIN_SDDR_DQ[11] F13 F7
DDR_A[11]
A10/AP M2
D9 DQ13 SDDR_DQ[13] SDDR_DQ[12] MAIN_SDDR_DQ[12] VDD10_2 GND_2
DDR_A[12]
A11 P7
B1 DQ14 SDDR_DQ[14] G6 F8 3V3
3V3_LRX_AVDD33
A12 R2
B9 DQ15 SDDR_DQ[15]
1V8 AR309
VDD10_3 GND_3
22
G7 F9
DDR_BA[0] BA0 L2
SDDR_DQ[3] MAIN_SDDR_DQ[3] VDD10_4 GND_4
DDR_BA[1] BA1 L3
SDDR_DQ[4] MAIN_SDDR_DQ[4] G8 F10 L1712
120-ohm
A1 VDD_5 SDDR_DQ[1] MAIN_SDDR_DQ[1] VDD10_5 GND_5
DDR2_CLK E1 VDD_4
C1719 SDDR_DQ[6] MAIN_SDDR_DQ[6] G9 F11 C1775 C1784 C1785
R1700
CLK J8 J9 VDD_3 100pF VDD10_6 GND_6 10uF 0.1uF 0.1uF

100
/DDR2_CLK
CLK K8 M9 VDD_2 50V G10 F12 10V 16V 16V
CKE K2 R1 VDD_1
VDD10_7 GND_7
DDR2_CKE G11 F14
DDR2_ODT ODT K9
VDD10_8 GND_8
/DDR_CS CS L8 A9 VDDQ_10 G12 G5 3V3_LTX_AVDD33
/DDR_RAS RAS K7 C1 VDDQ_9 VDD10_9 GND_9
/DDR_CAS CAS L7 C3 VDDQ_8 G13 G14
/DDR_WE WE K3 C7 VDDQ_7 VDD10_10 GND_10
C9 VDDQ_6 MAIN_DDR2_CLK
R344 22 H6 G16 L1711
120-ohm
E9 VDDQ_5 DDR2_CLK VDD10_11 GND_11
DDR_DQS[0] LDQS F7
G1 VDDQ_4 /MAIN_DDR2_CLK
R345 22 H13 H7 C1774 C1782 C1783 C1797 C1803 C1809
DDR_DQS[1] UDQS B7
G3 VDDQ_3 /DDR2_CLK VDD10_12 GND_12 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
G7 VDDQ_2 MAIN_DDR_DQS[0]
R346 22
DDR_DQS[0]
J6 H8 10V 16V 16V 16V 16V 16V
ASIC_DDR_DM[0] LDM F3 G9 VDDQ_1 R347 22

VDD10_13 GND_13
ASIC_DDR_DM[1] UDM B3
MAIN_DDR_DQS[1] DDR_DQS[1] J13 H9
MAIN_DDR_DM[0]
R348 22
ASIC_DDR_DM[0]
VDD10_14 GND_14
R349 22
K6 H10 VDD_3.3V
/DDR_DQS[0] LDQS E8 A3 VSS_5 MAIN_DDR_DM[1] ASIC_DDR_DM[1] VDD10_15 GND_15
/DDR_DQS[1] UDQS A8 E3 VSS_4
/MAIN_DDR_DQS[0]
R350 22
/DDR_DQS[0]
K13 H11
J3 VSS_3
R351 22
VDD10_16 GND_16 L1710
NC_4 L1
N1 VSS_2 /MAIN_DDR_DQS[1] /DDR_DQS[1] L6 H12 120-ohm
NC_5 R3
P9 VSS_1
VDD10_17 GND_17 C1773
NC_6 R7 AR301 22
L7 H14 10uF
C1781
0.1uF
C1795
0.1uF
C1796
0.1uF
C1802
0.1uF
C1808
0.1uF
VDD10_18 GND_18 10V 16V 16V 16V 16V 16V
B2 VSSQ_10 /MAIN_DDR_WE /DDR_WE L8 H15
NC_1 A2
B8 VSSQ_9 MAIN_DDR2_CKE DDR2_CKE VDD10_19 GND_19
NC_2 E2
A7 VSSQ_8 MAIN_DDR_BA[1] DDR_BA[1] L9 H16
NC_3 R8
D2 VSSQ_7 MAIN_DDR_BA[0]
AR302 22
DDR_BA[0] VDD10_20 GND_20
D8 VSSQ_6 L10 J7 PLL_VDD_3.3V
VSSDL E7 VSSQ_5 MAIN_DDR_A[2] DDR_A[2] VDD10_21 GND_21
J7
F2 VSSQ_4 MAIN_DDR_A[0] DDR_A[0] L11 J8 L1709
F8 VSSQ_3 /MAIN_DDR_RAS /DDR_RAS VDD10_22 GND_22 120-ohm
H2 VSSQ_2 MAIN_DDR2_ODT
AR303 22
DDR2_ODT L12 J9 C1772
VDDL J1 H8 VSSQ_1 VDD10_23 GND_23 10uF
C1780
0.1uF
C1793
0.1uF
C1794
0.1uF
C1801
0.1uF
C1807
0.1uF
MAIN_DDR_A[1] DDR_A[1] L13 J10 10V 16V 16V 16V 16V 16V
MAIN_DDR_A[3] DDR_A[3] VDD10_24 GND_24
MAIN_DDR_A[12] DDR_A[12] M6 J11
MAIN_DDR_A[9]
AR304 22
DDR_A[9] VDD10_25 GND_25
LTX_VDD10
M13 J12
MAIN_DDR_A[10] DDR_A[10] VDD10_26 GND_26
MAIN_DDR_A[5] DDR_A[5] J14
MAIN_DDR_A[7] DDR_A[7] GND_27 1V0
LTX_VDD10
MAIN_DDR_A[11] DDR_A[11] H5 J15
AR305 22 LTX_VDD10_1 GND_28 L1708
MAIN_DDR_A[8] DDR_A[8]
J5 J16 120-ohm
LTX_VDD10_2 GND_29
K5 K7 C1771
10uF
C1779
0.1uF
C1791
0.1uF
C1792
0.1uF
C1800
0.1uF
C1806
0.1uF
/MAIN_DDR_CAS /DDR_CAS
LTX_VDD10_3 GND_30 10V 16V 16V 16V 16V 16V
R352 22
L5 K8
/MAIN_DDR_CS
/DDR_CS
LTX_VDD10_4 GND_31
M5 K9
LTX_VDD10_5 GND_32
1V8 K10
VDD_3.3V GND_33
K11 DDR_VREF_LG8300
GND_34
E5 K12
C1728 C1738 C1739
C1723
10uF
C1725
0.1uF
C1727
0.1uF 0.1uF
C1731
0.1uF 0.1uF 0.1uF
C1742
0.1uF
C1745
0.1uF
C1746
0.1uF
C1749
0.1uF
C1751
0.1uF
C1889
0.1uF
C1890
0.1uF
C1756
0.1uF
C1853
0.1uF
C1759
0.1uF
C1761
0.1uF
VDD33_1 GND_35
1V8 1V8 10V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V E6 K14
VDD33_2 GND_36 C1769 C1770 C1778 C1790
E7 K15 10uF 0.1uF 0.1uF 0.1uF
VDD33_3 GND_37 10V 16V 16V 16V
E8 K16
VDD33_4 GND_38
DDR_VREF_LG8300 DDR_VREF0_3D E9 L14
R1712 VDD33_5 GND_39
4.7K R1714 E10 L15
1% 4.7K
1% 3.3V TO 1.8V VDD33_6 GND_40
E11 M7
R1713 R1715 VDD33_7 GND_41
4.7K
1%
4.7K
1%
3V3 E12 M8
VDD33_8 GND_42
C1891 C1892
0.1uF 1000pF
C1893 C1894
0.1uF1000pF E13 M9
1V8 VDD33_9 GND_43
E14 M10
R359
IC1704 VDD33_10 GND_44
0 AZ1117BH-1.8TRE1 E15 M11
IN ADJ/GND VDD33_11 GND_45
F15 M12
OPT
R360
0 VDD33_12 GND_46
C3304
22uF
C3305
0.1uF OUT G15 M14
Close to LG8300 Close to DDR2(IC1702) 25V 16V
C3308 C3306
3V3_LRX_AVDD33 VDD33_13 GND_47
10uF 10uF
C3307
0.1uF
M15
6.3V 6.3V 16V GND_48
R361
L16 N5
1 LRX_AVDD33_1 GND_49
N16 N6
3V3_LTX_AVDD33 LRX_AVDD33_2 GND_50
N15
GND_51
E4 P5
LTX_AVDD33_1 GND_52
G4 P11
LTX_AVDD33_2 GND_53
L4 R4
LTX_AVDD33_3 GND_54
N4 R14
LTX_AVDD33_4 GND_55
J4
LTX_AVDD33_5
M16
DDR_VREF_LG8300
LRX_AVSS33_1
P16
LRX_AVSS33_2
T4
DDR_VREF0
R11 F4
DDR_VREF1 LTX_AVSS33_1
V17 H4
1V8 DDR_VREF2 LTX_AVSS33_2
K4
LTX_AVSS33_3
N7 M4
DDR_VDDQ_1 LTX_AVSS33_4
N8 P4
DDR_VDDQ_2 LTX_AVSS33_5
N9
DDR_VDDQ_3
N10
DDR_VDDQ_4
N11 C17
DDR_VDDQ_5 DDRPLL_AVSS33
5V TO 1.0V N12 D17
DDR_VDDQ_6 SYSPLL_AVSS33
N13 E16
CLOSE TO VIN AND AGND PIN 1V0 DDR_VDDQ_7 ADPLL_AVSS33
N14 F16
MLB-201209-0120P-N2
R1703 10K DDR_VDDQ_8 SSPLL_AVSS33 PLL_VDD_3.3V

+5V_3D P6
IC1700 DDR_VDDQ_9
L1703
AOZ1072AI-3 P7 C18
L1702 DDR_VDDQ_10 DDRPLL_AVDD33
L1700 PGND LX_2 3.6uH P8 D18
CIC21J501NE
1 8
DDR_VDDQ_11 SYSPLL_AVDD33
NR8040T3R6N P9 E17
VIN
2 7
LX_1 1% DDR_VDDQ_12 SSPLL_AVDD33
C1710 R1708
3.3K OPT
P10 E18
0.1uF AGND 2A EN OPT
R1
C1718 DDR_VDDQ_13 ADPLL_AVDD33
C1701 C1704
16V 3 6
R1705 C1714 C1702 100pF C1720 P12
10uF 10uF 10K 22uF 22uF 50V
0.1uF
16V
DDR_VDDQ_14
10V 10V
FB
4 5
COMP 10V 10V
OPT
P13
9.1K DDR_VDDQ_15
R1704
2200pF
C1713
P14
DDR_VDDQ_16
R1707 P15
12K
R2
DDR_VDDQ_17
1%
Vout=0.8*(1+R1/R2)

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Great Company Great People
BBTV
BBTV (PU12A)
(PU12A) Training
Training manual
manual
Contents
- Block Diagram
- Power Flow Diagram
- Trouble Shooting Guide
2010.12.17 PDP ATSC Gr. LEE SUNG KEU

Trouble Shooting Guide for LG Service Man
Great Company Great People 5/39

SET Layout
Z Board
Power Board
Y Board
ASIC
Main
X board Emitter
50PZ950-UA model image 50PX950-UA model block diagram
Point
1. 3D RF emitter sub Assy and wafer

- 3D RF emitter make 3D sync for 3D Active glasses
- RF emitter signal form ASIC to Main board and it connect to RF emitter Assy through 12pin wafer on Main board

SET Layout
Z Board
Power Board
Y Board
ASIC
Main
X board Emitter
60PZ950-UA model image 50PX950-UA model block diagram
Point
1. 3D RF emitter sub Assy and wafer

- 3D RF emitter make 3D sync for 3D Active glasses
- RF emitter signal form ASIC to Main board and it connect to RF emitter Assy through 12pin wafer on Main board

Main board (GP3)
Power 18pin
USB
Speaker 4pin
USB
LVDS 80P HDMI 4

BCM35230 HDMI 3
` HDMI 2
IR/Control HDMI 1
RGB RS232
wireless
LAN Side AV
Tuner
RF Emitter Rear AV
IR
Component
Main board for 3D block diagram SPDIF
GP3 Main board
PC Audio

1. GP3_BCM_PDP Block Diagram
(Front-end) (System + Scalar)
US NAND DDR3 X-TAL

NAND DDR3 X-TAL
IF 8Gbit
8Gbit 2GB
2GB 54MHz
54MHz
ATSC/ NTSC CVBS1/
SANYO SIF_LIVE
CVBS1,2 1080P
UDA55AL LVDS
LR1,2 L/R Indicator
GPIO77
KOR
COMP_LR1,2
IF
ATSC/ NTSC
LGIT CVBS1/ RGB_LR BCM_SPDIF
SIF_LIVE SPDIF
TDSB-H001F
CHB LGE35230
LGE35230
IF Ethernet LAN
BRA EXT_IN BCM_I2S
IF
ISDB-T HDMI
LGIT CVBS1/ USB2
CABLE
TDTR-T036F SIF_LIVE SIF_LIVE
USB1
(External Input/Output) (3DF_Block) (Etc)
CVBS1/LR Serial BCM_I2S Audio_AMP

Audio_AMP
Serial Flash
Flash DDR2
DDR2 STA368BWG
CVBS2/LR 2Mbit 256Mb STA368BWG
COMP1/2 2Mbit 256Mb
EXT_IN
L/R Indicator
COMP1_LR NEC CEC Control
NEC Micom
Micom
1080P(L) uPD
COMP2_LR 1080P uPD
RGB_LR LG8300_3DF_ASIC
LG8300_3DF_ASIC 1080P(R)
RGB
3D_Sync
4:1 Switch
SII9287B
HDMI Wireless
3D_Sync Wireless
BCM_SPDIF RF_Tx
RF_Tx Interface
Interface
HDMI 1.3 x 4

2. 3DF Block Diagram
RF_Shutter_Glasses
DDR2 X-tal Serial_Flash

RF_Tx
RF_Tx (256Mbit) (25MHz) (2Mbit)
3D_GPIO 3D_SYNC_OUT
3D_SYNC
3
EMITTER_PULSE
LVDS 2Ch
I2C
I2C Left (2D):
1920x1080/60Hz
I2C_M
LVDS ( 80Pin )
L/R DETECT 3DF_ASIC
3DF_ASIC PDP
BCM35230
BCM35230
GPIO[2] PDP
3DF_ASIC RESET
PO_RST_N
LG8300
LG8300
LVDS 2Ch
LVDS 2Ch
Right : 1920x1080
3D : 1920x1080/60Hz 60Hz
1920x1080/60Hz
(S/S, T/B, C/B, F/S)
1920x1080/48Hz
(F/S)
■ Processing
LVDS-Rx , Dual Link 10 bit (25~85MHz)
LVDS-Tx , Quad Link 10 bit (25~85MHz)
DDR2-PHY : 333MHz (Max.350MHz)
(DDR2 x16 1ea, 256Mb)
GPIO#32

Power-Up Boot Fail Trouble Shooting
NTSC/ATSC
TUNER DDR2 X-tal Serial_Flash
X-tal NAND Flash
DDR3 (2GB) (256Mbit) (25MHz) (2Mbit)
TDVJ-H101F (54MHz) (8GB)
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Buffer Buffer 1920x1080/60Hz
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
CVBS(ATV) Right(2D) :
1920x1080/60Hz
CVBS waveform SPDIF Out

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
R/G/B Video (Digital AMP)
RGB-PC Front I2S
DDC End
Rear AV CVBS LGE35230 HDMI CEC
Side AV CVBS
Reset 24C16
NEC
AV1,2 L/R L/R RX/TX I2C Micom
Local
COMP 1,2 L/R L/R Audio KEY
RGB-PC Front IR
Audio In End RS-232C
UART
UART
SIF
HDMI SW DP/DM
TMDS/DDC HDMI USB 2.0
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Power-Up Boot Fail Trouble Shooting
Check P500 All N Check Power connector Y Replace Power board

Voltage Level (ST_5V) OK ?
Check L501 (pin3) Output N

Replace L501
Voltage Level (P_5V)
Check IC501(pin8) N Replace IC501

Voltage Level 0.9V
Check IC502 (pin2) N Replace IC502

Voltage Level 2.5V
Replace IC101

No OSD Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

No OSD Trouble Shooting
Check P400 N Check GPIO Path of IC701

5V_ON
Check SMPS Vs,Va, 5V,17V N Replace Power Board
Check IC
#62(TXAC1-) , #61(TXAC1+) ,
N Maybe BCM has problems
#46(TXAC2-) , #45(TXAC2+),
Replace IC3202
#30(TXAC3-) ,#29(TXAC3+)
,#14(TXB4-) , #13(TXBC4+)
Y
Check LVDS Cable for damage or Y

Replace Cable
open conductors.
Check PDP Module Electrical Specifications

Control board Power Supply Sequence
Check CAS
Refer to Module CAS Input Signal Timing Specification
Control Signal Register
It should satisfy the Pixel Clock on CAS.

No OSD Trouble Shooting (Module Power Sequence)
< 50R3 >

Module Control Trouble Shooting
“TILT” on Adjust Remocon N N

PDP Module Power is OK? Check SMPS & cable
: PDP internal pattern displays?
SCL
Y Y
Replace PDP Module
SDA
PDP Module is OK.

N Check Signal N
Check P902 SCL,SDA line SCL,SDA Replace X3200
: X3200 output
line R3230, R3202
< Sample Signal on R2717, R2703 >
ACK signal Check

Low : OK
High : Error

Digital TV Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Digital TV Video Trouble Shooting
Check RF Cable
Check Tuner 5V,7V Power N Replace IC500 or IC506

IC500(7V),IC506(5V)
Check IF_P,IF_N (TU2103) N Maybe Tuner has problems

R17, P18 : Replace Tuner
N
Check IC
#62(TXAC1-) , #61(TXAC1+) , Maybe BCM has problems
#46(TXAC2-) , #45(TXAC2+), Replace IC3202
#30(TXAC3-) ,#29(TXAC3+)
,#14(TXB4-) , #13(TXBC4+)
Check PDP Module

Control board
Refer to Module CAS

Analog TV Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Analog TV Video Trouble Shooting
Check RF Cable
Check Tuner 5V,7V Power N

Replace IC500 or IC506
IC500(7V),IC506(5V)
Check CVBS signal N Replace Tuner(TU2103)

TU2103 #11 Pin
Replace BCM35230(IC101)
< CVBS waveform – sample >

- Defend on the input signal.

Component Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Component Video Trouble Shooting
Check input signal format

Is it supported?
Check Component Cable
Check signal N Check the damage of JK1100

L1108~L1113 And Replace Connector
Y
※ Measured signals depend on the input signal.

RGB Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

RGB Video Trouble Shooting

Is it supported?
Check RGB Cable conductors for

damage
N Replace connector (P801).

Check P801
Check signal, Hsync, Vsync N Replace R801,R802

R801, R802
Check signal N Replace L803,L804,L805

L803,L804,L805
Replace BCM35230 ※ Measured signals depend on the input signal.

AV Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

AV Video Trouble Shooting

Is it supported?
Check AV Cable / S-Video Cable for damage or

open conductors
Check AV port of JK1100 (Rear) N Replace or reseat connector

Check JK1101 (Side)
Check signal N Replace Resistor

R1115(Rear AV), R1142 (Side AV)
※ Measured signals depend on the input signal.

HDMI Video Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

HDMI Video Trouble Shooting

Is it supported?
Check HDMI Cable for damage or open

conductors
Check JK701~JK703 for proper N Replace connector

connection or damage
Check EDID N EDID D/L

SVC REMOTCONTROL
Check HDMI SW(IC700) N Replace IC700

Power(R522) & I2C Signal(R752/3)

All Source Audio Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4
Great Company Great People 26/3\9

All Source Audio Trouble Shooting
Make sure you can’t hear any audio
Check BCM I2S Output N Replace IC501.

R1605~R1608
Check Power N Replace 17V(L1604), 3.3V(L1605)

17V(L1604), 3.3V(L1605)
Check IC16000 Status

N Replace IC1600
/PDN(#23), /Reset(#30) is High?
Check Signal (PWM) N

Replace L1600~L1603
L1600~L1603
Y
Check Connector N
Replace P1600
P1600
Y
Check speaker for damage. N Replace the Speaker

Digital TV Audio Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Digital TV Audio Trouble Shooting
N Follow procedure digital TV video

Check video output
trouble shooting (on page 15)
Follow procedure All source audio trouble N

shooting (on page 27) Replace BCM35230 (IC101)

Analog TV Audio Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Analog TV Audio Trouble Shooting
N Follow procedure analog TV video

Check video output
Check TU2103 (pin3) for 5V N Replace IC500 or IC506
Check SIF signal (TU2103 #9) N Replace Tuner
Check SIF signal (R2138) N Check SIF line
Follow procedure All source audio trouble

shooting (on page 27 < SIF waveform – sample >
Y
Replace BCM35230 (IC101)

Component / RGB / AV Audio Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

Component / RGB / AV Audio Trouble Shooting
Check Connector and cables

JK1100 (Component, AV Rear) N Replace connector or cable if
P801 (RGB) found damaged
JK1101 (AV Side)
Y
Check signal
L1100 / L1107 (Component1)
L1103 / L1104 (Component2) N
Replace the Resistor
R801 / R802 (RGB)
R1105 / R1106 (AV Rear)
R1101 / R1102 (AV Side)
Y
Follow procedure All source audio


HDMI Audio Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

HDMI Audio Trouble Shooting
N Re-download EDID data.

Check EDID
Follow procedure All source audio trouble

shooting (on page 27)

OPTIC Audio Out Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

OPTIC Audio Out Trouble Shooting
N Replace BCM35230 (IC101)

Check SPDIF signal (R803)
Check Signal (JK802 #3)
Replace JK802
< SPDIF waveform – sample >


USB Trouble Shooting
NTSC/ATSC
X-tal NAND Flash
IF waveform
LVDS ( 80Pin )
LVDS 2Ch
SIF CVBS
I2C Left (2D):
HD/SD 3DF_ASIC
3DF_ASIC
Video LG8300
LG8300
MAIN IF LVDS 2Ch
Encoder
1920x1080/60Hz

SIF Y/Cb/Cr
COMP1
Audio
Y/Cb/Cr MCLK
COMP2 DSP STA368
RGB-PC Front I2S
DDC End
Side AV CVBS
Reset 24C16
NEC
Local
RGB-PC Front IR
UART
UART
SIF
HDMI SW DP/DM
SII9287B
RX
RMII LAN
Side HDMI 1/2/3/4

USB Trouble Shooting
Check USB 2.0 Cable for damage or open

conductors
Check IC1200/1 voltage level 5V N Replace IC 1200 ,IC1201

(L1200/L12010)
Check P1200,P1201 N
Replace P1200,P1201
Replace BCM35230 (IC101)
• Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)

LG 60pz750-Ug Chassis Pu12a

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LG 60pz750-Ug Chassis Pu12a

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Formate disponibile

Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 60PZ750 60PZ750-UG

P/NO : MFL67006104(1103-REV00) Printed in Korea

SAFETY PRECAUTIONS ...........................................................................................................3

ADJUSTMENT INSTRUCTION ..................................................................................................6

BLOCK DIAGRAM ...................................................................................................................13

EXPLODED VIEW ...................................................................................................................14

CIRCUIT DIAGRAM .....................................................................................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Good Earth Ground

1. Application Range 4. MAC Address and ESN Key Write

Caution) When still image is displayed for a period of 20 minutes

3. Adjustment items - Load button click(2) for MAC Address write.

3-2. Final assembly adjustment

6-2. Equipment & Condition

- Push “IN-START” Key in service remote controller.

(2) Check adjust device

7-3. Download method

EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH]

Vender ID C/S1 C/S2

Vender ID C/S1 C/S2 HDMI2 20 9C 50

RGB [C/S: 1C]

8-6. Manual adj. method

V If internal pattern is not available, use HDMI input. In EZ

- Offset color coordinate : Only THX model

12. Check Wireless function.

9. Checking the EYE-Q Operation.

(Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)

15. Check RF Emitter.

16. Option selection per country

16-4. POWER Supply Unit PCB Ass'y Va/Vs

(1) Model name: 50/60PK750-UA, 50/60PK950-UA

(5) Updating Completed, The TV will restart automatically.

(6) If your TV is turned on, check your updated version and

*.epk File Download)

4. Completed selecting Tool option.

- 14 - LGE Internal Use Only

NAND FLASH MEMORY 8Gbit Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)

OPT OPT 1110: Reserved

- Low : Write Protection

NC_12 NC_19 NAND_CLE: at end of RESETb pulse (O)

BSS83 NAND_DATA[0-7] C116

R101 B2 AF25 FP_IN1 8pF

4.7K HDMI_RX2+ TXA4N

HDMI0_D2P TXOUT0_L4N OPT

AE25 FALE NAND_ALE OPT

AH26 BSS83 FCEB_2

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2011 LG Electronics Inc. All rights reserved.

BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D

NFM18PS105R0J NFM18PS105R0J C249 C253 C256 C258

MODEL_OPT_6 S Tuner Support Not Support IC101 C283

+3.3V_Normal AA6 N23

MODEL_OPT_0 DVR READY Support Not Support

MODEL_OPT_1 MOTION R/C Support Not Support

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2011 LG Electronics Inc. All rights reserved.

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2011 LG Electronics Inc. All rights reserved.

JEDEC Types : DDR_DQ[0:4]