EXPERIMENT NO.

1
Aim: To design NOT, NOR, NAND gates using CADENCE and compute the delay ,Power
dissipation & Noise Margin .

Tools used: Cadence Virtuoso

Theory:
1. Not Gate:
A Not gate is also called as inverter. If input is true output is false similarly if input is false
output is true.

In Out

Fig 1.1: Symbol of inverter

Truth table:

Table 1.1: Truth table of NOT Gate

Input Output

0 1
1 0

Design Equation:
Output= 𝑖𝑛𝑝𝑢𝑡

1
Simulation Setup:
1.NOT GATE:

Fig 1.2:Circuit diagram of NOT Gate using CMOS

Fig 1.3:DC analysis test setup of CMOS invertor

2
 Fig 1.4:Transient analysis test setup of CMOS invertor

Given Specifications:
Table 1.2: Specifications of NOT Gate

Wnmos 2um
Wpmos 4um
Vdd 1.8v
Input 0-1.8v
Timing variables tp =100ns, tr = 1ns,
tf=1ns, tw=49ns
Load Capacitor 1pf

Output Waveform:

Fig 1.5:Transient analysis output waveform

3
 Fig 1.6: Dc analysis output waveform

Output parameters of CMOS invertor:

Table 1.3: Parameters of NOT Gate

Parameter value
Delay 0.96ns
Noise margin(l) 0.6052V
Noise margin(H) 0.7355V
NM(min of NML and 0.6052V
NMH)
Power 58.89* 10−6 watt

2.NOR GATE:
The output is high only when neither A nor B is high. That is, normally high but any kind of non
zero input will make it low.

4
 in1

out

in2

Fig 1.7: Symbol of NOR GATE

Design Equation:
̅̅̅̅̅̅̅̅
Output= 𝐴 +𝐵

Truth table:
Table 1.4: Truth table of NOR Gate

A B Output(Y)
0 0 1
0 1 0
1 0 0
1 1 0

Simulation Setup:

Fig 1.8:Circuit diagram of NOR Gate using CMOS

5
 Fig 1.9:DC analysis test setup of NOR gate

Fig 1.10:Transient analysis test setup of NOR gate

Given Specifications:
Table 1.5: Specifications of NOR Gate

Wpmos1 8um
Wpmos2 8um
Wnmos1 2um
Wnmos2 2um
Vdd 1.8v
Input1 0-1.8v
Timing variables 1 tp =200ns,
tr=1ns,tf=1ns,tw=99ns
Input2 0-1.8v
Timing variables 2 tp =100ns,
tr=1ns,tf=1ns,tw=49ns
Load Capacitor 1pf

6
Output Waveform:

Fig 1.11:Transient analysis output waveform

Fig 1.12: Dc analysis output waveform

7
Output parameters of NOR using cmos:

Table 1.6: Parameters of NOR Gate

Parameter value
Delay1 1.741ns
Delay2 8.25ns
Worst case delay 8.25ns
Noise margin(l) 0.8068 V
Noise margin(H) 0.515 V
Noise Margin(min of 0.515 V
NMl and NMH)
Power 34.05* 10−6 watt
3.NAND Gate:
It is the combination of AND Gate followed by NOT gate i.e. it is the opposite operation of AND
gate where the Logic NAND gate is complementary of AND gate. The logic output of NAND
gate is low only when the inputs are high.

in1

out

in1

Fig 1.13:Symbol of NAND Gate

Design Equation:
̅̅̅̅
Y= 𝐴𝐵
Truth table:

Table 1.7: Truth table of NAND Gate

A B Output(Y)
0 0 1
0 1 1
1 0 1
1 1 0

8
Simulation Setup:

Fig 1.14:Circuit diagram of NAND Gate using CMOS

Fig 1.15:DC analysis test setup of NAND gate

9
 Fig 1.16:Transient analysis test setup of NAND gate

Given Specifications:
Table 1.8: Specifications

Wpmos1 4um
Wpmos2 4um
Wnmos1 4um
Wnmos2 4um
Vdd 1.8V
Input1 0-1.8V
Timing variables 1 tp =200ns,
tr=1ns,tf=1ns,tw=99ns
Input2 0-1.8V
Timing variables 2 tp =100ns,
tr=1ns,tf=1ns,tw=49ns
Load Capacitor 1pf

10
Output Waveform:

Fig 1.17:Transient analysis output waveform

Fig 1.18: Dc analysis output waveform

11
Output parameters of NOR using cmos:

Table 1.9: Parameters of NAND Gate

Parameter value
Delay1 1.282ns
Delay2 1.287ns
Worst case delay 1.287ns
Noise margin(l) 0.4855 V
Noise margin(H) 0.9088 V
Noise Margin(min of 0.4855 V
NML & NMH)
Power 17.41uWatt

Results:
Delay time,average power and noise margin is calculated for NOT, NAND ,NOR Gates and
their output waveform are verified using cadence virtuoso.

12