p1 Thuy Tran TN

Email: ntranthuy@yahoo.com
408 297 3482 (Phone or by appointment)

THUY TRAN TN
Objective
CMOS RFIC/AMS Layout Mask Designer, Sr.

7+ yrs experience CMOS Layout Designer successfully collaborated w/ team

designers taped out the Analog Mixed Signal embedded cores, block chips
layout designs, in the abrupt change of Fabless Semiconductor environment, …

Advance Techniques, Technologies, and Tools/OS/App:

Analog Layout Techniques: Floorplanning chip blocks, hier-designs

(waterfall/Bottom-up methodologies), matching, digitization, Cross Couple,
balancing, and shielding of critical devices … sensitive nets

Edited prop. of P-Cell, RLC; Created Libraries attached to tech- files

Design Technology: TSMCN65; TSMCN45; CMOS&&BiCMOS Processes

Cadence Virtuoso Layout V5.x VLE/VXL&& Cadence DIVA, ASSURA;

Verification EDA: Mentor CALIBRE debugging using RVE …

Unix Solaris /CDE win; SUSE Linux; WS vault; Tag; DesignSynch; reports

Windows(2003/XP), MS-Office (Power Point, Word, Project2003, Excel)

10/2008 – Present CMC DA Engineering San Jose, CA

Experience
Cmos Layout Design Engineer
 Used Cadence VLE/VXL V.5.xx to floorplan and layout the block chips,
completed deliverables; e.g. MEM, DAC, ADC, DDR/SDRAM, OPAMP,
LNA, USB, NET-COMM, …. ;success verified with 100% errors free
 Used Calibre to verify and debug the errors from the RVE; DRC, LVS, SC,
ERC, … xRC as needed
 Created LEF, DEF, GDSII, … files; supported the Design/Tape-out Team
 p2 Thuy Tran TN

02/2007 – 10/2008 Qualcomm San Diego, CA

RF/AMS Layout Mask Designer, Sr.
 Supported Design Engineers of QCT/MCM to tape out the Analog Mixed
Signal embedded core Top Blocks for Wireless SOC; TVDAC, PCDAC,
PLL_NT, TXDAC, DLL_SDRAM, which were achieved used the Cadence
VLS/VXL to floor-plan, layout; used Calibre for Verified DRC, LVS, ERC,
SC, Cellchecker,..., debugging utilized the Calibre RVE; generated LEF, DEF,
CIF, Gatediffareas, and GDSII files…
 Managed the designs used Tags, DesignSynch, Vault;…;library folders of cells;
searched using Tree, …, and performed the ECO as Program Manager/ Design
Engineers requested

10/2001 – 12/2007 CMOS Design Consulting Groups San Jose, CA

IC CMOS Layout Engineer
 Used Cadence OPUS VIRTUOSO Layout Editor to layout the devices:
Wireless ASIC RF AMS, Analog, Digital, BiCMOS, PNP, NPN DIODE,
VCO, Op-Amp, …., SRAM, Decoder, Sense Amp, Pre-charge, buffer,
Adder… I/O Pad/circuitry & ESD, Pre-driver (Tri-state buffer), Driver, ...
 Implemented layout techniques of Matching, Cross Coupling, Common
Centroid, digitization, Shielding, E-migration … Moat, Double Guard-ring,
latch-up prevented, DFM. Isolation layers, different voltages…
 Modified layouts, reused IPs, Verified DRC, LVS Fixed Errors, ...
 Attended detailed schematics, w/ the designers team, for the specified high
performance and constraint area
 Deployed the sharing library of STANDARD cells, Macro/Block Cells ReUse,
Automatic PR, while integrated the full custom layout; generated the Abstract
of Exclusive OR/NOR, D Flip Flop, JK Flip Flop, Tri-state buffer,
Transmission Gate, MUX, Memories s.a HS SRAM, ROM, and DRAM, ….

Education University of California Santa Cruz-ext Santa Cruz, CA

Computer Engineering Award Certificate in VLSI Design Engineering

MOS/SDI Institute San Jose, CA

IC CMOS Layout Design Professional Development

SJSU San Jose, CA

Computational Mathematics

Interests IC Custom AMS layouts: DAC, ADC, LNA/LNF, PLL, AUDIO Osc, MEMs, NET..
 p3 Thuy Tran TN

References Ba’ Ngo CMC, Ngo Xuan Huy LT, Wooping Lai SDI, Đinh Vu, Joesph T Huynh