A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : PAL61
1 1

PCB NO : LA-6561P (DA80000JO10)

DAZ NO : DAZ0FI00100
BOM P/N : 43193131L01,46193131L03.
GPIOMAP:E3MasterGPIOMap10102010.xlsx
E3 MACALLAN 15.6" SG
rPGA Sandy Bridge +
FCBGA PCH Cougar Point-M
2 2

2011-01-12
REV : 1.0(A00)
@ : Nopop Component
CONN@:ConnectorComponent

3 3

MBType BOMP/N

TPMEN/TCMDIS 43193131L01 (R1) 1@ 3@

TPMDIS/TCMEN 43193131L02 (R1) 2@ 4@

TPMDIS/TCMDIS 43193131L03 (R1) 2@ 3@

MB PCB
4 4
Part Number Description

DA80000I700 PCB 0FI LA-6561P REV0 M/B DSC

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 1 of 77
A B C D E
 A B C D E

Block Diagram Compal confidential Model: PAL61 Support Frequence 1066/1333

LVDS SW Memory BUS

LVDS LCD LVDS (DDR3) DDRIII-DIMM X2
page24 PI3LVD400ZFEX BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
LVDS Sandy Bridge page12,13
page23
4MB (Socket G1)
1
GPU rPGA /BGA CPU 1
HDMI HDMIRepeater HDMI
USB 13 TS
CONN page25 PS121 page25 PEG
988 pins page24
USB 11
BT page42
DOCKING DP page6~11
page47~50
DP
PORT FDI DMI
USB 12 Camera
VGA Trough eDP Cable
page39 page24
Lane x 8 Lane x 4
DAI
VGA
CRT CONN Video Switch
USB 8,9 VGA SATA Repeater
page46 MAX14885EETL INTEL USB
SATA 5 page25 SATA 4 MAX4951BECTP E-SATA
IO/B
DOCK LAN page45
COUGAR POINT-M USB 1 USB Port page45

BGA USB 0
USB Port page45
2
1394 2
page36 USB 2
2. IEEE1394+Card reader page14~21 USB Port
OZ600RJ1LN IO/B
USB 1
SDXC page36 USB Port
PCIE 6 Intel Lewisville
PCIE 7 82579LM
page36
HD Audio I/F
PCI Express BUS DOCK LAN
page32
SPI
PCIE 3 PCIE 5 PCIE 2 PCIE 1 Option S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
LAN SWITCH
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TPM1.2 LPC BUS PI3L720
Card Pink Panther WLAN WWAN/UWB SSX35BCB HDA Codec INT.Speaker
W25X64ZE page32
92HD90B2 page30
page38 page37 page37 page37 page36
page36
USB 10 USB 6 USB 4 USB 5 64M 4K sector page30 HeadPhone & Transformer
SATA 0
TDA8034HN USH TPM1.2 MIC Jack
3
Smart Card
page34
page33 3

Stick page34 BCM5882 W25Q32BV page46

HDD MDC
IO/B
page35,36 32M 4K sector
CPU XDP Port RFID page28 page45 RJ45
page34 Fingerprint DAI
page7 FP_USB USB 7 SATA 1
CONN To Docking side page33
page23
PCH XDP Port E-Module
PCIE 4 Dig.
page14 RJ11
SMSC SIO
BC BUS page29
MIC
Thermal ECE5028 Trough Cable
page40 Trough eDP Cable
EMC4022 SMSC KBC
page22
MEC5055
WiFi ON/OFF page41

4 4
IO/B

DELL CONFIDENTIAL/PROPRIETARY
DC/DC Interface TP CONN KB CONN
page43 page42 page42
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Power On/Off TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
SW & LED page31 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 2 of 77
A B C D E
 5 4 3 2 1

POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS USB PORT# DESTINATION
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 JUSB1 (Ext Right Side)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JESA1 (Ext Right Side)
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF OFF D
2 IO Board- JUSB1 (Ext Left Side)
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF OFF
3 IO Board- JUSB2 (Ext Left Side)
S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF PCH
6 JMINI3(Pink Panther)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO
PM TABLE 8 DOCKING
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA DESTINATION 9 DOCKING
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
C
+3.3V_ALW_PCH +1.8V_RUN (M-OFF) SATA 0 HDD C
power
plane +3.3V_RTC_LDO +1.5V_RUN 10 Express card
+0.75V_DDR_VTT
SATA 1 ODD/ E3 Module Bay 11 Bluetooth
+VCC_CORE
+1.05V_RUN_VTT
SATA 2 NA
+1.05V_RUN 12 Camera
State
SATA 3 NA
13 LCD Touch
S0 ON ON ON ON ON SATA 4 ESATA
SATA 5 Dock 0 BIO
S3 ON ON OFF ON OFF
USH
1 NA
S5 S4/AC ON OFF OFF ON OFF

S5 S4/AC don't exist OFF OFF OFF OFF OFF

B
PCI EXPRESS DESTINATION B

Lane 1 MINI CARD-1 WWAN

Lane 2 MINI CARD-2 WLAN

DSC DP/HDMI Port Connetion Lane 3 Express card

Port C Dock DP port 2 Lane 4 E3 Module Bay (USB3)

Port D Dock DP port 1 Lane 5 MINI CARD-3 (Pink Panther)

Port E MB HDMI Conn Lane 6 MMI

Lane 7 10/100/1G LOM

A
Lane 8 None A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 3 of 77
5 4 3 2 1
 5 4 3 2 1

MODC_EN
HDDC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21

ADAPTER
D
PGPU_PWR_EN ISL95870A SI3456BDV SI3456BDV D
+GPU_CORE
(PU15) (Q27) (Q30)

+PWR_SRC 1.05V_VTTPWRGD
BATTERY ISL95870AH +5V_HDD +5V_MOD
+0.8V_VCC_SA
(PU13)

ALWON

+15V_ALW
ISL6236IRZA
CHARGER +5V_ALW RUN_ON
(PU2)

C C

SI4164DY
+3.3V_ALW (Q50)

AUX_EN_WOWL

PCH_ALW_ON
+5V_RUN

AUX_ON
SUS_ON

RUN_ON

M_ON
SN1003055 SN1003055
MAX17411 RT8209BGQW RT9026GFP TPS51311
(PU9) (PU3) (PU5) (PU4) (PU7) (PU6) SI3456BDV SI3456BDV S13456 SI3456 NTMS4107 SI3456
(Q38) (Q49) (Q54) (Q34) (Q55) (Q58)
CPU_VTT_ON
0.75V_VR_EN

M_ON
DDR_ON

RUN_ON

B B
1.05V_0.8V_PWROK

+3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M

+VCC_GFXCORE +VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M

Pop option
RUN_ON

CPU1.5V_S3_GATE RUN_ON
Pop option

+1.0V_LAN +3.3V_M

AO4728 SI3456 SI4164

(QC3) (Q59) (Q63)
+0.8V_VCCSA
A A

+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

+1.5V_CPU_VDDQ +1.5V_RUN
Compal Electronics, Inc.

www.vinafix.vn
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 4 of 77
5 4 3 2 1
 5 4 3 2 1

2.2K
SMBUS Address [0x9a]

2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002 SMBUS Address [A0h]
C9 MEM_SMBDATA 200 DIMMA A0h --> 1010 0000
2N7002
2.2K
202
PCH SMBUS Address [A4h]
D +3.3V_LAN 200 DIMMB A4h --> 1010 0100 D
2.2K
C6 LAN_SMBCLK 28
LAN_SMBDATA 31 LOM SMBUS Address [C8]
G8
M16 E14 53
51 XDP1 SMBUS Address [TBD]
2.2K
SML1_SMBDATA

SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]

3A 3A
2.2K +3.3V_ALW SMBUS Address
APR_EC: 0x48
B4 DOCK_SMB_CLK 127 2.2K
1A SPR_EC: 0x70
129 DOCKING MSLICE_EC: 0x72
1A A3 DOCK_SMB_DAT
USB: 0x59 2.2K
+3.3V_RUN
AUDIO: 0x34
2.2K SLICE_BATTERY: 0x17 14
SLICE_CHARGER: 0x13 G Sensor
+3.3V_ALW 13 SMBUS Address [TBD]
C C
2.2K

B5 LCD_SMBCLK
1B 30
1B A4 LCD_SMDATA
32 WWAN
SMBUS Address [TBD]
2.2K

KBC 2.2K
+3.3V_ALW
SMBUS Address
100 ohm 7
1C A56 PBAT_SMBCLK SMB_ADM1032: 0x98
6 BATTERY SMBUS Address [0x16] SMB_DIAG_DUMP: 0x04
1C B59 PBAT_SMBDAT 100 ohm
CONN SMB_DIAG_DUMP2: 0x05
2.2K SMB_BLACKTOP: 0x60

+3.3V_ALW
2.2K
A50 USH_SMBCLK M9
1E
B53 USH_SMBDAT L9 USH SMBUS Address [0xa4]
1E
B B
2.2K

+3.3V_ALW
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT

2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 10
1G
A47 CHARGER_SMBDAT 9 Charger
1G SMBUS Address [0x12]

2.2K
+3.3V_RUN
2.2K
B7 BAY_SMBDAT 31
2D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
A7 BAY_SMBCLK 32 E3 Module Bay TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
A
SMBUS Address [TBD] BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, A
2D
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2.2K
+3.3V_RUN
2.2K
B49 GPU_SMBCLK
2A 8 Compal Electronics, Inc.
B48 GPU_SMBDAT 9
A/D,D/A SMBUS Address [0x30] Title
2A
converter SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 5 of 77
5 4 3 2 1
 5 4 3 2 1

JCPU1I

JCPU1A T35 F22

PEG_COMP VSS161 VSS234
PEG_ICOMPI J22 T34 VSS162 VSS235 F19
PEG_ICOMPO J21 T33 VSS163 VSS236 E30
DMI_CRX_PTX_N0 B27 H22 T32 E27
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO VSS164 VSS237
DMI_CRX_PTX_N1 B25 T31 E24
<16> DMI_CRX_PTX_N1 DMI_RX#[1] VSS165 VSS238
DMI_CRX_PTX_N2 A25 T30 E21
D <16> DMI_CRX_PTX_N2 DMI_RX#[2] PEG_CRX_GTX_N[0..15] <47> VSS166 VSS239 D
DMI_CRX_PTX_N3 B24 K33 PEG_CRX_GTX_N15 T29 E18
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] VSS167 VSS240
M35 PEG_CRX_GTX_N14 T28 E15
DMI_CRX_PTX_P0 PEG_RX#[1] PEG_CRX_GTX_N13 VSS168 VSS241
<16> DMI_CRX_PTX_P0 B28 DMI_RX[0] PEG_RX#[2] L34 T27 VSS169 VSS242 E13
DMI_CRX_PTX_P1 B26 J35 PEG_CRX_GTX_N12 T26 E10
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3] VSS170 VSS243

DMI
DMI_CRX_PTX_P2 A24 J32 PEG_CRX_GTX_N11 P9 E9
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] VSS171 VSS244
DMI_CRX_PTX_P3 B23 H34 PEG_CRX_GTX_N10 P8 E8
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] VSS172 VSS245
H31 PEG_CRX_GTX_N9 P6 E7
DMI_CTX_PRX_N0 PEG_RX#[6] PEG_CRX_GTX_N8 VSS173 VSS246
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 P5 VSS174 VSS247 E6
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 E22 G30 PEG_CRX_GTX_N7 P3 E5
DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_CRX_GTX_N6 VSS175 VSS248
<16> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35 P2 VSS176 VSS249 E4
<16> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 D21 E34 PEG_CRX_GTX_N5 N35 E3
DMI_TX#[3] PEG_RX#[10] PEG_CRX_GTX_N4 VSS177 VSS250
PEG_RX#[11] E32 N34 VSS178 VSS251 E2
<16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 G22 D33 PEG_CRX_GTX_N3 N33 E1
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_CRX_GTX_N2 VSS179 VSS252
<16> DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31 N32 VSS180 VSS253 D35

PCI EXPRESS* - GRAPHICS

<16> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 F20 B33 PEG_CRX_GTX_N1 N31 D32
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_CRX_GTX_N0 VSS181 VSS254
<16> DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32 PEG_CRX_GTX_P[0..15] <47> N30 VSS182 VSS255 D29
PEG_CTX_GRX_P[0..15] N29 D26
PEG_CRX_GTX_P15 PEG_CTX_GRX_P[0..15] <47> VSS183 VSS256
PEG_RX[0] J33 N28 VSS184 VSS257 D20
L35 PEG_CRX_GTX_P14 PEG_CTX_GRX_N[0..15] N27 D17
PEG_RX[1] PEG_CRX_GTX_P13 PEG_CTX_GRX_N[0..15] <47> VSS185 VSS258
PEG_RX[2] K34 N26 VSS186 VSS259 C34
<16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 A21 H35 PEG_CRX_GTX_P12 M34 C31
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PEG_CRX_GTX_P11 VSS187 VSS260
<16> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32 L33 VSS188 VSS261 C28
<16> FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 E19 G34 PEG_CRX_GTX_P10 L30 C27
FDI_CTX_PRX_N3 FDI0_TX#[2] Intel(R) FDI PEG_RX[5] PEG_CRX_GTX_P9 VSS189 VSS262
<16> FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31 L27 VSS190 VSS263 C25
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 B21 F33 PEG_CRX_GTX_P8 L9 C23
FDI_CTX_PRX_N5 FDI1_TX#[0] PEG_RX[7] PEG_CRX_GTX_P7 VSS191 VSS264
<16> FDI_CTX_PRX_N5 C20 FDI1_TX#[1] PEG_RX[8] F30 L8 VSS192 VSS265 C10
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 D18 E35 PEG_CRX_GTX_P6 L6 C1
FDI_CTX_PRX_N7 FDI1_TX#[2] PEG_RX[9] PEG_CRX_GTX_P5 VSS193 VSS266
<16> FDI_CTX_PRX_N7 E17 FDI1_TX#[3] PEG_RX[10] E33 L5 VSS194 VSS267 B22
F32 PEG_CRX_GTX_P4 L4 B19

<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 FDI0_TX[0]

PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
D34
E31
PEG_CRX_GTX_P3
PEG_CRX_GTX_P2 CheckifsupportPCIEGEN2
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 PEG_CRX_GTX_P1 L1 B13
C FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PEG_CRX_GTX_P0 VSS198 VSS271 C
<16> FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32 K35 VSS199 VSS272 B11
<16> FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 G18 K32 B9
FDI_CTX_PRX_P4 FDI0_TX[3] PEG_CTX_GRX_C_N15 VSS200 VSS273
<16> FDI_CTX_PRX_P4 B20 FDI1_TX[0] PEG_TX#[0] M29 K29 VSS201 VSS274 B8
<16> FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 C19 M32 PEG_CTX_GRX_C_N14 K26 B7
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P0 CC49 2 VSS202 VSS275
<16> FDI_CTX_PRX_P6 D19 FDI1_TX[2] PEG_TX#[2] M31 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P0 J34 VSS203 VSS276 B5
<16> FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 F17 L32 PEG_CTX_GRX_C_N12 PEG_CTX_GRX_C_N0 CC33 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N0 J31 B3
FDI1_TX[3] PEG_TX#[3] PEG_CTX_GRX_C_N11 VSS204 VSS277
PEG_TX#[4] L29 H33 VSS205 VSS278 B2
FDI_FSYNC0 J18 K31 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P1 CC50 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P1 H30 A35
<16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] VSS206 VSS279
FDI_FSYNC1 J17 K28 PEG_CTX_GRX_C_N9 PEG_CTX_GRX_C_N1 CC34 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N1 H27 A32
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] VSS207 VSS280
J30 PEG_CTX_GRX_C_N8 H24 A29
FDI_INT PEG_TX#[7] PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P2 CC51 2 PEG_CTX_GRX_P2 VSS208 VSS281
<16> FDI_INT H20 FDI_INT PEG_TX#[8] J28 1 0.22U_0402_16V7K~D H21 VSS209 VSS282 A26
H29 PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N2 CC35 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N2 H18 A23
FDI_LSYNC0 PEG_TX#[9] PEG_CTX_GRX_C_N5 VSS210 VSS283
<16> FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 H15 VSS211 VSS284 A20
FDI_LSYNC1 H17 E29 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P3 CC52 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P3 H13 A3
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] VSS212 VSS285
F27 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N3 CC36 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N3 H10
PEG_TX#[12] PEG_CTX_GRX_C_N2 VSS213
PEG_TX#[13] D28 H9 VSS214
F26 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P4 CC53 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P4 H8
PEG_TX#[14] PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N4 CC37 2 VSS215
PEG_TX#[15] E25 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N4 H7 VSS216
EDP_COMP A18 H6
eDP_COMPIO PEG_CTX_GRX_C_P15 PEG_CTX_GRX_C_P5 CC54 2 VSS217
A17 eDP_ICOMPO PEG_TX[0] M28 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P5 H5 VSS218
B16 M33 PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_N5 CC38 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N5 H4
eDP_HPD PEG_TX[1] PEG_CTX_GRX_C_P13 VSS219
(1)EDP_COMPIOuse4miltracetoRC1 PEG_TX[2] M30
PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_P6 CC55 2
H3 VSS220
PEG_TX[3] L31 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P6 H2 VSS221
(2)EDP_ICOMPOuse12miltoRC1 C15 eDP_AUX PEG_TX[4] L28 PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_N6 CC39 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N6 H1 VSS222
D15 K30 PEG_CTX_GRX_C_P10 G35
eDP_AUX# PEG_TX[5] VSS223
eDP

K27 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P7 CC56 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P7 G32

PEG_TX[6] PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N7 CC40 2 VSS224
PEG_TX[7] J29 1 0.22U_0402_16V7K~D PEG_CTX_GRX_N7 G29 VSS225
C17 J27 PEG_CTX_GRX_C_P7 G26
eDP_TX[0] PEG_TX[8] PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P8 CC57 1 PEG_CTX_GRX_P8 VSS226
F16 eDP_TX[1] PEG_TX[9] H28 2 0.22U_0402_16V7K~D G23 VSS227
C16 G28 PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N8 CC41 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N8 G20
eDP_TX[2] PEG_TX[10] PEG_CTX_GRX_C_P4 VSS228
G15 eDP_TX[3] PEG_TX[11] E28 G17 VSS229
F28 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P9 CC58 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P9 G11
B PEG_TX[12] PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N9 CC42 1 VSS230 B
C18 eDP_TX#[0] PEG_TX[13] D27 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N9 F34 VSS231
E16 E26 PEG_CTX_GRX_C_P1 F31
eDP_TX#[1] PEG_TX[14] PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P10 CC59 1 VSS232
D16 eDP_TX#[2] PEG_TX[15] D25 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P10 F29 VSS233
F15 PEG_CTX_GRX_C_N10 CC43 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N10
eDP_TX#[3]
PEG_CTX_GRX_C_P11 CC60 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P11
Sandy Bridge_rPGA_Rev1p0 PEG_CTX_GRX_C_N11 CC44 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N11

CONN@ PEG_CTX_GRX_C_P12 CC61 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P12

PEG_CTX_GRX_C_N12 CC45 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N12
PEG reverse check CFG2 routing
PEG_CTX_GRX_C_P13 CC62 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P13
DP Compensation PEG_CTX_GRX_C_N13 CC46 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N13 Sandy Bridge_rPGA_Rev1p0

PEG Compensation PEG_CTX_GRX_C_P14 CC63 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P14 CONN@

PEG_CTX_GRX_C_N14 CC47 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N14
+1.05V_RUN_VTT +1.05V_RUN_VTT PEG_CTX_GRX_C_P15 CC64 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P15
PEG_CTX_GRX_C_N15 CC48 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N15
1

RC1 RC2
24.9_0402_1%~D 24.9_0402_1%~D
2

EDP_COMP PEG_COMP

eDP_COMPIO and ICOMPO signals should be shorted near

balls and routed with typical impedance <25 mohms PEG_ICOMPI and RCOMPO signals should be shorted and routed
A A
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATICS,MB A6561
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 6 of 77
5 4 3 2 1
 5 4 3 2 1

+1.05V_RUN_VTT
Follow DG Rev0.71 SM_DRAMPWROK topology +1.5V_CPU_VDDQ +3.3V_ALW_PCH

+1.05V_RUN_VTT +1.05V_RUN_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
+3.3V_ALW_PCH

1
0.1U_0402_16V4Z~D 1 1

1
CC1561 2

CC65

CC66
RC12 @RC124
@ RC124 JXDP1

5
UC2 200_0402_5%~D 1K_0402_5%~D 1 2
2 2 XDP_PREQ# GND0 GND1 CFG16
1 B 3 4 CFG16 <9>

P
<40,41> RUNPWROK

2
RUNPWROK_AND OBSFN_A0 OBSFN_C0
4 1 2 PM_DRAM_PWRGD_CPU XDP_PRDY# 5 6 CFG17 CFG17 <9>

2
O RC28 130_0402_5%~D OBSFN_A1 OBSFN_C1
+3.3V_ALW_PCH 1 2 2 A 7 GND2 GND3 8

2
RC18 200_0402_5%~D SYS_PWROK_XDP XDP_OBS0 9 10 CFG0 CFG0 <9>
74AHC1G09GW_TSSOP5~D RC64 XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
<16> PM_DRAM_PWRGD Place near JXDP1 11 12 CFG1 <9>

3
39_0402_5%~D OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
D XDP_OBS2 CFG2 D
15 OBSDATA_A2 OBSDATA_C2 16 CFG2 <9>
XDP_OBS3 17 18 CFG3 CFG3 <9>

1 1
OBSDATA_A3 OBSDATA_C3
D 19 GND6 GND7 20
<9> CFG10 CFG10 21 22 CFG8 CFG8 <9>
QC1 CFG11 OBSFN_B0 OBSFN_D0 CFG9
<11,43> RUN_ON_CPU1.5VS3# 2 <9> CFG11 23 OBSFN_B1 OBSFN_D1 24 CFG9 <9>
G SSM3K7002FU_SC70-3~D 25 26
XDP_OBS4 GND8 GND9 CFG4
S 27 28 CFG4 <9>

3
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 OBSDATA_B1 OBSDATA_D1 30 CFG5 <9>
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33 OBSDATA_B2 OBSDATA_D2 34 CFG6 <9>
XDP_OBS7 35 36 CFG7 CFG7 <9>
OBSDATA_B3 OBSDATA_D3
37 GND12 GND13 38
H_CPUPWRGD 1 2 H_CPUPWRGD_XDP 39 40 CLK_XDP
RC51 PWRGOOD/HOOK0 ITPCLK/HOOK4
<14,16> SIO_PWRBTN#_R 2 1K_0402_5%~D CFD_PWRBTN#_XDP 41 HOOK1 ITPCLK#/HOOK5 42 CLK_XDP#
@ RC6 0_0402_5%~D 43 44
CFG0 XDP_HOOK2 VCC_OBS_AB VCC_OBS_CD XDP_RST#_R
1 2 45 HOOK2 RESET#/HOOK6 46
+1.05V_RUN_VTT RC71 2 1K_0402_5%~D SYS_PWROK_XDP 47 48 XDP_DBRESET#
<16,40> SYS_PWROK HOOK3 DBR#/HOOK7
@ RC9 0_0402_5%~D 49 50
DDR_XDP_WAN_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,28,37> DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# RC1251 20_0402_5%~D DDR_XDP_WAN_SMBCLK_R1 53 54 XDP_TRST#
<12,13,14,15,28,37> DDR_XDP_WAN_SMBCLK SCL TRST#
@RC126
@ RC126 56_0402_5%~D RC127 0_0402_5%~D 55 56 XDP_TDI
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 TCK0 TMS 58
@RC128
@ RC128 49.9_0402_1%~D 59 60
H_PROCHOT# GND16 GND17
1 2
RC44 62_0402_5%~D JCPU1B CONN@ SAMTE_BSH-030-01-L-D-A
CONN@

A28 CPU_DMI 1 2 CLK_CPU_DMI <15>

MISC

CLOCKS
BCLK CPU_DMI# @ RC13 1
C26 PROC_SELECT# BCLK# A27 2 0_0402_5%~D CLK_CPU_DMI# <15>
@ RC15 0_0402_5%~D XDP_RST#_R 2 1 PLTRST_XDP# <17>
RC8 1K_0402_5%~D
C C
<40> CPU_DETECT# AN34 SKTOCC#
A16 CPU_DPLL 1 2
DPLL_REF_CLK CLK_CPU_DPLL <15>
A15 CPU_DPLL# @ RC1001 2 0_0402_5%~D
DPLL_REF_CLK# CLK_CPU_DPLL# <15>
@ RC101 0_0402_5%~D
1 2 CLK_XDP 1 2 CLK_CPU_ITP <15>
H_CATERR# AL33 @ RC48 0_0402_5%~D @RH107 0_0402_5%~D
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# <15>
@ RH106 0_0402_5%~D
THERMAL

D
AN33 R8 DDR3_DRAMRST#_CPU 3 1
<41> PECI_EC PECI SM_DRAMRST# DDR3_DRAMRST# <12>
DDR3
MISC
QC2
Max 500mils BSS138W-7-F_SOT323-3~D

G
<9> CLK_XDP_ITP 1 2

2
1
<41,59> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @RH109
@ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
SM_RCOMP[1] A5 <9> CLK_XDP_ITP# 1 2
A4 SM_RCOMP2 4.99K_0402_1%~D DDR_HVREF_RST @RH108
@ RH108 0_0402_5%~D
SM_RCOMP[2]
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 1

2
@RC129
@RC129 THERMTRIP#
0_0402_5%~D
CC177
0.047U_0402_16V4Z~D
place RC129 near CPU 2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# AP27

AR26 XDP_TCLK 1 2
TCK <15> DDR_HVREF_RST_PCH
PWR MANAGEMENT

XDP_TMS @RC46
JTAG & BPM

AR27 0_0402_5%~D
H_PM_SYNC TMS XDP_TRST#
<16> H_PM_SYNC AM34 PM_SYNC TRST# AP30 <41> DDR_HVREF_RST_GATE 1 2 PU/PD for JTAG signals
@ RC47 0_0402_5%~D
AR28 XDP_TDI_R +3.3V_RUN
TDI XDP_TDO_R
TDO AP26
<18> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R AP33 UNCOREPWRGOOD
B @ RC25 0_0402_5%~D XDP_DBRESET# B
2 1
RC19 1K_0402_5%~D
AL35 XDP_DBRESET#_R 2 1 XDP_DBRESET# XDP_DBRESET# <14,16>
PM_DRAM_PWRGD_CPU DBR# @ RC26 +1.05V_RUN_VTT
V8 0_0402_5%~D
SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0 XDP_TMS RC27 2 1 51_0402_1%~D
BPM#[0] XDP_OBS1_R @ RC30 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
BPM#[1] AR29 1 2 1 2
AR30 XDP_OBS2_R @ RC31 1 2 0_0402_5%~D XDP_OBS2 @RC23
@ RC23 0_0402_5%~D XDP_TDI_R RC29 2 1 51_0402_1%~D
PCH_PLTRST#_R BPM#[2] XDP_OBS3_R @ RC33 0_0402_5%~D XDP_OBS3
AR33 RESET# BPM#[3] AT30 1 2
AP32 XDP_OBS4_R @ RC34 1 2 0_0402_5%~D XDP_OBS4 XDP_PREQ# @
@RC32
RC32 2 1 51_0402_1%~D
BPM#[4] XDP_OBS5_R @ RC36 0_0402_5%~D XDP_OBS5 XDP_TDO_R XDP_TDO
BPM#[5] AR31 1 2 1 2
AT31 XDP_OBS6_R @ RC37 1 2 0_0402_5%~D XDP_OBS6 @ RC24 0_0402_5%~D XDP_TDO RC35 2 1 51_0402_1%~D
BPM#[6] XDP_OBS7_R @ RC38 0_0402_5%~D XDP_OBS7
BPM#[7] AR32 1 2
@ RC39 0_0402_5%~D
For ESD concern, please put near CPU XDP_TCLK RC40 2 1
51_0402_1%~D
Sandy Bridge_rPGA_Rev1p0 XDP_TRST# RC41 2 1
51_0402_1%~D

Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R

+1.05V_RUN_VTT SM_RCOMP2
SM_RCOMP1
1
0.1U_0402_16V4Z~D

SM_RCOMP0
1 RC130
1
75_0402_1%~D

RC4

140_0402_1%~D

200_0402_1%~D
25.5_0402_1%~D
10K_0402_5%~D

1
CC140

RC42

RC43

RC45
2

2
UC1
2

1 5

A NC VCC
<14,17> PCH_PLTRST# 2 A
3 4
GND Y
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
5 4
2
A
PCH_PLTRST#_BUF 1 2 PCH_PLTRST#_R
RC10 43_0402_5%~D Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATICS,MB A6561
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 7 of 77
3 2 1
 5 4 3 2 1

JCPU1D
JCPU1C

AE2 M_CLK_DDR2
D <13> DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR2 <13> D
AB6 M_CLK_DDR0 AD2 M_CLK_DDR#2
<12> DDR_A_D[0..63] SA_CLK[0] M_CLK_DDR0 <12> SB_CLK#[0] M_CLK_DDR#2 <13>
AA6 M_CLK_DDR#0 DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
SA_CLK#[0] M_CLK_DDR#0 <12> SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D0 C5 V9 DDR_CKE0_DIMMA DDR_B_D1 A7
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> SB_DQ[1]
DDR_A_D1 D5 DDR_B_D2 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 SA_DQ[2] C8 SB_DQ[3]
DDR_A_D3 D2 DDR_B_D4 A9 AE1 M_CLK_DDR3
SA_DQ[3] SB_DQ[4] SB_CLK[1] M_CLK_DDR3 <13>
DDR_A_D4 D6 AA5 M_CLK_DDR1 DDR_B_D5 A8 AD1 M_CLK_DDR#3
SA_DQ[4] SA_CLK[1] M_CLK_DDR1 <12> SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 <13>
DDR_A_D5 C6 AB5 M_CLK_DDR#1 DDR_B_D6 D9 R10 DDR_CKE3_DIMMB
SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 <12> SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D6 C2 V10 DDR_CKE1_DIMMA DDR_B_D7 D8
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> SB_DQ[7]
DDR_A_D7 C3 DDR_B_D8 G4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8]
F10 SA_DQ[8] F4 SB_DQ[9]
DDR_A_D9 F8 DDR_B_D10 F1 AB2
DDR_A_D10 SA_DQ[9] DDR_B_D11 SB_DQ[10] RSVD_TP[11]
G10 SA_DQ[10] RSVD_TP[1] AB4 G1 SB_DQ[11] RSVD_TP[12] AA2
DDR_A_D11 G9 AA4 DDR_B_D12 G5 T9
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D13 SB_DQ[12] RSVD_TP[13]
F9 SA_DQ[12] RSVD_TP[3] W9 F5 SB_DQ[13]
DDR_A_D13 F7 DDR_B_D14 F2
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
G8 SA_DQ[14] G2 SB_DQ[15]
DDR_A_D15 G7 DDR_B_D16 J7 AA1
DDR_A_D16 SA_DQ[15] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
K4 SA_DQ[16] RSVD_TP[4] AB3 J8 SB_DQ[17] RSVD_TP[15] AB1
DDR_A_D17 K5 AA3 DDR_B_D18 K10 T10
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D19 SB_DQ[18] RSVD_TP[16]
K1 SA_DQ[18] RSVD_TP[6] W10 K9 SB_DQ[19]
DDR_A_D19 J1 DDR_B_D20 J9
DDR_A_D20 SA_DQ[19] DDR_B_D21 SB_DQ[20]
J5 SA_DQ[20] J10 SB_DQ[21]
DDR_A_D21 J4 DDR_B_D22 K8 AD3 DDR_CS2_DIMMB#
SA_DQ[21] SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# <13>
DDR_A_D22 J2 AK3 DDR_CS0_DIMMA# DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# <12> SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D24 M5 AD6
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> SB_DQ[24] RSVD_TP[17]
DDR_A_D24 M8 AG1 DDR_B_D25 N4 AE6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
N10 SA_DQ[25] RSVD_TP[8] AH1 N2 SB_DQ[26]
DDR_A_D26 N8 DDR_B_D27 N1
DDR_A_D27 SA_DQ[26] DDR_B_D28 SB_DQ[27]
N7 SA_DQ[27] M4 SB_DQ[28]
DDR_A_D28 M10 DDR_B_D29 N5 AE4 M_ODT2
SA_DQ[28] SB_DQ[29] SB_ODT[0] M_ODT2 <13>

DDR SYSTEM MEMORY B

DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
C SA_DQ[29] SA_ODT[0] M_ODT0 <12> SB_DQ[30] SB_ODT[1] M_ODT3 <13> C
DDR_A_D30 M_ODT1 DDR_B_D31
DDR SYSTEM MEMORY A
N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 <12> M1 SB_DQ[31] RSVD_TP[19] AD5
DDR_A_D31 M7 AG2 DDR_B_D32 AM5 AE5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D33 SB_DQ[32] RSVD_TP[20]
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM6 SB_DQ[33]
DDR_A_D33 AG5 DDR_B_D34 AR3
DDR_A_D34 SA_DQ[33] DDR_B_D35 SB_DQ[34]
AK6 SA_DQ[34] AP3 SB_DQ[35]
DDR_A_D35 AK5 DDR_B_D36 AN3
SA_DQ[35] SB_DQ[36] DDR_B_DQS#[0..7] <13>
DDR_A_D36 AH5 DDR_B_D37 AN2 D7 DDR_B_DQS#0
SA_DQ[36] DDR_A_DQS#[0..7] <12> SB_DQ[37] SB_DQS#[0]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 SA_DQ[38] SA_DQS#[1] G6 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 SA_DQ[44] SA_DQS#[7] AM15 AN8 SB_DQ[45]
DDR_A_D45 AH9 DDR_B_D46 AR6
DDR_A_D46 SA_DQ[45] DDR_B_D47 SB_DQ[46]
AL9 SA_DQ[46] AR5 SB_DQ[47]
DDR_A_D47 AL8 DDR_B_D48 AR9
SA_DQ[47] SB_DQ[48] DDR_B_DQS[0..7] <13>
DDR_A_D48 AP11 DDR_B_D49 AJ11 C7 DDR_B_DQS0
SA_DQ[48] DDR_A_DQS[0..7] <12> SB_DQ[49] SB_DQS[0]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D50 AT8 G3 DDR_B_DQS1
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL12 SA_DQ[50] SA_DQS[1] F6 AT9 SB_DQ[51] SB_DQS[2] J6
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D52 AH11 M3 DDR_B_DQS3
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AM11 SA_DQ[52] SA_DQS[3] N6 AR8 SB_DQ[53] SB_DQS[4] AN6
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D54 AJ12 AP8 DDR_B_DQS5
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AP12 SA_DQ[54] SA_DQS[5] AM9 AH12 SB_DQ[55] SB_DQS[6] AK11
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D56 AT11 AP14 DDR_B_DQS7
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 SA_DQ[56] SA_DQS[7] AM14 AN14 SB_DQ[57]
DDR_A_D57 AH14 DDR_B_D58 AR14
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AL15 SA_DQ[58] AT14 SB_DQ[59] DDR_B_MA[0..15] <13>
DDR_A_D59 AK15 DDR_B_D60 AT12
SA_DQ[59] DDR_A_MA[0..15] <12> SB_DQ[60]
DDR_A_D60 AL14 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 SA_DQ[61] SA_MA[0] AD10 AR15 SB_DQ[62] SB_MA[1] T7
B DDR_A_D62 DDR_A_MA1 DDR_B_D63 DDR_B_MA2 B
AJ15 SA_DQ[62] SA_MA[1] W1 AT15 SB_DQ[63] SB_MA[2] R7
DDR_A_D63 AH15 W2 DDR_A_MA2 T6 DDR_B_MA3
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
SA_MA[3] W7 SB_MA[4] T2
V3 DDR_A_MA4 T4 DDR_B_MA5
SA_MA[4] DDR_A_MA5 SB_MA[5] DDR_B_MA6
SA_MA[5] V2 SB_MA[6] T3
W3 DDR_A_MA6 DDR_B_BS0 AA9 R2 DDR_B_MA7
SA_MA[6] <13> DDR_B_BS0 SB_BS[0] SB_MA[7]
DDR_A_BS0 AE10 W6 DDR_A_MA7 DDR_B_BS1 AA7 T5 DDR_B_MA8
<12> DDR_A_BS0 SA_BS[0] SA_MA[7] <13> DDR_B_BS1 SB_BS[1] SB_MA[8]
DDR_A_BS1 AF10 V1 DDR_A_MA8 DDR_B_BS2 R6 R3 DDR_B_MA9
<12> DDR_A_BS1 SA_BS[1] SA_MA[8] <13> DDR_B_BS2 SB_BS[2] SB_MA[9]
DDR_A_BS2 V6 W5 DDR_A_MA9 AB7 DDR_B_MA10
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] SB_MA[10]
AD8 DDR_A_MA10 R1 DDR_B_MA11
SA_MA[10] DDR_A_MA11 SB_MA[11] DDR_B_MA12
SA_MA[11] V4 SB_MA[12] T1
W4 DDR_A_MA12 DDR_B_CAS# AA10 AB10 DDR_B_MA13
SA_MA[12] <13> DDR_B_CAS# SB_CAS# SB_MA[13]
DDR_A_CAS# AE8 AF8 DDR_A_MA13 DDR_B_RAS# AB8 R5 DDR_B_MA14
<12> DDR_A_CAS# SA_CAS# SA_MA[13] <13> DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_WE# AB9 R4 DDR_B_MA15
<12> DDR_A_RAS# SA_RAS# SA_MA[14] <13> DDR_B_WE# SB_WE# SB_MA[15]
DDR_A_WE# AF9 V7 DDR_A_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15]

Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATICS,MB A6561
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 8 of 77
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
RC51
1K_0402_5%~D

2
D JCPU1E D

L7 @ T1 PAD~D
RSVD28 @ T2 PAD~D
RSVD29 AG7
CFG0 AK28 AE7 @ T3 PAD~D
<7> CFG0 CFG[0] RSVD30
CFG1 AK29 AK2 @ T4 PAD~D PEG Static Lane Reversal - CFG2 is for the 16x
<7> CFG1 CFG[1] RSVD31
CFG2 AL26 W8 @ T5 PAD~D
<7> CFG2 CFG[2] RSVD32
CFG3 AL27
<7> CFG3 CFG[3]
CFG4 AK26 1:(Default) Normal Operation; Lane #
<7> CFG4 CFG[4]
CFG5 AL29 AT26 @ T6 PAD~D CFG2
<7> CFG5
CFG6 AL30
CFG[5] RSVD33
AM33 @ T7 PAD~D definition matches socket pin map definition
<7> CFG6 CFG[6] RSVD34
CFG7 AM31 AJ27 @ T8 PAD~D 0:Lane Reversed
<7> CFG7 CFG[7] RSVD35
CFG8 AM32
<7> CFG8 CFG[8]
CFG9 AM30
<7> CFG9 CFG[9]
CFG10 AM28
<7> CFG10 CFG[10]
CFG11 AM26 CFG4
+VCC_GFXCORE <7> CFG11 CFG[11]
@ T9 PAD~D CFG12 AN28 CFG[12]

1
@ T10 PAD~D CFG13 AN31 T8 @ T11 PAD~D
@ T12 PAD~D CFG14 CFG[13] RSVD37 @ T13 PAD~D RC52 @
AN26 CFG[14] RSVD38 J16
@ T14 PAD~D CFG15 AM27 H16 @ T15 PAD~D 1K_0402_5%~D
RSVD1 CFG16 CFG[15] RSVD39 @ T16 PAD~D
1 2 <7> CFG16 AK31 CFG[16] RSVD40 G16
@ RC122 49.9_0402_1%~D CFG17 AN29
<7> CFG17

2
CFG[17]

AR35 @ T17 PAD~D

+VCC_CORE RSVD1 RSVD41 @ T18 PAD~D
AJ31 VAXG_VAL_SENSE RSVD42 AT34
RSVD2 AH31 AT33 @ T19 PAD~D
RSVD3 RSVD3 VSSAXG_VAL_SENSE RSVD43 @ T20 PAD~D
1 2 AJ33 VCC_VAL_SENSE RSVD44 AP35 Display Port Presence Strap
@ RC120 49.9_0402_1%~D RSVD4 AH33 AR34 @ T21 PAD~D
VSS_VAL_SENSE RSVD45
C C
1 : Disabled; No Physical Display Port
1 2 RSVD2 PAD~D T22 @ AJ26 CFG4
RSVD5 attached to Embedded Display Port

RESERVED
@ RC123 49.9_0402_1%~D
1 2 RSVD4
@ RC121 49.9_0402_1%~D B34 @ T23 PAD~D 0 : Enabled; An external Display Port device is
+DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU B4 RSVD46 @ T24 PAD~D
1 2 +DIMM0_1_VREF_CPU A33
@ RC96 1K_0402_5%~D +DIMM0_1_CA_CPU D1
RSVD6 RSVD47
A34 @ T25 PAD~D connected to the Embedded Display Port
+DIMM0_1_CA_CPU RSVD7 RSVD48
1 2 +DIMM0_1_CA_CPU B35 @ T26 PAD~D
@ RC97 1K_0402_5%~D RSVD49 @ T27 PAD~D
RSVD50 C35

PAD~D T28 @ F25 CFG6

PAD~D T29 @ RSVD8
F24 RSVD9
PAD~D T30 @ F23 CFG5
PAD~D T31 @ RSVD10 @ T32 PAD~D
D24 RSVD11 RSVD51 AJ32

1
PAD~D T33 @ G25 AK32 @ T34 PAD~D
PAD~D T35 @ RSVD12 RSVD52 @ RC54 RC53 @
G24 RSVD13
PAD~D T36 @ E23 1K_0402_5%~D 1K_0402_5%~D
PAD~D T37 @ RSVD14
D23 RSVD15
PAD~D T38 @ C30 AH27 @ T39 PAD~D

2
PAD~D T40 @ RSVD16 VCC_DIE_SENSE
A31 RSVD17
PAD~D T41 @ B30
PAD~D T42 @ RSVD18
B29 RSVD19
PAD~D T43 @ D30 AN35
RSVD20 RSVD54 CLK_XDP_ITP <7>
PAD~D T44 @ B31 AM35
RSVD21 RSVD55 CLK_XDP_ITP# <7>
PAD~D T45 @ A30
PAD~D T46 @ RSVD22
C29 RSVD23
PCIE Port Bifurcation Straps
PAD~D T47 @ J20
PAD~D T48 @ RSVD24 @ T49 PAD~D
B18 RSVD25 RSVD56 AT2
PAD~D T155 @ A19 AT1 @ T50 PAD~D 11: (Default) x16 - Device 1 functions 1 and 2 disabled
VCCIO_SEL RSVD57 @ T51 PAD~D
RSVD58 AR1
B B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
PAD~D T52 @ J15 RSVD27 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
KEY 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Sandy Bridge_rPGA_Rev1p0 CFG7

1
CONN@
RC56 @
1K_0402_5%~D

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 9 of 77
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+1.05V_RUN_VTT
+VCC_CORE +VCC_CORE

53AAG35 8.5A 22uFX12.

VCC1
AG34 VCC2 VCCIO1 AH13

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
1 1 1 1 1 AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
CC67 CC75 CC68 CC76 CC77 AG31 AC10 1 1 1 1 1 1 1 1 1 1 1
D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC5 VCCIO4 D
AG30 VCC6 VCCIO5 Y10
2 2 2 2 2

CC78

CC69

CC79

CC80

CC81

CC82

CC83

CC84

CC85

CC70

CC86
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
2 2 2 2 2 2 2 2 2 2 2
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
1 1 1 1 1 1 AF33 VCC13 VCCIO12 J11
@ AF32 H14
CC87 CC71 CC72 CC88 CC73 VCC14 VCCIO13
CC74 AF31 H12
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC15 VCCIO14
AF30 VCC16 VCCIO15 H11
2 2 2 2 2 2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13

PEG AND DDR

AF27 VCC19 VCCIO18 G12 1 1 1
AF26 VCC20 VCCIO19 F14 1 1 1 1 1

CC107

CC108

CC109
AD35 F13 + + +
VCC21 VCCIO20

CC89

CC90

CC91

CC92

CC93
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
2 2 2 2 2 2 2 2
AD32 VCC24 VCCIO23 E14
AD31 E12 @ @ @ @ @
VCC25 VCCIO24
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
+VCC_CORE
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
1 1 1 1 1 AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
C CC110 CC111 CC112 CC113 CC114 C
AC28 VCC38 VCCIO36 A14
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D AC27 A13
2 2 2 2 2 VCC39 VCCIO37
AC26 VCC40 VCCIO38 A12
+1.05V_RUN_VTT
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23

1
AA32 VCC44
AA31 Note: Place the PU resistors close to CPU RC60
VCC45 75_0402_1%~D
1 1 1 1 1 AA30 VCC46 RC61 close to CPU 300 - 1500mils
AA29 VCC47
CC115 CC116 CC117 CC118 CC119 AA28

2
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC48
AA27 VCC49
2 2 2 2 2 H_CPU_SVIDALRT#
AA26 VCC50 1 2 VIDALERT_N <59>

CORE SUPPLY
Y35 RC61 43_0402_5%~D
VCC51
Y34 VCC52
Y33 VCC53
Y32 VCC54
Y31 VCC55 +1.05V_RUN_VTT
1 1 1 1 1 Y30 VCC56
Y29 VCC57
CC120 CC121 CC122 CC123 CC124 Y28 VCC58

1
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D Y27 CAD Note: Place the PU
2 2 2 2 2 VCC59 RC63
Y26 VCC60 resistors close to CPU
V35 130_0402_1%~D RC63 close to CPU 300 - 1500mils

SVID
VCC61 H_CPU_SVIDALRT#
V34 VCC62 VIDALERT# AJ29
V33 AJ30 VIDSCLK
VIDSCLK <59>

2
VCC63 VIDSCLK VIDSOUT
V32 VCC64 VIDSOUT AJ28 VIDSOUT <59>
V31 Iccmax current changed for PDDG Rev0.7
VCC65
1 1
@
1
@
1
@
V30
V29
VCC66 CPU Power Rail Table
CC125 CC126 CC127 CC128 VCC67
V28 VCC68
S0 Iccmax
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D V27 Voltage Rail Voltage Current (A)
B 2 2 2 2 VCC69 B
V26 VCC70
U35 VCC71
U34 VCC72
VCC 0.65-1.3 53
U33 VCC73
U32 VCC74
U31 VCC75
VCCIO 1.05 8.5
U30 VCC76
U29 VCC77
U28 VCC78
VAXG 0.0-1.1 26
U27 VCC79
+VCC_CORE
U26 VCC80
R35 +VCC_CORE VCCPLL 1.8 3
VCC81
R34 VCC82
R33 VCC83

1
R32 VCC84
VDDQ 1.5 5
1 1 1 1 R31 Place RC66,RC70 near CPU RC66
@ VCC85
R30 VCC86 100_0402_1%~D
+ CC129 + CC130 + CC131 + CC132 R29 VCCSA 0.65-0.9 6
VCC87
SENSE LINES

470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D R28

2
VCC88 VCCSENSE_R
R27 VCC89 VCC_SENSE AJ35 1 2 VCCSENSE <59>
2 3 2 3 2 3 2 3 VSSSENSE_R @RC67
@ RC67 1
R26 VCC90 VSS_SENSE AJ34 2 0_0402_5%~D VSSSENSE <59> +1.5V_MEM 1.5 12-16 *
P35 @RC68
@ RC68 0_0402_5%~D
VCC91
P34 VCC92

1
P33 VCC93
P32 B10 VTT_SENSE_R 1 2 VTT_SENSE <58> RC70
VCC94 VCCIO_SENSE VSSIO_SENSE_R
@RC132
@ RC1321
P31 VCC95 VSSIO_SENSE A10 2 0_0402_5%~D VTT_GND <58> 100_0402_1%~D * Description
P30 @RC133
@ RC133 0_0402_5%~D
VCC96
P29 5A to Mem controller(+1.5V_CPU_VDDQ)

2
VCC97
1 1 P28 VCC98 5-6A to 2 DIMMs/channel
P27 VCC99 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
+ @CC133 + CC134 P26
470U_D2T_2VM~D 470U_D2T_2VM~D VCC100
A A
2 3 2 3

DELL CONFIDENTIAL/PROPRIETARY
Sandy Bridge_rPGA_Rev1p0
Compal Electronics, Inc.
Title
CONN@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 10 of 77
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU_VDDQ Source
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +15V_ALW AO4728L_SO8~D
8 1
7 2

1
10U_0805_6.3V6M~D

20K_0402_5%~D
6 3 1 @

CC135

RC73
RC72 5

1
100K_0402_5%~D JCPU1H
RC74

4
100K_0402_5%~D 2
AT35 AJ22

2
VSS1 VSS81
AT32 VSS2 VSS82 AJ19
D RUN_ON_CPU1.5VS3 D
AT29 AJ16

2
VSS3 VSS83

3
AT27 VSS4 VSS84 AJ13
AT25 VSS5 VSS85 AJ10
QC4B 1 AT22 AJ7
RUN_ON_CPU1.5VS3# DMN66D0LDW-7_SOT363-6~D VSS6 VSS86
5 AT19 VSS7 VSS87 AJ4
CC136 AT16 AJ3
4700P_0402_25V7K~D +V_DDR_REF QC5 +V_SM_VREF_CNT VSS8 VSS88
AT13 AJ2

4
2 NTR4503NT1G_SOT23-3~D VSS9 VSS89
AT10 VSS10 VSS90 AJ1

6
AT7 VSS11 VSS91 AH35
1 3 AT4 VSS12 VSS92 AH34
QC4A AT3 AH32
DMN66D0LDW-7_SOT363-6~D VSS13 VSS93
<38,40,43,56,64> RUN_ON 1 2 2 AR25 VSS14 VSS94 AH30

1
@ RC77 0_0402_5%~D AR22 AH29
RC78 VSS15 VSS95
AR19 AH28

1
2 100K_0402_5%~D VSS16 VSS96
<41> CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# <7,43> AR16 VSS17 VSS97 AH26
@ RC79 0_0402_5%~D AR13 AH25
VSS18 VSS98
1 2 AR10 AH22

2
@ RC134 0_0402_5%~D VSS19 VSS99
AR7 VSS20 VSS100 AH19
AR4 VSS21 VSS101 AH16
AR2 VSS22 VSS102 AH7
RUN_ON_CPU1.5VS3 AP34 AH4
+VCC_GFXCORE

JCPU1G
POWER AP31
AP28
AP25
VSS23
VSS24
VSS25
VSS103
VSS104
VSS105
AG9
AG8
AG4
26A AP22
VSS26 VSS106
AF6
VSS27 VSS107
AP19 AF5

SENSE
LINES
+VCC_GFXCORE VSS28 VSS108
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE <59> AP16 VSS29 VSS109 AF3
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <59> AP13 VSS30 VSS110 AF2
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 1 1 1 1 AT21 VAXG3 AP10 VSS31 VSS111 AE35

CC137

CC138

CC144

CC145

CC146

CC147

CC139

CC148

AT20 VAXG4 AP7 VSS32 VSS112 AE34

AT18 VAXG5 AP4 VSS33 VSS113 AE33
AT17 VAXG6 AP1 VSS34 VSS114 AE32
C 2 2 2 2 2 2 2 2 C
AR24 VAXG7 AN30 VSS35 VSS115 AE31
AR23 CC1782 1 0.1U_0402_10V7K~D AN27 AE30
VAXG8 VSS36 VSS116
AR21 AN25 AE29
AR20
VAXG9 +V_SM_VREF_CNT AN22
VSS37
VSS VSS117
AE28

VREF
VAXG10 CC1792 VSS38 VSS118
AR18 VAXG11 1 0.1U_0402_10V7K~D AN19 VSS39 VSS119 AE27
AR17 VAXG12 AN16 VSS40 VSS120 AE26
AP24 VAXG13 SM_VREF AL1 AN13 VSS41 VSS121 AE9
AP23 CC1492 1 0.1U_0402_10V7K~D AN10 AD7
VAXG14 VSS42 VSS122
AP21 VAXG15 AN7 VSS43 VSS123 AC9
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 AP20 +V_SM_VREF should AN4 AC8

VAXG16 VSS44 VSS124
CC151

CC141

CC152

CC153

AP18 have 10 mil trace width CC1502 1 0.1U_0402_10V7K~D AM29 AC6

VAXG17 VSS45 VSS125
AP17 VAXG18 AM25 VSS46 VSS126 AC5
AN24 VAXG19 AM22 VSS47 VSS127 AC3
2 2 2 2
AN23 VAXG20 AM19 VSS48 VSS128 AC2
AN21 +1.5V_CPU_VDDQ @PJP1
@ PJP1 AM16 AB35
VAXG21 VSS49 VSS129
AN20 VAXG22 DDR3 -1.5V RAILS 1 2 AM13 VSS50 VSS130 AB34
AN18 VAXG23 AM10 VSS51 VSS131 AB33
AN17 PAD-OPEN 4x4m AM7 AB32
VAXG24 5A VSS52 VSS132
GRAPHICS

AM24 VAXG25 VDDQ1 AF7 +1.5V_MEM AM4 VSS53 VSS133 AB31

AM23 AF4 @PJP2
@ PJP2 AM3 AB30
VAXG26 VDDQ2 VSS54 VSS134
AM21 VAXG27 VDDQ3 AF1 1 2 AM2 VSS55 VSS135 AB29
470U_D2T_2VM~D

470U_D2T_2VM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2_2VM_R6M~D
1 1 AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1 1 AM1 VSS56 VSS136 AB28
@ AM18 AC4 PAD-OPEN 4x4m AL34 AB27
VAXG29 VDDQ5 VSS57 VSS137
CC159

CC158

CC161

CC162

CC163

CC164

CC165

CC166

CC167
+ + AM17 AC1 + AL31 AB26
VAXG30 VDDQ6 VSS58 VSS138
AL24 VAXG31 VDDQ7 Y7 AL28 VSS59 VSS139 Y9
2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4 AL25 VSS60 VSS140 Y8
2 3 2 3 2
AL21 VAXG33 VDDQ9 Y1 AL22 VSS61 VSS141 Y6
AL20 VAXG34 VDDQ10 U7 AL19 VSS62 VSS142 Y5
AL18 VAXG35 VDDQ11 U4 AL16 VSS63 VSS143 Y3
AL17 VAXG36 VDDQ12 U1 AL13 VSS64 VSS144 Y2
AK24 VAXG37 VDDQ13 P7 AL10 VSS65 VSS145 W35
AK23 VAXG38 VDDQ14 P4 AL7 VSS66 VSS146 W34
B B
AK21 VAXG39 VDDQ15 P1 AL4 VSS67 VSS147 W33
AK20 VAXG40 AL2 VSS68 VSS148 W32
AK18 VAXG41 AK33 VSS69 VSS149 W31
AK17 VAXG42 AK30 VSS70 VSS150 W30
AJ24 VAXG43 AK27 VSS71 VSS151 W29
AJ23 VAXG44 AK25 VSS72 VSS152 W28
AJ21 VAXG45 AK22 VSS73 VSS153 W27
AJ20 VAXG46 AK19 VSS74 VSS154 W26
AJ18 VAXG47 AK16 VSS75 VSS155 U9
AJ17 VAXG48 AK13 VSS76 VSS156 U8
AH24 6A AK10 U6
SA RAIL

VAXG49 VSS77 VSS157

AH23 VAXG50 AK7 VSS78 VSS158 U5
AH21 VAXG51 VCCSA1 M27 +VCC_SA AK4 VSS79 VSS159 U3
10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D
AH20 VAXG52 VCCSA2 M26 AJ25 VSS80 VSS160 U2
AH18 VAXG53 VCCSA3 L26
AH17 VAXG54 VCCSA4 J26 1 1 1 1 1

@CC171
@
VCCSA5 J25
CC168

CC169

CC170

CC171

CC172
J24 +
VCCSA6 Sandy Bridge_rPGA_Rev1p0
VCCSA7 H26
2 2 2 2
VCCSA8 H25
2
CONN@
1.8V RAIL

3A 1 2 +GND_VCC_SA <62>
@ RC137 0_0402_5%~D
+1.8V_RUN B6 H23 VCCSA_SENSE <62>
MISC

VCCPLL1 VCCSA_SENSE
A6 VCCPLL2
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

330U_D2_2.5VM_R6M~D

1 1 1 1 A2 VCCPLL3
1
CC173

CC174

CC175

CC176

+ C22 H_FC_C22 RC81 @

FC_C22 0_0402_5%~D
VCCSA_VID1 C24 1 2 VCCSA_VID_1 <62>
2 2 2
10K_0402_5%~D

@ RC138 0_0402_5%~D
1

A 2 A
2
RC83

Sandy Bridge_rPGA_Rev1p0

CONN@
DELL CONFIDENTIAL/PROPRIETARY
2

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 11 of 77
5 4 3 2 1
 5 4 3 2 1

+V_DDR_REF 1 2 +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel

@ RD1 0_0402_5%~D JDIMM1 CONN@
1 2
VREF_DQ VSS
JDIMM1 H=5.2

2.2U_0603_6.3V6K~D
+DIMM0_1_VREF_CPU 1 2 3 4 DDR_A_D4
@ RD7 0_0402_5%~D DDR_A_D0 VSS DQ4 DDR_A_D5
5 DQ0 DQ5 6

0.1U_0402_16V4Z~D
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
1 1 9 VSS DQS0# 10
11 12 DDR_A_DQS0
DM0 DQS0

CD1

CD2
13 VSS VSS 14
DDR_A_D2 15 16 DDR_A_D6 +1.5V_MEM
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13 RD27
25 VSS VSS 26
D DDR_A_DQS#1 1K_0402_1%~D D
27 DQS1# DM1 28
All VREF traces should DDR_A_DQS1 29 30 DDR3_DRAMRST#_R
<8> DDR_A_DQS#[0..7] DQS1 RESET#
have 10 mil trace width 31 32

2
DDR_A_D10 VSS VSS DDR_A_D14
<8> DDR_A_D[0..63] 33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15 DDR3_DRAMRST#_R 1 2
DQ11 DQ15 <13> DDR3_DRAMRST#_R DDR3_DRAMRST# <7>
37 38 RD28 1K_0402_1%~D
<8> DDR_A_DQS[0..7] VSS VSS
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
<8> DDR_A_MA[0..15] Populate RD1 for Intel DDR3 41 DQ17 DQ21 42
43 44
VREFDQ multiple methods M1 DDR_A_DQS#2 45
VSS VSS
46
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
Note: 51 DQ18 DQ23 52
DDR_A_D19 53 54
Check voltage tolerance of 55
DQ19 VSS
56 DDR_A_D28
DDR_A_D24 VSS DQ28 DDR_A_D29
VREF_DQ at the DIMM socket 57 DQ24 DQ29 58
DDR_A_D25 59 60
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72
Layout Note:
Place near JDIMM1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
<8> DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
+1.5V_MEM DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
C C
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

93 VDD VDD 94
1 1 1 1 DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
CD3

CD4

CD5

CD6

99 VDD VDD 100

M_CLK_DDR0 101 102 M_CLK_DDR1
2 2 2 2 <8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<8> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <8>
105 VDD VDD 106
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 <8>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<8> DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# <8>
111 VDD VDD 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
DDR_A_CAS# 115 116 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 VDD VDD 118
DDR_A_MA13 119 120 M_ODT1 +DIMM0_1_VREF_CA
+1.5V_MEM A13 ODT1 M_ODT1 <8>
DDR_CS1_DIMMA# 121 122
<8> DDR_CS1_DIMMA# S1# NC
123 VDD VDD 124
125 TEST VREF_CA 126 1 2 +V_DDR_REF
127 128 @ RD29 0_0402_5%~D
VSS VSS
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132 1 2 +DIMM0_1_CA_CPU
330U_SX_2VY~D

1 133 134 1 1 @ RD31 0_0402_5%~D

VSS VSS
@ CD13

CD15

CD16
1 1 1 1 1 1 1 DDR_A_DQS#4 135 136
DQS4# DM4
CD7

CD8

CD9

CD10

CD11

CD51

CD14

+ DDR_A_DQS4 137 138

DQS4 VSS DDR_A_D38
139 VSS DQ38 140
DDR_A_D34 DDR_A_D39 2 2
141 DQ34 DQ39 142
2 2 2 2 2 2 2 2 DDR_A_D35 143 DQ35 VSS 144
145 146 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150
B DQ41 VSS DDR_A_DQS#5 B
151 VSS DQS5# 152
153 154 DDR_A_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS VSS 168
Layout Note: DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS6# DM6
171 172
Place near JDIMM1.203,204 173
DQS6 VSS
174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
+0.75V_DDR_VTT 189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 DQ58 DQ62 192
DDR_A_D59 193 194 DDR_A_D63
DQ59 DQ63
195 VSS VSS 196
RD21 2 10K_0402_5%~D 197 198
SA0 EVENT#
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+3.3V_RUN 199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,13,14,15,28,37>

1 1 1 1 1 2 201 SA1 SCL 202 DDR_XDP_WAN_SMBCLK <7,13,14,15,28,37>
RD3 10K_0402_5%~D 1 1 203 204 +0.75V_DDR_VTT
VTT VTT
CD17

CD18

CD19

CD20

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT
CD21

CD22

2 2 2 2
205 GND1 GND2 206
2 2
TYCO_2-2013289-2~D
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 12 of 77
5 4 3 2 1
 5 4 3 2 1

2-3A to 1 DIMMs/channel
All VREF traces should +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM
have 10 mil trace width JDIMM2 CONN@
1 VREF_DQ VSS 2
3 4 DDR_B_D4
VSS DQ4
JDIMM2 H=9.2

2.2U_0603_6.3V6K~D
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

0.1U_0402_16V4Z~D
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
<8> DDR_B_DQS#[0..7] 1 1 9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0

CD23

CD24
<8> DDR_B_D[0..63] Populate RD4 for Intel DDR3 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
VREFDQ multiple methods M1 2 2 DDR_B_D3 17
DQ2 DQ6
18 DDR_B_D7
<8> DDR_B_DQS[0..7] DQ3 DQ7
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
D <8> DDR_B_MA[0..15] DQ8 DQ12 D
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 DQS1 RESET# 30 DDR3_DRAMRST#_R <12>
Note: 31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
Layout Note: 55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
Place near JDIMM2 DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
+1.5V_MEM
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD VDD 76
77 78 DDR_B_MA15
NC A15
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_B_BS2 79 80 DDR_B_MA14
<8> DDR_B_BS2 BA2 A14
1 1 1 1 81 VDD VDD 82
C DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
CD25

CD26

CD27

CD28

DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD VDD 88
2 2 2 2 DDR_B_MA8 DDR_B_MA6
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <8>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
+1.5V_MEM <8> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <8>
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 <8>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<8> DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# <8>
111 VDD VDD 112
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

DDR_B_WE# 113 114 DDR_CS2_DIMMB#

<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
1 117 VDD VDD 118
+DIMM0_1_VREF_CA
@CD35
@

1 1 1 1 1 1 1 DDR_B_MA13 119 120 M_ODT3

A13 ODT1 M_ODT3 <8>
CD29

CD30

CD31

CD32

CD33

CD34

CD35

CD36

+ DDR_CS3_DIMMB# 121 122

<8> DDR_CS3_DIMMB# S1# NC
123 VDD VDD 124
125 TEST VREF_CA 126
2 2 2 2 2 2 2 2
127 VSS VSS 128

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS VSS 134 1 1
DDR_B_DQS#4 135 136
DQS4# DM4

CD37

CD38
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
139 VSS DQ38 140
DDR_B_D34 DDR_B_D39 2 2
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS DDR_B_D44
145 VSS DQ44 146
B DDR_B_D40 DDR_B_D45 B
147 DQ40 DQ45 148
Layout Note: DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 152
Place near JDIMM2.203,204 153
VSS DQS5#
154 DDR_B_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
+0.75V_DDR_VTT DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_B_D60

DDR_B_D56 VSS DQ60 DDR_B_D61
1 1 1 1 181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS
CD39

CD40

CD41

CD42

185 186 DDR_B_DQS#7

VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
2 2 2 2
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS VSS 196
+3.3V_RUN 197 198
SA0 EVENT#
+3.3V_RUN 199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,12,14,15,28,37>
2 1 201 SA1 SCL 202 DDR_XDP_WAN_SMBCLK <7,12,14,15,28,37>
RD5 10K_0402_5%~D +0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D
RD6

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

1 1 205 GND1 GND2 206

A A
CD43

CD44

TYCO_2-2013310-2~D
2

2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 13 of 77
5 4 3 2 1
 5 4 3 2 1

PCH_AZ_SYNC is sampled +3.3V_ALW_PCH CONN@

JXDP2
CMOS_CLR1 CMOS setting at the rising edge of RSMRST# pin. 1 GND0 GND1 2
So signal should be PU to the ALWAYS rail. USB_OC0#_R XDP_FN0 XDP_FN16
Shunt Clear CMOS <17> USB_OC0#_R USB_OC1#_R @ RH1
1 2
33_0402_5%~D XDP_FN1 +3.3V_ALW_PCH
3 OBSFN_A0 OBSFN_C0 4
XDP_FN17
1 2 5 OBSFN_A1 OBSFN_C1 6
<17> USB_OC1#_R USB_OC2# @ RH3 33_0402_5%~D XDP_FN2
Open Keep CMOS +3.3V_ALW_PCH <17> USB_OC2# USB_OC3# @ RH4
1 2
33_0402_5%~D XDP_FN3 XDP_FN0
7 GND2 GND3 8
XDP_FN8
1 2 1 9 OBSDATA_A0 OBSDATA_C0 10
<17> USB_OC3# USB_OC4# @ RH5 33_0402_5%~D XDP_FN4 @ XDP_FN1 XDP_FN9
<17> USB_OC4# 1 2 11 OBSDATA_A1 OBSDATA_C1 12
ME_CLR1 TPM setting USB_OC5# @ RH6 1 2 33_0402_5%~D XDP_FN5 CH1 13 14
<17> USB_OC5# GND4 GND5

1
USB_OC6# @ RH7 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_16V4Z~D XDP_FN2 15 16 XDP_FN10
RH66 <17> USB_OC6# SIO_EXT_SMI# @ RH8 33_0402_5%~D XDP_FN7 2 XDP_FN3 OBSDATA_A2 OBSDATA_C2 XDP_FN11
Shunt Clear ME RTC Registers 1K_0402_5%~D <17,41> SIO_EXT_SMI# SLP_ME_CSW_DEV#@ RH9
1 2
33_0402_5%~D XDP_FN8
17 OBSDATA_A3 OBSDATA_C3 18
1 2 19 GND6 GND7 20
<18,40> SLP_ME_CSW_DEV# USB_MCARD1_DET#@ RH10 33_0402_5%~D XDP_FN9
Open Keep ME RTC Registers <18,37> USB_MCARD1_DET# HDD_DET#_R @ RH12
1 2
33_0402_5%~D XDP_FN10
21 OBSFN_B0 OBSFN_D0 22
1 2 23 24

2
BBS_BIT0_R @ RH13 33_0402_5%~D XDP_FN11 OBSFN_B1 OBSFN_D1
1 2 25 GND8 GND9 26
GPIO36 @ RH14 1 2 33_0402_5%~D XDP_FN12 XDP_FN4 27 28 XDP_FN12
+RTC_CELL PCH_AZ_SYNC <18> GPIO36 GPIO37 @ RH15 33_0402_5%~D XDP_FN13 XDP_FN5 OBSDATA_B0 OBSDATA_D0 XDP_FN13
1 2 29 OBSDATA_B1 OBSDATA_D1 30
<18> GPIO37 EN_ESATA_RPTR# @ RH16 33_0402_5%~D XDP_FN14
<18> EN_ESATA_RPTR# 1 2 31 GND10 GND11 32

1
TEMP_ALERT# @ RH17 1 2 33_0402_5%~D XDP_FN15 XDP_FN6 33 34 XDP_FN14
<18,40> TEMP_ALERT# OBSDATA_B2 OBSDATA_D2
1

RH282 @ PCH_GPIO15 @ RH18 1 2 33_0402_5%~D XDP_FN16 XDP_FN7 35 36 XDP_FN15

D
RH38 100K_0402_5%~D <18> PCH_GPIO15 SIO_EXT_SCI#_R @ RH19 33_0402_5%~D XDP_FN17 @ RH283 1K_0402_5%~D OBSDATA_B3 OBSDATA_D3 D
1 2 37 GND12 GND13 38
<18> SIO_EXT_SCI#_R +3.3V_ALW_PCH
330K_0402_5%~D @ RH20 33_0402_5%~D
<41,59> 1.05V_0.8V_PWROK 1 21.05V_0.8V_PWROK_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
<16,41> PCH_RSMRST#_Q 2 1 RSMRST#_XDP <7,16> SIO_PWRBTN#_R 1 2 PCH_PWRBTN#_XDP 41 42

2
@ RH24 1K_0402_5%~D @ RH21 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
43 44
2

PCH_INTVRMEN VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP

45 HOOK2 RESET#/HOOK6 46
47 48 XDP_DBRESET#
HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,16>
1

@ RH284 0_0402_5%~D 49 50
RH39 @ DDR_XDP_WAN_SMBDAT_R2 GND14 GND15 PCH_JTAG_TDO
On Die PLL VR is supplied by <7,12,13,15,28,37> DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
330K_0402_5%~D CH2 1 2 DDR_XDP_WAN_SMBCLK_R2 53 54
1.5V when sampled high, 1.8 V <7,12,13,15,28,37> DDR_XDP_WAN_SMBCLK SCL TRST#
15P_0402_50V8J~D @ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
TCK1 TDI
when sampled low 2 1 PCH_RTCX1 PCH_JTAG_TCK 57 58 PCH_JTAG_TMS
2

TCK0 TMS
59 GND16 GND17 60
YH1

1
1 G 2 SAMTE_BSH-030-01-L-D-A
INTVRMEN- Integrated SUS RH2
10M_0402_5%~D UH4A
1.1V VRM Enable 4 3
G
* High - Enable Internal VRs CH3 A20 C38 LPC_LAD0
LPC_LAD0 <34,35,40,41>

2
15P_0402_50V8J~D 32.768KHZ_12.5PF_Q13MC1461000~D RTCX1 FWH0 / LAD0 LPC_LAD1 +3.3V_RUN
A38

LPC
Low - Enable External VRs FWH1 / LAD1 LPC_LAD1 <34,35,40,41>
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 B37 LPC_LAD2
RTCX2 FWH2 / LAD2 LPC_LAD2 <34,35,40,41>
@ RH286 C37 LPC_LAD3
0_0402_5%~D FWH3 / LAD3 LPC_LAD3 <34,35,40,41>
+RTC_CELL 1 2 PCH_RTCRST# D20
RH22 20K_0402_5%~D RTCRST# LPC_LFRAME# PCH_GPIO33
FWH4 / LFRAME# D36 LPC_LFRAME# <34,35,40,41> 2 1
1 2 SRTCRST# G22 RH355 100K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST# LPC_LDRQ0#
E36

RTC
LDRQ0# LPC_LDRQ0# <40>
1 2 INTRUDER# K22 K36 LPC_LDRQ1# IRQ_SERIRQ 2 1
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <40>
RH11 1M_0402_5%~D RH28 8.2K_0402_5%~D
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <34,35,40,41>
@ CH100 PCH_AZ_SYNC_Q2 1
27P_0402_50V8J~D RH41 10K_0402_5%~D
1 1 2 2 1 1 2 2 SATA0RXN AM3 PSATA_PRX_DTX_N0_C <28>
1 2 PCH_AZ_BITCLK N34 AM1 BBS_BIT0_R 1 2
<45> PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <28>

SATA 6G
RH32 33_0402_5%~D AP7 HDD RH52 4.7K_0402_5%~D
SATA0TXN PSATA_PTX_DRX_N0_C <28>
<45> PCH_AZ_MDC_SYNC 1 2 PCH_AZ_SYNC_Q PCH_AZ_SYNC L34 HDA_SYNC SATA0TXP AP5 PSATA_PTX_DRX_P0_C <28>
@ @ RH33 33_0402_5%~D
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<30> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <29>
1 2 1 2 SATA1RXP AM8 SATA_ODD_PRX_DTX_P1_C <29>
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D 1 2 PCH_AZ_RST# K34 AP11 ODD/ E Module Bay
<45> PCH_AZ_MDC_RST# HDA_RST# SATA1TXN SATA_ODD_PTX_DRX_N1_C <29>
CMOS place near DIMM RH34 33_0402_5%~D AP10
C
SATA1TXP SATA_ODD_PTX_DRX_P1_C <29> C
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
<30> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
SATA2RXP AD5
<30> PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT <45> PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34 HDA_SDIN1 SATA2TXN AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
SATA2TXP
<30> PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @ RH35 10K_0402_5%~D

IHDA
RH26 33_0402_5%~D +3.3V_ALW_PCH HDA_SDIN2
SATA3RXN AB8
<30> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# 1 2 A34 HDA_SDIN3 SATA3RXP AB10 No Reboot Strap
RH27 33_0402_5%~D @ RH287 1K_0402_5%~D AF3
SATA3TXN
<30> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK <45> PCH_AZ_MDC_SDOUT 1 2 SATA3TXP AF1 Low = Default
1 RH25 33_0402_5%~D RH36 33_0402_5%~D PCH_AZ_SDOUT A36 SPKR

SATA
HDA_SDO High = No Reboot
<40> ME_FWP 1 2 SATA4RXN Y7 ESATA_PRX_DTX_N4_C <45>
@ CH101 +3.3V_ALW_PCH RH50 1K_0402_5%~D Y5
SATA4RXP ESATA_PRX_DTX_P4_C <45>
27P_0402_50V8J~D PCH_GPIO33 C36 AD3 E-SATA
2 HDA_DOCK_EN# / GPIO33 SATA4TXN ESATA_PTX_DRX_N4_C <45>
SATA4TXP AD1 ESATA_PTX_DRX_P4_C <45>
1

USB30_SMI# N32
<29> USB30_SMI# HDA_DOCK_RST# / GPIO13
@ RH288 Y3
SATA5RXN SATA_PRX_DKTX_N5_C <39>
0_0603_5%~D Y1
SATA5RXP SATA_PRX_DKTX_P5_C <39>
SATA5TXN AB3 SATA_PTX_DKRX_N5_C <39> DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2

JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <39>

+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN

JTAG
JTAG_TMS SATAICOMPO
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1 JTAG_TDO +1.05V_RUN
SATA3RCOMPO AB12
+3.3V_RUN
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

AB13 SATA3_COMP 1 2
SATA3COMPI
1

RH42 49.9_0402_1%~D
+3.3V_RUN
RH48

RH49

RH47
1

PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2

@ RH295 SPI_CLK SATA3RBIAS RH46 750_0402_1%~D
SPI_MOSI (PCH_SPI_DO)

1
8.2K_0402_5%~D @ @ @ PCH_SPI_CS0# Y14
2

High: Enable IntelΓ Anti-Theft Technology SPI_CS0# RH30

Left floating: Disable Intel Anti-Theft Technology PCH_SPI_CS1# T1 10K_0402_5%~D

SPI
2

SPI_CS1# SATA_ACT#
SATALED# P3
PCH_SPI_DO SATA_ACT# <44>

2
PCH_SPI_DO V4 V14 HDD_DET#_R @ RH290 1 2 0_0402_5%~D
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <28>
B
1 2 B
@ R933 0_0402_5%~D PCH_SPI_DIN BBS_BIT0_R

S
U3 SPI_MISO SATA1GP / GPIO19 P1 1 3 PCH_SATA_MOD_EN# <41>
S

PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC
CougarPoint_Rev_1p0 QH1 BSS138W-7-F_SOT323-3~D

G
2
1 2 QH7
RH31 1M_0402_5%~D SSM3K7002FU_SC70-3~D
G

<7,17> PCH_PLTRST#
2

BBS_BIT0 - BIOS BOOT STRAP BIT 0

PCH_PLTRST#_EC
<17,35,37,38,40,41> PCH_PLTRST#_EC

+3.3V_SPI C745
+3.3V_SPI C746 0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D 1 2
1 2
1

200 MIL SO8

1

R888
200 MIL SO8
1

R890 3.3K_0402_5%~D
16Mb Flash ROM 1 JSPI1
3.3K_0402_5%~D R891 R892 SPI_PCH_CS1#
64Mb Flash ROM 3.3K_0402_5%~D X76@ U53 3.3K_0402_5%~D 1 1
2 PCH_SPI_CS1# RH345
1 2
0_0402_5%~D
2

SPI_PCH_CS1# 1 2
X76@ U52 2 SPI_PCH_CS1#_R 1 8 3 SPI_PCH_DO 1 2
2

SPI_PCH_CS0# /CS VCC 3

1 2 SPI_PCH_CS0#_R 1 8 R936 22_0402_5%~D 4 PCH_SPI_DO RH346 0_0402_5%~D
2

/CS VCC SPI_PCH_DIN 1 4

R935 47_0402_5%~D 2 SPI_DIN32 2 DO /HOLD 7 5 5 SPI_PCH_DIN 1 2
SPI_PCH_DIN 1 2 SPI_DIN64 2 7 R895 33_0402_5%~D 6 PCH_SPI_DIN RH347 0_0402_5%~D
DO /HOLD SPI_WP#_SEL SPI_CLK32 6
R894 33_0402_5%~D 1 2 3 /WP CLK 6 1 2 SPI_PCH_CLK 7 7 SPI_PCH_CLK 1 2
<40> SPI_WP#_SEL SPI_WP#_SEL 1 2 3 6 SPI_CLK64 1 2 SPI_PCH_CLK @ R896 0_0402_5%~D R897 33_0402_5%~D 8 PCH_SPI_CLK RH348 0_0402_5%~D
/WP CLK SPI_DO32 1 8
@ R898 0_0402_5%~D R899 33_0402_5%~D 4 GND DIO 5 2 SPI_PCH_DO 9 9 SPI_PCH_CS0# 1 2
4 5 SPI_DO64 1 2 SPI_PCH_DO R900 33_0402_5%~D 10 PCH_SPI_CS0# RH349 0_0402_5%~D
GND DIO R901 33_0402_5%~D 10
11 11 +3.3V_SPI
W25Q16BVSSIG_SO8~D 12 +3.3V_M
W25Q64BVSSIG_SO8~D 12
13 13
14 14 1 2
15 RH350 0_0402_5%~D
SPI_CLK32 15
16 16
SPI_CLK64
1
1

@ 17
@ RE2 G1
G2 18
A RE1 33_0402_5%~D A
33_0402_5%~D
2
2

1
1 @ HRS_FH12-16S-0P5SH(55)~D
@ CE1
CE2 27P_0402_50V8J~D CONN@
27P_0402_50V8J~D 2
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 14 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN

www.qdzbwx.com QH5A

2
DMN66D0LDW-7_SOT363-6~D

MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK <7,12,13,14,28,37>

5
MEM_SMBDATA 3 4 DDR_XDP_WAN_SMBDAT <7,12,13,14,28,37>
QH5B
D FollowDG0.9Devicedown&Express/Mini UH4B DMN66D0LDW-7_SOT363-6~D D

cardtopology 1 2
PCIE_PRX_WANTX_N1 BG34 @RH296
@ RH296 0_0402_5%~D
<37> PCIE_PRX_WANTX_N1 PERN1
PCIE_PRX_WANTX_P1 BJ34 E12 PCH_SMB_ALERT#
<37> PCIE_PRX_WANTX_P1 PERP1 SMBALERT# / GPIO11 +3.3V_ALW_PCH
MiniWWAN (Mini Card 1)---> PCIE_PTX_WANRX_N1 AV32 1 2
<37> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1 PETN1 MEM_SMBCLK @RH297
@ RH297 0_0402_5%~D
<37> PCIE_PTX_WANRX_P1 AU32 PETP1 SMBCLK H14

PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA SML1_SMBCLK 1 2

<37> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 RH298 2.2K_0402_5%~D
<37> PCIE_PRX_WLANTX_P2 PERP2
MiniWLAN (Mini Card 2)---> PCIE_PTX_WLANRX_N2 BB32 SML1_SMBDATA 1 2
<37> PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 PETN2 RH299 2.2K_0402_5%~D
AY32

SMBUS
<37> PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
SML0ALERT# / GPIO60 A12 DDR_HVREF_RST_PCH <7>
PCIE_PRX_EXPTX_N3 BG36 +3.3V_ALW_PCH
<38> PCIE_PRX_EXPTX_N3 PERN3
PCIE_PRX_EXPTX_P3 BJ36 C8 LAN_SMBCLK
<38> PCIE_PRX_EXPTX_P3 PERP3 SML0CLK LAN_SMBCLK <32>
EXPRESS Card---> PCIE_PTX_EXPRX_N3 AV34
<38> PCIE_PTX_EXPRX_N3 PCIE_PTX_EXPRX_P3 PETN3 LAN_SMBDATA DDR_HVREF_RST_PCH
<38> PCIE_PTX_EXPRX_P3 AU34 PETP3 SML0DATA G12 LAN_SMBDATA <32> 2 1
RH300 1K_0402_5%~D
PCIE_PRX_EMBTX_N4 BF36 GPIO74 2 1
<29> PCIE_PRX_EMBTX_N4 PERN4
PCIE_PRX_EMBTX_P4 BE36 RH301 10K_0402_5%~D
<29> PCIE_PRX_EMBTX_P4 PERP4
E3 Module Bay---> PCIE_PTX_EMBRX_N4 AY34 C13 GPIO74 MEM_SMBCLK 2 1
<29> PCIE_PTX_EMBRX_N4 PCIE_PTX_EMBRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 RH302 2.2K_0402_5%~D
<29> PCIE_PTX_EMBRX_P4 BB34 PETP4
E14 SML1_SMBCLK MEM_SMBDATA 2 1

PCI-E*
PCIE_PRX_WPANTX_N5 SML1CLK / GPIO58 SML1_SMBCLK <41> RH303 2.2K_0402_5%~D
<37> PCIE_PRX_WPANTX_N5 BG37 PERN5
1/2vMINI CARD-3 PCIE PCIE_PRX_WPANTX_P5 BH37 M16 SML1_SMBDATA PCH_SMB_ALERT# 2 1
<37> PCIE_PRX_WPANTX_P5 PERP5 SML1DATA / GPIO75 SML1_SMBDATA <41>
PCIE_PTX_WPANRX_N5 AY36 RH304 10K_0402_5%~D
(Mini Card 3)---> <37> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5
<37> PCIE_PTX_WPANRX_P5 PETP5
PCIE_PRX_MMITX_N6 BJ38
<36> PCIE_PRX_MMITX_N6 PERN6
PCIE_PRX_MMITX_P6 BG38

Controller
<36> PCIE_PRX_MMITX_P6 PERP6 +3.3V_LAN
MMI ---> PCIE_PTX_MMIRX_N6 AU36 M7 PCH_CL_CLK1
<36> PCIE_PTX_MMIRX_N6 PETN6 CL_CLK1 PCH_CL_CLK1 <37>
PCIE_PTX_MMIRX_P6 AV36
C <36> PCIE_PTX_MMIRX_P6 PETP6 C

Link
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1 LAN_SMBCLK 2 1
<32> PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 <37>
PCIE_PRX_GLANTX_P7 BJ40 RH305 2.2K_0402_5%~D
<32> PCIE_PRX_GLANTX_P7 PERP7
10/100/1G LAN ---> PCIE_PTX_GLANRX_N7 AY40 LAN_SMBDATA 2 1
<32> PCIE_PTX_GLANRX_N7 PCIE_PTX_GLANRX_P7 PETN7 PCH_CL_RST1# RH306 2.2K_0402_5%~D
<32> PCIE_PTX_GLANRX_P7 BB40 PETP7 CL_RST1# P10 PCH_CL_RST1# <37>
BE38 PERN8
BC38 RH80
PERP8 GFX_CLK_REQ#
AW38 PETN8 +3.3V_ALW_PCH 2 1
AY38 PETP8 10K_0402_5%~D
M10 GFX_CLK_REQ#
PEG_A_CLKRQ# / GPIO47

1
PCIE_MINI1# D
<37> CLK_PCIE_MINI1# 2 1 Y40 CLKOUT_PCIE0N
@ RH3072 1 0_0402_5%~D PCIE_MINI1 Y39 2 QH2
<37> CLK_PCIE_MINI1 CLKOUT_PCIE0P <40,50> 3.3V_RUN_GFX_ON
MiniWWAN (Mini Card 1)---> +3.3V_ALW_PCH @ RH3082 1 0_0402_5%~D AB37 CLK_PCIE_VGA# G SSM3K7002FU_SC70-3~D
CLKOUT_PEG_A_N CLK_PCIE_VGA# <47>

CLOCKS
RH81 10K_0402_5%~D MINI1CLK_REQ# J2 AB38 CLK_PCIE_VGA S
<37> MINI1CLK_REQ#

3
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <47>

2 1 PCIE_LAN# AB49 AV22 CLK_CPU_DMI#

<32> CLK_PCIE_LAN# @ RH82 2 CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <7>
<32> CLK_PCIE_LAN 1 0_0402_5%~D PCIE_LAN AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_CPU_DMI
CLK_CPU_DMI <7>
10/100/1G LAN ---> @ RH83 0_0402_5%~D
LANCLK_REQ# M1
<32> LANCLK_REQ# PCIECLKRQ1# / GPIO18
AM12 CLK_CPU_DPLL#
CLKOUT_DP_N CLK_CPU_DPLL CLK_CPU_DPLL# <7>
CLKOUT_DP_P AM13 CLK_CPU_DPLL <7>
2 1 PCIE_MMI# AA48 CLK_BUF_DMI# 1 2
<36> CLK_PCIE_MMI# @ RH85 2 PCIE_MMI CLKOUT_PCIE2N CLK_BUF_DMI
MMI Card---> <36> CLK_PCIE_MMI 1 0_0402_5%~D AA47 CLKOUT_PCIE2P
RH74 1 2 10K_0402_5%~D
+3.3V_RUN @ RH86 1 2 0_0402_5%~D BF18 CLK_BUF_DMI# RH75 10K_0402_5%~D
RH87 10K_0402_5%~D MMICLK_REQ# CLKIN_DMI_N CLK_BUF_DMI
<36> MMICLK_REQ# V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18
CLK_BUF_BCLK 1 2
RH91 10K_0402_5%~D
2 1 PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK
<37> CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N
MiniWPAN (Mini Card 3)---> @ RH88 2 1 0_0402_5%~D PCIE_MINI3 Y36 BG30 CLK_BUF_BCLK
B <37> CLK_PCIE_MINI3 CLKOUT_PCIE3P CLKIN_GND1_P B
+3.3V_ALW_PCH @ RH90 2 1 0_0402_5%~D CLK_BUF_DOT96# 1 2
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
<37> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25
G24 CLK_BUF_DOT96# RH77 10K_0402_5%~D
CLKIN_DOT_96N CLK_BUF_DOT96
CLKIN_DOT_96P E24
2 1 PCIE_EXP# Y43 CLK_BUF_CKSSCD# 1 2
<38> CLK_PCIE_EXP# CLKOUT_PCIE4N
Express card---> @ RH92 2 1 0_0402_5%~D PCIE_EXP Y45 CLK_BUF_CKSSCD RH78 1 2 10K_0402_5%~D
<38> CLK_PCIE_EXP CLKOUT_PCIE4P
+3.3V_ALW_PCH @ RH93 2 1 0_0402_5%~D AK7 CLK_BUF_CKSSCD# RH79 10K_0402_5%~D
RH94 10K_0402_5%~D EXPCLK_REQ# CLKIN_SATA_N CLK_BUF_CKSSCD
<38> EXPCLK_REQ# L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5
CLK_PCH_14M 1 2
RH183 10K_0402_5%~D
2 1 PCIE_MINI2# V45 K45 CLK_PCH_14M
<37> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH95 2 1 0_0402_5%~D PCIE_MINI2 V46
<37> CLK_PCIE_MINI2 CLKOUT_PCIE5P
MiniWLAN (Mini Card 2)---> +3.3V_ALW_PCH @ RH96 2 1 0_0402_5%~D
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<37> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>
CLOCK TERMINATION for FCIM and need close to PCH
AB42 V47 XTAL25_IN 2 1
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT RH309
AB40 V49 @ 0_0402_5%~D
CLKOUT_PEG_B_P XTAL25_OUT

1
+3.3V_ALW_PCH 1 2 PEG_B_CLKRQ# E6 RH99
RH98 10K_0402_5%~D PEG_B_CLKRQ# / GPIO56 1M_0402_5%~D
Y47 XCLK_RCOMP 1 2 +1.05V_RUN YH2
XCLK_RCOMP RH100 90.9_0402_1%~D 25MHZ_12PF_X5H025000DC1H-H
V40

2
CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P 2 1

10P_0402_50V8J~D

10P_0402_50V8J~D
T13 PCIECLKRQ6# / GPIO45
2 2

CH18

CH19
2 1 PCIE_EMB# V38 K43 PCI_TCM 4@ RH311 2 1 22_0402_5%~D
<29> CLK_PCIE_EMB# CLK_PCI_TPM_CHA <35>
FLEX CLOCKS

@ RH3102 PCIE_EMB CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64

eModule Bay---> <29> CLK_PCIE_EMB 1 0_0402_5%~D V37 CLKOUT_PCIE7P
+3.3V_ALW_PCH @ RH3122 1 0_0402_5%~D F47 SIO_14M RH313 2 1 22_0402_5%~D
CLKOUTFLEX1 / GPIO65 CLK_SIO_14M <40> 1 1
RH104 10K_0402_5%~D EMBCLK_REQ# K12
<29> EMBCLK_REQ# PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47 PCI_TPM RH314 2 1 22_0402_5%~D CLK_PCI_TPM <34>
A CLK_BCLK_ITP# A
<7> CLK_CPU_ITP# 2 1 AK14 CLKOUT_ITPXDP_N
@ RH2802 1 0_0402_5%~D CLK_BCLK_ITP AK13 K49 JETWAY_14M @RH315
@ RH315 2 1 22_0402_5%~D
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 JETWAY_CLK14M <35>
@ RH281 0_0402_5%~D

CougarPoint_Rev_1p0
PCIEREQpowerrail: DELL CONFIDENTIAL/PROPRIETARY
suspend:034567 Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
core:12 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 15 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW_PCH 1 2 PCH_CRT_BLU +3.3V_RUN

RH131 150_0402_1%~D
1 2 PCH_CRT_GRN

2.2K_0402_5%~D

2.2K_0402_5%~D
RH132 150_0402_1%~D

1
1 2 PCH_CRT_RED

RH316

RH317
1 2 SUS_STAT#/LPCPD# RH133 150_0402_1%~D
@ RH318 10K_0402_5%~D 1 2 ENVDD_PCH
RH134 100K_0402_5%~D
1 2 ME_SUS_PWR_ACK PCH_DPWROK 1 2 PCH_RSMRST#_R

2
RH144 10K_0402_5%~D @ RH113 0_0402_5%~D

1 2 PCH_PCIE_WAKE# G_CLK_DDC2 1 6 PCH_CRT_DDC_CLK

D PCH_CRT_DDC_CLK <25> D
RH142 10K_0402_5%~D DSWODVREN - On Die DSW VR Enable
RESET_OUT# 1 2 SYS_PWROK QH6A
1 2 SIO_SLP_LAN# @RH321
@ RH321 0_0402_5%~D Enabled (DEFAULT) DMN66D0LDW-7_SOT363-6~D

2
@ RH319 10K_0402_5%~D +3.3V_RUN
HIGH: RH127 STUFFED,

5
1 2 PCH_RI# RH129 UNSTUFFED QH6B
RH140 10K_0402_5%~D DMN66D0LDW-7_SOT363-6~D
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R G_DAT_DDC2 4 3 PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT <25>
@ RH323 0_0402_5%~D Disabled
+3.3V_RUN
LOW: RH129 STUFFED,
RH127 UNSTUFFED
1 2 CLKRUN# PCH_RSMRST#_Q 1 2
RH137 8.2K_0402_5%~D RH322 10K_0402_5%~D

UH4C Intel request DDPB can not support eDP

UH4D
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <24> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <24,40> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <24> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
C <6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <23> LDDC_CLK_PCH L_DDC_CLK C
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <23> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39
DMI
FDI
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 Minimum speacing of 20mils for LVD_IBG AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD
AW16 FDI_INT LCD_ACLK-_PCH AK39

LVDS
+1.05V_RUN FDI_INT FDI_INT <6> <23> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42
<23> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P
LCD_A0-_PCH AN48 AV45
<23> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N
DMI_COMP_R FDI_FSYNC1 LCD_A1-_PCH

Digital Display Interface

1 2 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 <6> <23> LCD_A1-_PCH AM47 LVDSA_DATA#1 DDPB_1P AV46
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48
<23> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AJ48 AU47
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6> LVDSA_DATA#3 DDPB_2P
RH112 750_0402_1%~D AV47
FDI_LSYNC1 LCD_A0+_PCH DDPB_3N
FDI_LSYNC1 BB10 FDI_LSYNC1 <6> <23> LCD_A0+_PCH AN47 LVDSA_DATA0 DDPB_3P AV49
LCD_A1+_PCH AM49
+RTC_CELL <23> LCD_A1+_PCH LVDSA_DATA1
LCD_A2+_PCH AK49
<23> LCD_A2+_PCH LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
A18 DSWODVREN RH1271 2 330K_0402_1%~D P42
DSWVRMEN DDPC_CTRLDATA
System Power Management

@ RH1291 2 330K_0402_1%~D LCD_BCLK-_PCH AF40

<23> LCD_BCLK-_PCH LVDSB_CLK#
1 2 SUSACK#_R C12 E22 PCH_DPWROK LCD_BCLK+_PCH AF39 AP47
<40> SUSACK# SUSACK# DPWROK PCH_DPWROK <40> <23> LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN
@ RH114 0_0402_5%~D AP49
LCD_B0-_PCH DDPC_AUXP
<23> LCD_B0-_PCH AH45 LVDSB_DATA#0 DDPC_HPD AT38
XDP_DBRESET# K3 B9 PCH_PCIE_WAKE# LCD_B1-_PCH AH47
<7,14> XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# <40> <23> LCD_B1-_PCH LVDSB_DATA#1
LCD_B2-_PCH AF49 AY47
B <23> LCD_B2-_PCH LVDSB_DATA#2 DDPC_0N B
AF45 LVDSB_DATA#3 DDPC_0P AY49
1 2 SYS_PWROK_R P12 N3 CLKRUN# AY43
<7,40> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 CLKRUN# <35,40,41> DDPC_1N
@RH116
@ RH116 0_0402_5%~D LCD_B0+_PCH AH43 AY45
<23> LCD_B0+_PCH LVDSB_DATA0 DDPC_1P
LCD_B1+_PCH AH49 BA47
<23> LCD_B1+_PCH LVDSB_DATA1 DDPC_2N
1 2 PCH_PWROK L22 G8 SUS_STAT#/LPCPD# T56 PAD~D LCD_B2+_PCH AF47 BA48
<41> RESET_OUT# PWROK SUS_STAT# / GPIO61 <23> LCD_B2+_PCH LVDSB_DATA2 DDPC_2P
@RH117
@ RH117 0_0402_5%~D AF43 BB47
LVDSB_DATA3 DDPC_3N
DDPC_3P BB49
1 2 PM_APWROK_R L10 N14 SUSCLK T57 PAD~D
<41> PM_APWROK APWROK SUSCLK / GPIO62
@RH118
@ RH118 0_0402_5%~D
T58 PAD~D PCH_CRT_BLU N48 M43
<25> PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
1 2 PM_DRAM_PWRGD_R B13 D10 SIO_SLP_S5# PCH_CRT_GRN P49 M36
<7> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# <41> <25> PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA
@RH320
@ RH320 0_0402_5%~D PCH_CRT_RED T49
<25> PCH_CRT_RED CRT_RED
T59 PAD~D
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45

CRT
<14,41> PCH_RSMRST#_Q RSMRST# SLP_S4# SIO_SLP_S4# <40> DDPD_AUXN
@RH120
@ RH120 0_0402_5%~D G_CLK_DDC2 T39 AT43
T60 PAD~D G_DAT_DDC2 CRT_DDC_CLK DDPD_AUXP
M40 CRT_DDC_DATA DDPD_HPD BH41
1 2 ME_SUS_PWR_ACK_R K16 F4 SIO_SLP_S3#
<41> ME_SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# <40>
@RH121
@ RH121 0_0402_5%~D RH123 20_0402_1%~D BB43
DDPD_0N
<7,14> SIO_PWRBTN#_R
T61 PAD~D
<25> PCH_CRT_HSYNC 1 2 HSYNC M47 CRT_HSYNC DDPD_0P BB45
1 2 SIO_PWRBTN#_R E20 G10 SIO_SLP_A# 1 2 VSYNC M49 BF44
<41> SIO_PWRBTN# PWRBTN# SLP_A# SIO_SLP_A# <40,57> <25> PCH_CRT_VSYNC CRT_VSYNC DDPD_1N
@ RH122 0_0402_5%~D RH124 20_0402_1%~D BE44
T62 PAD~D DDPD_1P
DDPD_2N BF42
AC_PRESENT H20 G16 SIO_SLP_SUS# CRT_IREF T43 BE42
<41> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# SIO_SLP_SUS# <40> DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
T63 PAD~D BG42
DDPD_3P

1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <7>
RH139 8.2K_0402_5%~D CougarPoint_Rev_1p0
RH126
PCH_RI# A10 K14 SIO_SLP_LAN# 1K_0402_0.5%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <32,40>

2
CougarPoint_Rev_1p0
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 16 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN

1 2 PCI_PIRQA#
RH324 8.2K_0402_5%~D
UH4E
D PCI_PIRQB# D
1 2 RSVD1 AY7
RH325 8.2K_0402_5%~D AV7
PAD~D T72 @ RSVD2
BG26 TP1 RSVD3 AU3
1 2 PCI_PIRQC# PAD~D T64 @ BJ26 BG4
RH326 8.2K_0402_5%~D PAD~D T73 @ TP2 RSVD4
BH25 TP3
PAD~D T65 @ BJ16 AT10
PCI_PIRQD# PAD~D T74 @ TP4 RSVD5
1 2 BG16 TP5 RSVD6 BC8
RH329 8.2K_0402_5%~D PAD~D T66 @ AH38
PAD~D T67 @ TP6
AH37 TP7 RSVD7 AU2
1 2 PCI_REQ1# PAD~D T75 @ AK43 AT4
RH327 10K_0402_5%~D PAD~D T76 @ TP8 RSVD8
AK45 TP9 RSVD9 AT3
PAD~D T77 @ C18 AT1
LVDS_CBL_DET# PAD~D T68 @ TP10 RSVD10
1 2 N30 TP11 RSVD11 AY3
RH330 10K_0402_5%~D PAD~D T69 @ H3 AT5
PAD~D T78 @ TP12 RSVD12
AH12 TP13 RSVD13 AV3
1 2 CAM_MIC_CBL_DET# PAD~D T79 @ AM4 AV1
RH331 10K_0402_5%~D PAD~D T80 @ TP14 RSVD14
AM5 TP15 RSVD15 BB1
PAD~D T70 @ Y13 BA3
BT_DET# PAD~D T81 @ TP16 RSVD16
1 2 K24 TP17 RSVD17 BB5
RH328 10K_0402_5%~D PAD~D T71 @ L24 BB3
PAD~D T82 @ TP18 RSVD18
AB46 TP19 RSVD19 BB7
1 2 PCH_GPIO3 PAD~D T83 @ AB45 BE8

RSVD
@RH332
@ RH332 10K_0402_5%~D TP20 RSVD20
RSVD21 BD4
RSVD22 BF6

PAD~D T84 @ B21 AV5

PAD~D T85 @ TP21 RSVD23
M20 TP22 RSVD24 AV10
PAD~D T86 @ AY16
PAD~D T87 @ TP23
BG46 TP24 RSVD25 AT8

RSVD26 AY5
RSVD27 BA2
C PAD~D T88 @ C
BE28 TP25
PAD~D T89 @ BC30 AT12
PAD~D T90 @ TP26 RSVD28
BE32 TP27 RSVD29 BF3
PAD~D T91 @ BJ32
PAD~D T92 @ TP28
BC28 TP29
PAD~D T93 @ BE30
PAD~D T94 @ TP30
BF32 TP31
PAD~D T95 @ BG32 C24 USBP0-
TP32 USBP0N USBP0- <45>
PCI_GNT3# PAD~D T96 @ AV26 TP33 USBP0P A24 USBP0+
USBP0+ <45> ----->Right Side
PAD~D T97 @ BB26 C25 USBP1-
TP34 USBP1N USBP1- <45>
PAD~D T98 @ AU28 TP35 USBP1P B25 USBP1+
USBP1+ <45> ----->Right Side
1

PAD~D T99 @ AY30 C26 USBP2-

TP36 USBP2N USBP2- <46>
@ RH333 PAD~D T100 @ AU26 TP37 USBP2P A26 USBP2+
USBP2+ <46> ----->left Side
1K_0402_5%~D PAD~D T101 @ AY26 K28 USBP3-
TP38 USBP3N USBP3- <46>
PAD~D T102 @ AV28 TP39 USBP3P H28 USBP3+
USBP3+ <46> ----->Left Side
PAD~D T103 @ AW30 E28 USBP4-
USBP4- <37>
2

TP40 USBP4N
USBP4P D28 USBP4+
USBP4+ <37> ----->WLAN/WIMAX
C28 USBP5-
USBP5N USBP5- <37>
USBP5P A28 USBP5+
USBP5+ <37> ----->WWAN/UWB
C29 USBP6-
USBP6N USBP6- <37>
USBP6P B29 USBP6+ USBP6+ <37> ----->Flash
PCI_PIRQA# K40 N28 USBP7-
PIRQA# USBP7N USBP7- <34>
PCI_PIRQB# K38 M28 USBP7+ ----->USH

PCI
PIRQB# USBP7P USBP7+ <34>
A16 swap override Strap/Top-Block PCI_PIRQC# H38 L30 USBP8-
PIRQC# USBP8N USBP8- <39>
PCI_PIRQD# G38 PIRQD# USBP8P K30 USBP8+
USBP8+ <39> ----->DOCK
Swap Override jumper G30 USBP9-
USBP9N USBP9- <39>
PCI_REQ1# C46 E30 USBP9+ ----->DOCK

USB
REQ1# / GPIO50 USBP9P USBP9+ <39>
C44 C30 USBP10-
<37> PCIE_MCARD2_DET#_R REQ2# / GPIO52 USBP10N USBP10- <38>
Low = A16 swap <42> BT_DET#
BT_DET# E40 REQ3# / GPIO54 USBP10P A30 USBP10+
USBP10+ <38> ----->Express Card +3.3V_ALW_PCH
PCI_GNT#3 L32 USBP11-
USBP11N USBP11- <42>
High = Default BBS_BIT1 D47 GNT1# / GPIO51 USBP11P K32 USBP11+ USBP11+ <42> ----->Blue Tooth RPH1
E42 G32 USBP12- USB_OC0# 4 5
GNT2# / GPIO53 USBP12N USBP12- <24>
B PCI_GNT3# F46 GNT3# / GPIO55 USBP12P E32 USBP12+
USBP12+ <24> ----->Camera USB_OC1# 3 6 B
C32 USBP13- USB_OC3# 2 7
USBP13N USBP13- <24>
USBP13P A32 USBP13+
USBP13+ <24> ----->LCD Touch USB_OC4# 1 8
LVDS_CBL_DET# G42
<24> LVDS_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 Within 500 mils 10K_1206_8P4R_5%~D
CAM_MIC_CBL_DET# PIRQF# / GPIO3 USBRBIAS RPH2
<24> CAM_MIC_CBL_DET# C42 PIRQG# / GPIO4 USBRBIAS# C33 1 2
1 2 FFS_PCH_INT D44 RH151 USB_OC5# 4 5
<28> HDD_FALL_INT PIRQH# / GPIO5
1 2 @RH334
@ RH334 0_0402_5%~D 22.6_0402_1%~D USB_OC6# 3 6
<34> PLTRST_USH#
@ RH3351 2 0_0402_5%~D B33 2 7
<36> PLTRST_MMI# USBRBIAS
@ RH3361 2 0_0402_5%~D PAD~D T104 @ K10 USB_OC2# 1 8
<7> PLTRST_XDP# PME#
@ RH3371 2 0_0402_5%~D
<32> PLTRST_LAN#
@ RH3381 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R 1 2 10K_1206_8P4R_5%~D
<47> PLTRST_GPU# PLTRST# OC0# / GPIO59 USB_OC0# <45>
@ RH3431 2 0_0402_5%~D K20 USB_OC1#_R @RH339
@ RH3391 2 0_0402_5%~D
<29> PLTRST_EMB# OC1# / GPIO40 USB_OC1# <46>
@ RH340 0_0402_5%~D B17 USB_OC2# @RH341
@ RH341 0_0402_5%~D SIO_EXT_SMI# 2 1
OC2# / GPIO41 USB_OC2# <14>
2 1 PCI_5048 H49 C16 USB_OC3# RH51 10K_0402_5%~D
<40> CLK_PCI_5048 CLKOUT_PCI0 OC3# / GPIO42 USB_OC3# <14>
RH160 2 1 22_0402_5%~D PCI_MEC H43 L16 USB_OC4#
<41> CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <14>
RH102 1 2 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5#
<39> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC5# <14>
RH103 33_0402_5%~D K42 D14 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC6# <14>
2 1 PCI_LOOPBACKOUT H40 C14 SIO_EXT_SMI#
<15> CLK_PCI_LOOPBACK CLKOUT_PCI4 OC7# / GPIO14 SIO_EXT_SMI# <14,41>
RH105 22_0402_5%~D
USB_OC0#_R <14>
CougarPoint_Rev_1p0
USB_OC1#_R <14>

+3.3V_RUN CH102
0.1U_0402_16V4Z~D
1 2

Boot BIOS Strap

5

A UH3 SATA_SLPD A
PCH_PLTRST# 1 BBS_BIT1 Boot BIOS Location
P

<7,14> PCH_PLTRST# B PCH_PLTRST#_EC

(BBS_BIT0) BBS_BIT1
O 4 PCH_PLTRST#_EC <14,35,37,38,40,41>
2 A
G

0 0 LPC
DELL CONFIDENTIAL/PROPRIETARY
1
TC7SH08FU_SSOP5~D
3

@ RH342
1K_0402_5%~D
0 1 Reserved (NAND) Compal Electronics, Inc.
Title
2

1 0 PCI SCHEMATICS,MB A6561

Size Document Number Rev
1 1 SPI B
* 401931
Date: Thursday, January 13, 2011 Sheet 17 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW_PCH
2
RH53
4.7K_0402_5%~D
+3.3V_RUN
1

SLP_ME_CSW_DEV#
CONTACTLESS_DET# 1 2
2

RH256 10K_0402_1%~D
RH353
D D
1K_0402_5%~D
@ UH4F
<14> SIO_EXT_SCI#_R
1

SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET#

<41> SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68 CONTACTLESS_DET# <34>
@RH259
@ RH259 0_0402_5%~D
PCH_GPIO1 A42 B41 DGPU_PWROK
TACH1 / GPIO1 TACH5 / GPIO69 DGPU_PWROK <40,64>
IO_LOOP# H36 C41
<46> IO_LOOP# TACH2 / GPIO6 TACH6 / GPIO70 PCIE_MCARD3_DET# <37>
IO1_LOOP# E38 A40
<46> IO1_LOOP# TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# <37>
Note: PCH has internal pull up 20k ohm on
<14,40> SIO_EXT_WAKE# C10 GPIO8
E3_PAID_TS_DET# (GPIO27)
PM_LANPHY_ENABLE C4
<32> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15 G2 P4 SIO_A20GATE
<14> PCH_GPIO15 GPIO15 A20GATE SIO_A20GATE <41>
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
PECI AU16
EN_ESATA_RPTR# U2
<14> EN_ESATA_RPTR# SATA4GP / GPIO16
ENABLED - HIGH DEFAULT P5 SIO_RCIN#
RCIN# SIO_RCIN# <41>
DISABLED - LOW +3.3V_RUN

GPIO
GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT

CPU/MISC
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 SIO_A20GATE 2 1
<46> MEDIA_DET# SCLOCK / GPIO22 THRMTRIP# RH262 56_0402_5%~D RH158 10K_0402_5%~D
E8 T14 INIT3_3V# PAD~D T106 1 SIO_RCIN# 2 1
<37> PCIE_MCARD1_DET# GPIO24 / MEM_LED INIT3_3V# @ RH203 10K_0402_5%~D
E3_PAID_TS_DET# E16 AY1 DF_TVS CH97
+3.3V_ALW_PCH <24> E3_PAID_TS_DET# GPIO27 DF_TVS 0.1U_0402_16V4Z~D
SLP_ME_CSW_DEV# 2 SIO_EXT_SCI#
<14,40> SLP_ME_CSW_DEV# P8 GPIO28 1 2
AH8 RH263 10K_0402_5%~D
SIO_EXT_WAKE# DGPU_HOLD_RST# TS_VSS1 PCH_GPIO1
2 1 <47> DGPU_HOLD_RST# K1 STP_PCI# / GPIO34 1 2
C RH177 10K_0402_5%~D RH164 10K_0402_5%~D C
TS_VSS2 AK11
1 2 PCH_GPIO15 USB_MCARD1_DET# K4
<14,37> USB_MCARD1_DET# GPIO35
RH354 1K_0402_5%~D AH10
GPIO36 TS_VSS3
<14> GPIO36 V8 SATA2GP / GPIO36
TS_VSS4 AK10
GPIO37 M5
<14> GPIO37 SATA3GP / GPIO37
TPM_ID0 N2 P37 NC_1 PAD~D T108 @
SLOAD / GPIO38 NC_1
TPM_ID1 M3 SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2 VSS_NCTF_15
<28> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
<14,40> TEMP_ALERT# SATA5GP / GPIO49 VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17
<42> KB_DET# GPIO57 VSS_NCTF_17
BH47 VSS_NCTF_18
VSS_NCTF_18
VSS_NCTF_1 A4 BJ4 VSS_NCTF_19
VSS_NCTF_1 VSS_NCTF_19
VSS_NCTF_2 A44 BJ44 VSS_NCTF_20
VSS_NCTF_2 VSS_NCTF_20
VSS_NCTF_3 A45 BJ45 VSS_NCTF_21
VSS_NCTF_3 VSS_NCTF_21

NCTF
VSS_NCTF_4 A46 BJ46 VSS_NCTF_22
VSS_NCTF_4 VSS_NCTF_22
VSS_NCTF_5 A5 BJ5 VSS_NCTF_23
VSS_NCTF_5 VSS_NCTF_23
GPIO17 1 2 VSS_NCTF_6 A6 BJ6 VSS_NCTF_24
@ RH273 1K_0402_5%~D VSS_NCTF_6 VSS_NCTF_24
VSS_NCTF_7 B3 C2 VSS_NCTF_25
B VSS_NCTF_7 VSS_NCTF_25 B
VSS_NCTF_8 B47 C48 VSS_NCTF_26
VSS_NCTF_8 VSS_NCTF_26
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27 PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_9 VSS_NCTF_27
Trace wide 10mil & length 30mil VSS_NCTF_10 VSS_NCTF_28
Layout note: ( TO CPU and NVRAM CONNECTOR)
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
All NCTF pins should have thick Trace wide 10mil & length 30mil
VSS_NCTF_11 VSS_NCTF_29
traces at 45°from the pad.
BE1 VSS_NCTF_11 VSS_NCTF_29 E1 All NCTF pins should have thick +VCCDFTERM
VSS_NCTF_12 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 VSS_NCTF_30 traces at 45°from the pad.
RH149 need to close to CPU

1
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
VSS_NCTF_13 VSS_NCTF_31 RH149
VSS_NCTF_14 BF49 F49 VSS_NCTF_32 2.2K_0402_5%~D
+3.3V_ALW_PCH VSS_NCTF_14 VSS_NCTF_32

2
2 1 KB_DET# CougarPoint_Rev_1p0
RH170 10K_0402_5%~D DF_TVS_R 1 2 DF_TVS
RH150 0_0402_5%~D

+3.3V_RUN

2 1 GPIO36
@RH171
@ RH171 10K_0402_5%~D
2 1 GPIO37 +3.3V_RUN +3.3V_RUN DMI & FDI Termination Voltage
@RH173
@ RH173 1K_0402_1%~D
2 1 EN_ESATA_RPTR#
RH265 10K_0402_5%~D Set to Vss when LOW
2

2 1 TEMP_ALERT# DF_TVS
RH266 10K_0402_5%~D 1@ RH267 3@ RH268 Set to Vcc when HIGH
2 1 MEDIA_DET# 10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1
A RH179 10K_0402_5%~D A

China TPM 0 0
1

1 2 GPIO17 TPM_ID0 TPM_ID1 No TPM, No China TPM 0 1

RH269 8.2K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2

2@ RH270 4@ RH271
USH2.0 1 1
IO_LOOP# 10K_0402_5%~D 2.2K_0402_5%~D
1
RH163
2
10K_0402_5%~D Compal Electronics, Inc.
1 2 IO1_LOOP# Title
1

RH272 10K_0402_5%~D
SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 18 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN

LH1
PCH Power Rail Table
+1.05V_RUN UH4G POWER +VCCADAC 2 1 S0 Iccmax
BLM18PG181SN1_0603~D Voltage Rail Voltage Current (A)

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D

10U_0805_4VAM~D
AA23 VCCCORE[1] VCCADAC U48 1 1 1
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001

10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH34

CH35

CH36
CRT
1 1 1 1 AD21 VCCCORE[3]
AD23 VCCCORE[4] VSSADAC U47
2 2 2

CH30

CH32

CH33

CH31

VCC CORE
AF21 VCCCORE[5]
V5REF 5 0.001
AF23 +3.3V_RUN
D 2 2 2 2 VCCCORE[6] D
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V5REF_Sus 5 0.001
AG24 VCCCORE[9] VCCALVDS AK36
AG26 VCCCORE[10]
AG27 AK37 +1.8V_RUN Vcc3_3 3.3 0.266
VCCCORE[11] VSSALVDS LH8
AG29 VCCCORE[12]
AJ23 HK1608R10J-T_0603~D

LVDS
VCCCORE[13] +1.8V_RUN_LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 2 1 VccADAC3 3.3 0.001

22U_0805_6.3VAM~D
AJ27 1 1 1 0.1uH inductor, 200mA
VCCCORE[15]

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

CH105
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38

CH103

CH104
AJ31 CPN: SHI0110BJ0L VccADPLLA 1.05 0.08
+1.05V_RUN VCCCORE[17]
VCCTX_LVDS[3] AP36
2 2 2

VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08

AN19 VCCIO[28]
+1.05V_RUN
VccCore 1.05 1.3
1 2 +VCCAPLLEXP BJ22
@ RH247 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D

10U_0805_4VAM~D
1 V33 VccDMI 1.05 0.042

HVCMOS
VCC3_3[6] +3.3V_RUN
AN16 VCCIO[15]

CH40
1
AN17 VCCIO[16]
VccIO 1.05 2.925
2 @ CH43
VCC3_3[7] V34
0.1U_0402_10V7K~D
2 VccASW 1.05 1.01
AN21 VCCIO[17]
AN26 +1.05V_+1.5V_1.8V_RUN
VCCIO[18]
VccSPI 3.3 0.020
AN27 VCCIO[19] VCCVRM[3] AT16
+1.05V_RUN
AP21 VCCIO[20]
VccDSW3_3 3.3 0.003
C C
AP23 VCCIO[21] VCCDMI[1] AT20 +1.05V_RUN_VTT
VccpDFTERM 1.8 0.19

DMI
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 1 AP24 1 2 CH49

VCCIO
VCCIO[22] 1U_0402_6.3V6K~D
CH44

CH45

CH46

CH47

CH48

AP26 AB36 +1.05V_RUN_VCCCLKDMI 2 1 +1.05V_RUN VccRTC 3.3 2 (mA)

VCCIO[23] VCCCLKDMI LH9 HK1608R10J-T_0603~D
2 2 2 2 2 1 1
AT24 @
VCCIO[24] CH50 CH106 VccSus3_3 3.3 0.119
1U_0402_6.3V6K~D 10U_0805_4VAM~D
2 2
AN33 VCCIO[25]
VccSusHDA 3.3 0.01
AN34 VCCIO[26] VCCDFTERM[1] AG16
+3.3V_RUN +VCCDFTERM
VccVRM 1.8 / 1.5 0.16
BH29 AG17 1 2 +3.3V_RUN

DFT / SPI
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D
0.1U_0402_10V7K~D

1 VccClkDMI 1.05 0.02

+1.05V_+1.5V_1.8V_RUN AJ16 1 @PJP66
@ PJP66
VCCDFTERM[3]
CH51

1 2 +1.8V_RUN
AP16 CH52 VccSSC 1.05 0.095
2 VCCVRM[2] 0.1U_0402_10V7K~D PAD-OPEN1x1m
VCCDFTERM[4] AJ17
2
+VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL

+1.05V_RUN AP17 VCCIO[27]

VccALVDS 3.3 0.001
FDI

VCCSPI V1 +3.3V_M

+1.05V_RUN_VTT AU20 VCCDMI[2] 1 VccTX_LVDS 1.8 0.06

CH54
B CougarPoint_Rev_1p0 1U_0402_6.3V6K~D VccAPLLEXP 1.05 0.05 B
2

+1.05V_RUN
+1.05V_RUN

1 2 +VCCAPLL_FDI
@ RH195 0.022_0805_1%

+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
1 1
+ @ CH41 + @ CH42
2 1 330U_D2_2VM_R6M~D 330U_D2_2VM_R6M~D
RH197 0_0603_5%~D
+1.8V_RUN 2 2

2 1
@ RH198 0_0603_5%~D
+1.05V_RUN

2 1
@ RH199 0_0603_5%~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 19 of 77
5 4 3 2 1
 5 4 3 2 1

Note: C225 - STUFFED ONLY FOR CPT INTERPOSER;

+5V_ALW +5V_ALW_PCH
UNSTUFF FOR CPT

+1.05V_RUN PJP68 PAD-OPEN1x1m

1 2
1 2 +VCCACLK
+3.3V_ALW_PCH @ RH200 0.022_0805_1%
+3.3V_ALW2
UH4J POWER

S
1 2 1 3

20K_0402_5%~D
0.1U_0402_10V7K~D
@ RH201 0_0402_5%~D 1 AD49 N26 +1.05V_RUN
VCCACLK VCCIO[29] @ QH4
1 2

1
@RH253
@ RH253 0_0402_5%~D CH55 P26 1 SSM3K7002FU_SC70-3~D 1

G
2
0.1U_0402_10V7K~D VCCIO[30]

CH98

RH278
+VCCDSW3_3 T16
D 2 VCCDSW3_3 CH56 D
VCCIO[31] P28
1U_0402_6.3V6K~D
2 <43> ALW_ENABLE 2 @
+PCH_VCCDSW V12 T27 @

2
+1.05V_RUN @ LH3 DCPSUSBYP VCCIO[32]
1
10UH_LBR2012T100M_20%~D T29
VCCIO[33]

@
1 2 CH57 +3.3V_RUN_VCC_CLKF33 T38
0.1U_0402_10V7K~D VCC3_3[5]
2 +3.3V_ALW_PCH

10U_0805_6.3V6M~D

0.1U_0402_10V7K~D
1 VCCSUS3_3[7] T23
+1.05V_RUN

@ CH58
+VCCAPLL_CPY_PCH BH23 1
VCCAPLLDMI2
VCCSUS3_3[8] T24 +3.3V_ALW_PCH +5V_ALW_PCH +3.3V_ALW_PCH

0.1U_0402_10V7K~D
CH59
AL29 VCCIO[14]
2
V23 1

USB
VCCSUS3_3[9] 2

2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] DH2
1 RH208
2 10_0402_5%~D
VCCSUS3_3[6] P24 RB751S40T1_SOD523-2~D

@
CH61
1U_0402_6.3V6K~D AA19

1
2 VCCASW[1] +PCH_V5REF_SUS
T26 +1.05V_RUN

www.qdzbwx.com
VCCIO[34]
AA21 VCCASW[2] 1

AA24 M26 +PCH_V5REF_SUS CH63

VCCASW[3] V5REF_SUS

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
1 1 +3.3V_ALW_PCH 0.1U_0402_10V7K~D
2

0.1U_0402_10V7K~D
Clock and Miscellaneous
AA26 VCCASW[4]

CH64

CH65
AN23 +VCCA_USBSUS 1
DCPSUS[4] CRB 0.7 RH208,RH213 trace width 20mil.
AA27 VCCASW[5]
2 2

CH66
VCCSUS3_3[1] AN24
AA29 VCCASW[6] 2
+1.05V_M +5V_RUN +3.3V_RUN
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] V5REF

2
C C
1 1U_0402_6.3V6K~D 1 1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
AC27 RH213 DH3
CH67 VCCASW[9]

CH68

CH69
N20 +3.3V_ALW_PCH 10_0402_5%~D RB751S40T1_SOD523-2~D

PCI/GPIO/LPC
VCCSUS3_3[2]
AC29 VCCASW[10] 1
2 2 2
N22

1
VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
AC31 VCCASW[11] 1U_0603_10V6K~D +3.3V_RUN
VCCSUS3_3[4] P20
2
AD29 VCCASW[12] 1
VCCSUS3_3[5] P22
+3.3V_RUN CH71
AD31 VCCASW[13] 1
1U_0603_10V6K~D
CH72 2
1 2 W21 VCCASW[14] VCC3_3[1] AA16
@ RH215 0.022_0805_1% 0.1U_0402_10V7K~D
LH4 2 +3.3V_RUN
W23 VCCASW[15] VCC3_3[8] W16
10UH_LBR2012T100M_20%~D
1 2 +3.3V_RUN_VCC_CLKF33 W24 T34
VCCASW[16] VCC3_3[4]
10U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1 1 1
@ CH73

W26 +VCCA_USBSUS
VCCASW[17]
CH74

CH75
+3.3V_RUN 0.1U_0402_10V7K~D
W29 VCCASW[18] 1
2 2 2
W31 AJ2 @CH62
@CH62
VCCASW[19] VCC3_3[2] 1U_0402_6.3V6K~D
1 2
W33 VCCASW[20]
AF13 CH76 +1.05V_RUN
VCCIO[5] 0.1U_0402_10V7K~D
2 1
+VCCRTCEXT N16 DCPRTC CH77
1 VCCIO[12] AH13
+1.05V_+1.5V_1.8V_RUN 1U_0402_6.3V6K~D
CH78 2
Y49 VCCVRM[4] VCCIO[13] AH14
0.1U_0402_10V7K~D
2
B +1.05V_RUN AF14 LH5 @ B
+1.05V_RUN_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D
BD47

SATA
VCCADPLLA +VCCSATAPLL
VCCAPLLSATA AK1 1 2 +1.05V_RUN
1 +1.05V_RUN_VCCA_B_DPL BF47 +1.05V_+1.5V_1.8V_RUN 1
VCCADPLLB

@
CH79 AF11 CH80
1U_0402_6.3V6K~D VCCVRM[1] 10U_0805_6.3V6M~D
AF17 VCCIO[7]
2 2
AF33 VCCDIFFCLKN[1]
AF34 VCCDIFFCLKN[2] VCCIO[2] AC16 +1.05V_RUN
1 2 CH81 AG34 VCCDIFFCLKN[3]
1U_0402_6.3V6K~D AC17 1
VCCIO[3]
1 AG33 AD17 CH82
VCCSSC VCCIO[4] 1U_0402_6.3V6K~D
+1.05V_M CH96 2
1U_0402_6.3V6K~D +VCCSST V16 +1.05V_M
2 DCPSST
1 2 +1.05V_M_VCCSUS
@RH248
@ RH248 0.022_0805_1% 1 +1.05V_M_VCCSUS
1 T17 DCPSUS[1] VCCASW[22] T21
CH84 V19
MISC

0.1U_0402_10V7K~D CH83 @ DCPSUS[2]

+1.05V_RUN_VTT 2 1U_0402_6.3V6K~D
VCCASW[23] V21
2
CPU
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

BJ8 V_PROC_IO
1 1 1 VCCASW[21] T19
+RTC_CELL
CH86

CH87

CH85
4.7U_0603_6.3V6K~D
2 2 2
RTC

A22 P32
HDA

VCCRTC VCCSUSHDA +3.3V_ALW_PCH

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 1 1 1
LH6 CougarPoint_Rev_1p0
CH88

CH89

A 10UH_LBR2012T100M_20%~D CH90 CH91 A

1 2 +1.05V_RUN_VCCA_A_DPL 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
+1.05V_RUN 2 2 2 2

1 2 +1.05V_RUN_VCCA_B_DPL
DELL CONFIDENTIAL/PROPRIETARY
220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

LH7
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10UH_LBR2012T100M_20%~D 1 1
1 1 Compal Electronics, Inc.
CH94

CH92

CH95

CH93

+ +
Title
+1.05V_RUN_VCCA_A_DPL 1 2 +1.05V_RUN_VCCA_B_DPL
2 2 2 2 @ RH279 0_0805_5%~D SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 20 of 77
5 4 3 2 1
 5 4 3 2 1

UH4I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
D UH4H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
CougarPoint_Rev_1p0 G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

CougarPoint_Rev_1p0

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 21 of 77
5 4 3 2 1
 5 4 3 2 1

+FAN1_VOUT
DSConly
JFAN1 CONN@ <48> VGA_THERMDP VGA_THERMDP
FAN1_DET# 1 1
2 2 1

RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 5
3 G1

22U_0805_6.3VAM~D
4 6 C1104
4 G2

1
PlaceunderCPU 1 470P_0402_50V7K~D
2

C219
MOLEX_53398-0471~D
PlaceC266closetotheQ12aspossible

D2
<48> VGA_THERMDN VGA_THERMDN

REM_DIODE1_P_4022 2

2
1
@ 2 C
D C266 2 +5V_RUN +3.3V_M D
100P_0402_50V8J~D B
E Q12

3
1 MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 BC_INT#_EMC4022 2 1
+3.3V_RUN R385 10K_0402_5%~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
FAN1_TACH_FB 2 1
1 1 R426 10K_0402_5%~D

10U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
FAN1_DET# 2 1

C276

C275
1 1 R402 10K_0402_5%~D
2 2

C305

C1171
U9
2 2
2 VDDH
+3.3V_M 3 VDDH THERMATRIP2#
6 VDDL THERMTRIP2# 17
1 2 VDD_PWRGD 13
R389 10K_0402_5%~D VDD_PWRGD THERMATRIP3#
THERMTRIP3# 18

DP3/DN3forSODIMMonQ14,placeQ14closetoSODIMMandC272closetoQ14 1 2 REM_DIODE1_N_4022 23
C270 2200P_0402_50V7K~D REM_DIODE1_P_4022 DN1/THERM
24 DP1/VREF_T SYS_SHDN# 19 THERM_STP# <54>
DP5/DN5forSkinonQ13,placeQ13closetoJMINI1forWWANandC277closeQ13. VGA_THERMDN POWER_SW#
1
@R390
@ R390
2
47K_0402_1%~D
+RTC_CELL
26 DN2/DP4 POWER_SW# 20
VGA_THERMDP 27
REM_DIODE3_P_4022 DP2/DN4
2 1 REM_DIODE3_P_4022 30 21 ACAV_IN ACAV_IN <41,61,63>
C271 2200P_0402_50V7K~D REM_DIODE3_N_4022 DP3/DN5 ACAVAIL_CLR BC_INT#_EMC4022
1 1 29 DN3/DP5 ATF_INT#/BC_IRQ# 9 BC_INT#_EMC4022 <41>
1

E
C Q13
B
@ C272 2 @C277
@ C277 2 MMBT3904WT1G_SC70-3~D
100P_0402_50V8J~D B 100P_0402_50V8J~D 2 1 VCP2 31
2 2 C <61> MAX8731_IINP VCP
E Q14 R387 4.7K_0402_5%~D 25
3

C MMBT3904WT1G_SC70-3~D REM_DIODE3_N_4022 VIN C

FAN_OUT 5 +FAN1_VOUT
VSET_4022 28 4
VSET FAN_OUT

SMCLK/BC_CLK 8 BC_CLK_EMC4022 <41>

FAN1_TACH_FB 10 7
TACH/GPIO1 SMDATA/BC_DATA BC_DAT_EMC4022 <41>
FAN1_DET# 11 GPIO2
2 1 PWM 15 +3.3V_M
+3.3V_M GPIO3/PWM/THERMTRIP_SIO
R1178 10K_0402_5%~D
+3.3V_M

1
R388
1

<41> PCH_PWRGD# 1 2 3V_PWROK# 12 3V_PWROK# 22_0402_5%~D

R395 R391 1K_0402_5%~D
8.2K_0402_5%~D

2
1 +VCC_4022
VDD ADDR_XEN 1
32 2 +VCC_4022
2

+1.05V_RUN_VTT ADDR_MODE/XEN

0.1U_0402_16V4Z~D

1U_0402_6.3V6K~D
THERMATRIP2# R393 4.7K_0402_5%~D 1 1
R398 14
TEST1
1

C273

C1179
2.2K_0402_5%~D C 1 22
TEST2
1 2 2 +RTC_CELL 16 RTC_PWR3V VSS 33
B C278 2 2

1
1U_0402_6.3V6K~D
Q15 E 0.1U_0402_16V4Z~D
3

PMST3904_SOT323-3~D 2 EMC4022-1-EZK-TR_QFN32_5X5~D R403

1
<7> H_THERMTRIP# 10K_0402_5%~D

C274

2
2

B B

+3.3V_RUN_GFX +3.3V_M
1
1

1
10K_0402_5%~D

2.2K_0402_5%~D

R405
R1111

R1112

8.2K_0402_5%~D
2
2

THERMATRIP3#
+RTC_CELL C281
1

C 1 VSET_4022 0.1U_0402_16V4Z~D
THERMB3 2 1 2
B C280

5
Q115 E 0.1U_0402_16V4Z~D 1 U10
3

PMST3904_SOT323-3~D 2 C282 R406 TC7SH08FU_SSOP5~D 1

P
B DOCK_PWR_SW# <41>
0.1U_0402_16V4Z~D 953_0402_1%~D POWER_SW# 4 O
<47> THERMTRIP_VGA#
A 2 POWER_SW_IN# <41>

G
2
2

3
Rest=953,Tp=88degree

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 22 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN
D +3.3V_RUN D
PJP54 PJP55

PORTA +3.3V_RUN_LVDS_A 1 2
PORTB
+3.3V_RUN_LVDS_B 1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 1 1 PAD-OPEN1x1m 1 1 1 PAD-OPEN1x1m

C1145

C1146

C1147

C1149

C1150

C1148
U84 U85
VCC 4 VCC 4
2 2 2 2 2 2
VCC 10 VCC 10
<48> LCD_A0+_GPU 48 0B1 VCC 18 <48> LCD_B0+_GPU 48 0B1 VCC 18
<48> LCD_A0-_GPU 47 1B1 VCC 27 <48> LCD_B0-_GPU 47 1B1 VCC 27
<48> LCD_A1+_GPU 43 2B1 VCC 38 <48> LCD_B1+_GPU 43 2B1 VCC 38
<48> LCD_A1-_GPU 42 3B1 VCC 50 <48> LCD_B1-_GPU 42 3B1 VCC 50
<48> LCD_A2+_GPU 37 4B1 VCC 56 <48> LCD_B2+_GPU 37 4B1 VCC 56
<48> LCD_A2-_GPU 36 5B1 <48> LCD_B2-_GPU 36 5B1
<48> LCD_ACLK+_GPU 32 6B1 A0 2 SW_LVDS_A0+ <24> <48> LCD_BCLK+_GPU 32 6B1 A0 2 SW_LVDS_B0+ <24>
<48> LCD_ACLK-_GPU 31 7B1 A1 3 SW_LVDS_A0- <24> <48> LCD_BCLK-_GPU 31 7B1 A1 3 SW_LVDS_B0- <24>
<47> LDDC_CLK_GPU 22 8B1 A2 7 SW_LVDS_A1+ <24> 22 8B1 A2 7 SW_LVDS_B1+ <24>
<47> LDDC_DATA_GPU 23 9B1 A3 8 SW_LVDS_A1- <24> 23 9B1 A3 8 SW_LVDS_B1- <24>
A4 11 SW_LVDS_A2+ <24> A4 11 SW_LVDS_B2+ <24>
A5 12 SW_LVDS_A2- <24> A5 12 SW_LVDS_B2- <24>
A6 14 SW_LVDS_ACLK+ <24> A6 14 SW_LVDS_BCLK+ <24>
A7 15 SW_LVDS_ACLK- <24> A7 15 SW_LVDS_BCLK- <24>
<16> LCD_A0+_PCH 46 0B2 A8 19 LDDC_CLK_SW <24> <16> LCD_B0+_PCH 46 0B2 A8 19
<16> LCD_A0-_PCH 45 1B2 A9 20 LDDC_DATA_SW <24> <16> LCD_B0-_PCH 45 1B2 A9 20
<16> LCD_A1+_PCH 41 2B2 <16> LCD_B1+_PCH 41 2B2
40 17 DGPU_SELECT# 40 17 DGPU_SELECT#
<16> LCD_A1-_PCH 3B2 SEL DGPU_SELECT# <25,40> <16> LCD_B1-_PCH 3B2 SEL
<16> LCD_A2+_PCH 35 4B2 <16> LCD_B2+_PCH 35 4B2
<16> LCD_A2-_PCH 34 5B2 GND 1 <16> LCD_B2-_PCH 34 5B2 GND 1
<16> LCD_ACLK+_PCH 30 6 <16> LCD_BCLK+_PCH 30 6

C
LVDSSW <16> LCD_ACLK-_PCH
<16> LDDC_CLK_PCH
29
25
6B2
7B2
8B2
GND
GND
GND
9
13
<16> LCD_BCLK-_PCH 29
25
6B2
7B2
8B2
GND
GND
GND
9
13
C
<16> LDDC_DATA_PCH 26 9B2 GND 16 26 9B2 GND 16
GND 21 GND 21
DGPU_SELECT# 54 24 DGPU_SELECT# 54 24
SEL2 GND SEL2 GND
GND 28 GND 28
GND 33 SEL Chanel Source GND 33 SEL Chanel Source
52 NC GND 39 52 NC GND 39
5 NC GND 44 0 COM=B1 GPU 5 NC GND 44 0 COM=B1 GPU
51 NC GND 49 51 NC GND 49
GND 53 1 COM=B2 PCH GND 53 1 COM=B2 PCH
57 Thermal_GND GND 55 57 Thermal_GND GND 55

PI3LVD400ZFEX_TQFN56_11X5~D PI3LVD400ZFEX_TQFN56_11X5~D

+3.3V_RUN_GFX

1 2 LDDC_CLK_GPU
R1122 2.2K_0402_5%~D
1 2 LDDC_DATA_GPU
B R1121 2.2K_0402_5%~D B

+3.3V_RUN

1 2 LDDC_CLK_PCH
R1124 2.2K_0402_5%~D
1 2 LDDC_DATA_PCH
R1123 2.2K_0402_5%~D

+3.3V_FP
CONN@
JFP1 @ L8
@L8
1 1 2 +3.3V_RUN U12 DLW21SN121SQ2L_4P~D
1 @ R1135 0_0402_5%~D FP_USB_D+
2 2 1 GND VCC 4 +3.3V_FP <34> FP_USBD+ 1 1 2 2
3 FP_USB_D- 1 2 +3.3V_ALW
3 FP_USB_D+ @ R1136 0_0402_5%~D
4 4
7 5 FP_RESET# <34> 1 FP_USB_D- 2 3 FP_USB_D+ 4 3 FP_USB_D-
G1 5 IO1 IO2 <34> FP_USBD- 4 3
8 G2 6 6
C285 PRTR5V0U2X_SOT143-4~D 1 2
TYCO_2041084-6~D 0.1U_0402_16V4Z~D R409 0_0402_5%~D
A 2 A
1 2
R410 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
FingerprintCONN. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Title
SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 23 of 77
5 4 3 2 1
 5 4 3 2 1

LCD Power Q18

SI3456DDV-T1-GE3_TSOP6~D
+15V_ALW +LCDVDD +3.3V_ALW

D
S
6
ACES_59003-0400C-001 +LCDVDD +15V_ALW 4 5

1
2
1 R412 1
GND

1
DMN66D0LDW-7_SOT363-6~D

470_0402_5%~D

100K_0402_5%~D
100K_0402_5%~D

G
BATT_WHITE_LED 2 BATT_WHITE_LED <44> 1

1
R413
3 BATT_YELLOW_LED <44>

3
BATT_YELLOW_LED

R414
4 C292
BREATH_WHITE_LED <44>

2
BREATH_WHITE_LED 0.1U_0402_16V4Z~D
VR_SRC 5 +BL_PWR_SRC 2

DMN66D0LDW-7_SOT363-6~D
6

6 2
VR_SRC

0.1U_0402_25V4Z~D
7 1 2

2
VR_SRC

3
8 C246 D53 1
NC

Q19A
D DISP_ON 0.1U_0603_50V4Z~D RB751V-40GTE-17_SOD323-2~D D
DISP_ON/OFF# 9

Q19B

C293
10 BIA_PWM_LVDS 2 1
PWM <16,40> ENVDD_PCH
CONNTST_GND 11 2 5
2
VR_GND 12

1
13

4
VR_GND D6
VR_GND 14
LCD_B_CLK+ 15 SW_LVDS_BCLK+ <23>
LCD_B_CLK- 16 SW_LVDS_BCLK- <23> <40> LCD_VCC_TEST_EN 2
17 1 EN_LCDPWR 2
GND
LVDS_B2+ 18 SW_LVDS_B2+ <23>
19 SW_LVDS_B2- <23> 3 Q20
LVDS_B2- <47> ENVDD_GPU
20 SW_LVDS_B1+ <23> PDTC124EU_SC70-3~D
LVDS_B1+
21 SW_LVDS_B1- <23>

3
LVDS_B1- BAT54CW_SOT323-3~D
LVDS_B0+ 22 SW_LVDS_B0+ <23>
LVDS_B0- 23 SW_LVDS_B0- <23>
GND 24
LVDS_A_CLK+ 25 SW_LVDS_ACLK+ <23>
LVDS_A_CLK- 26 SW_LVDS_ACLK- <23>
GND 27
LVDS_A2+ 28 SW_LVDS_A2+ <23>
LVDS_A2- 29 SW_LVDS_A2- <23>
30 SW_LVDS_A1+ <23> D66 1 2 RB751V-40GTE-17_SOD323-2~D
LVDS_A1+ BIA_PWM_PCH <16> Q21
LVDS_A1- 31 SW_LVDS_A1- <23> DGPU_SESECT#
32 +PWR_SRC FDC654P-G_SSOT-6~D
LVDS_A0+
33
SW_LVDS_A0+ <23>
+3.3V_RUN 40mil
LVDS_A0- LDDC_DATA_SW
SW_LVDS_A0- <23>
40mil

D
EDID_DATA 34 LDDC_DATA_SW <23> 6 +BL_PWR_SRC

5
LDDC_CLK_SW @ U93

S
46 MGND6 EDID_CLK 35 LDDC_CLK_SW <23> 4 5
45 36 LCD_TST 2

P
OE#
MGND5 BIST LCD_TST <40>

1000P_0402_50V7K~D
44 37 +3.3V_RUN BIA_PWM_LVDS 1 2 BIA_PWM_LVDS_R 4 2 1
MGND4 V_EDID Y A BIA_PWM_GPU <47>

G
43 38 +LCDVDD @ RE9 0_0603_5% 1
MGND3 LCD_VDD

1
10K_0402_5%~D
42 39 74AHCT1G125GW_SOT353-5 1

3
MGND2 LCD_VDD

R1137
41 40 LVDS_CBL_DET# R422 C296
LVDS_CBL_DET# <17>

3
MGND1 CONNTST

C297
C 100K_0402_5%~D 0.1U_0603_50V4Z~D C
2
JLVDS1 CONN@ D63 2
1 2

2
RB751V-40GTE-17_SOD323-2~D

2
PWR_SRC_ON
D68 1 2 RB751V-40GTE-17_SOD323-2~D BIA_PWM_EC <41> Q22
SSM3K7002FU_SC70-3~D

D67 2 RB751V-40GTE-17_SOD323-2~D

S
1 PANEL_BKEN_PCH <16> 1 2 1 3
R423 47K_0402_5%~D

G
2
+3.3V_RUN DISP_ON D64 1 2 RB751V-40GTE-17_SOD323-2~D PANEL_BKEN_DGPU <47>

100K_0402_5%~D
1
1 2 LDDC_CLK_SW EN_INVPWR
<41> EN_INVPWR

R1138
R159 2.2K_0402_5%~D FDC654P: P CHANNAL
1 2 LDDC_DATA_SW D69 1 2 RB751V-40GTE-17_SOD323-2~D PANEL_BKEN_EC <40>
R160 2.2K_0402_5%~D
Panel backlight power control by EC

2
Place near to JLVDS1

+5V_TSP +5V_RUN +5V_TSP

CONN@
JCAM1 +15V_ALW 1 2
+LCDVDD +3.3V_RUN

0.1U_0402_10V7K~D
1 @ R1001 0_0603_5%~D
<17> CAM_MIC_CBL_DET# 1
0.1U_0402_16V4Z~D

USBP12_D+ 2 2
0.1U_0402_16V4Z~D

USBP12_D- 3 PMV45EN_SOT23-3~D 1
3

1
+CAMERA_VDD 4 4

0.1U_0402_25V4Z~D

C302
S

D
B B
1 1 <30> DMIC_CLK 5 5 3 1
6 R430 CONN@
6 2
C243

7 100K_0402_5%~D Q32 1 JTCH1

<30> DMIC0 7 +3.3V_ALW
C298

C306
G
8 1

2
2 2 8 1
SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

9 G1 2 2
1

10 G2 <18> E3_PAID_TS_DET# 3 3

1
2 USBP13_D- 4 4
D8

D7

Close to JLVDS1 of 42,43 pins Close to JLVDS1.41 JST_BM08B-SRSS-TB1-LF-SN~D R431 USBP13_D+ 5

@ @ 100K_0402_5%~D 5
1 6 6

DMN66D0LDW-7_SOT363-6~D
7
2

C304 Shield
8

2
Shield

3
0.1U_0402_25V4Z~D
2 MOLEX_48226-0611
+CAMERA_VDD

Q125B
For Webcam

DMN66D0LDW-7_SOT363-6~D
5 @ D74
USBP13_D- 2

6
S

3 1 +3.3V_RUN 1

4
0.1U_0402_16V4Z~D

@ L10 USBP13_D+ 3
10U_0805_10V4Z~D

Q125A
Q23 DLW21SN121SQ2L_4P~D
PMV45EN_SOT23-3~D USBP12+ USBP12_D+ PESD5V0U2BT_SOT23-3~D
G

1 1 <17> USBP12+ 1 2 2 <41> TOUCH_SCREEN_PD# 2

2

1
C299

C300

Place close JTCH1

1
USBP12- 4 3 USBP12_D-
2 2 <17> USBP12- 4 3 @LE1
@ LE1
1 2 USBP13_D+
+15V_ALW <17> USBP13+ 1 2
1 1 2
R427 0_0402_5%~D
C301 4 USBP13_D-
<17> USBP13- 4 3 3
1

0.1U_0402_16V4Z~D 1 2 DLW21SN121SQ2L_4P~D
R429 2 R428 0_0402_5%~D
100K_0402_5%~D Touch Screen Connector RE3
1 2
0_0402_5%~D
A A
2

1 2
@ D75 RE4 0_0402_5%~D
Webcam PWR CTRL USBP12_D- 2
1

D
SSM3K7002FU_SC70-3~D

1
<40> CCD_OFF
CCD_OFF 2 1 USBP12_D+ 3 DELL CONFIDENTIAL/PROPRIETARY
Q24

G
C303 PESD5V0U2BT_SOT23-3~D
S
Compal Electronics, Inc.
3

0.1U_0402_25V4Z~D
2 Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATICS,MB A6561
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 24 of 77
5 4 3 2 1
 2 1

+3.3V_RUN +3.3V_RUN_CRTSW +5V_RUN +5V_RUN_CRTSW

@ PJP57 @PJP58
@ PJP58
1 2 1 2

PAD-OPEN1x1m PAD-OPEN1x1m

+5V_RUN_CRTSW

1
U92 +3.3V_RUN_CRTSW
C1182
<47> GPU_CRT_RED 7
17
REDA
MAX14885E VCC 29
2
1U_0603_10V7K~D
<16> PCH_CRT_RED REDB 1
VCC 21
8 C1181
<47> GPU_CRT_GRN GRNA 1U_0402_6.3V6K~D
<16> PCH_CRT_GRN 18 GRNB VL 11
2
<47> GPU_CRT_BLU 9 BLUA
<16> PCH_CRT_BLU 19 BLBU
B B
RED1 33 RED_CRT <46>
5 24
Channel A --> GPU <47> GPU_CRT_CLK_DDC
<16> PCH_CRT_DDC_CLK 15
SCLA
SCLB
RED2 RED_DOCK <39>
32
<47> GPU_CRT_DAT_DDC 6 SDAA
GRN1
GRN2 23
GREEN_CRT <46>
GREEN_DOCK <39>
Port 1 --> MB Port RGB
<16> PCH_CRT_DDC_DAT 16 SDAB
BLU1 31 BLUE_CRT <46>
+3.3V_RUN 1 2 CRT_EN 2 EN BLU2 22 BLUE_DOCK <39>
R1584 100K_0402_5%~D
<47> GPU_CRT_HSYNC 3 SHA SCL1 35 CLK_DDC2_CRT <46>
13 26
Channel B --> PCH
<16> PCH_CRT_HSYNC SHB SCL2 CLK_DDC2_DOCK <39> Port 2 --> Docking Port RGB
<47> GPU_CRT_VSYNC 4 SVA SDA1 34 DAT_DDC2_CRT <46>
<16> PCH_CRT_VSYNC 14 SVB SDA2 25 DAT_DDC2_DOCK <39>

<40> EDID_SELECT# 1 S00 SH1 37 HSYNC_BUF <46>

CRT_SWITCH 40 28
<40> CRT_SWITCH S01 SH2 HSYNC_DOCK <39>
<23,40> DGPU_SELECT# 39 S10
CRT_SWITCH 38 36
S11 SV1 VSYNC_BUF <46>
SV2 27 VSYNC_DOCK <39>
30 GND
20 GND NC 12
10 GND
41 GPAD
MAX14885EETL+T_TQFN40_5X5~D

S01/S11 CRT_SWITCH 0 0 1 1

S10 DGPU_SELECT# 0 1 0 1

S00 EDID_SELECT# 0 1 0 1

A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title
SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 25 of 77
2 1
 2 1

+5V_RUN

BAT1000-7-F_SOT23-3~D
2
3

D4
NC
1
+3.3V_RUN +VDISPLAY_VCC

1
+5V_RUN_HDMI

0.1U_0402_10V7K~D

10U_0805_10V4Z~D
R443 1 1
4.7K_0402_5%~D

C337

C338
2A_8VDC_SMD1812P200TF
2
HDMI_OE# 2 2

2
0_1206_5%~D
@

1
+3.3V_RUN D
+3.3V_RUN

F2

R5
HDMI_HPD_SINK 2 Q25
G SSM3K7002FU_SC70-3~D

1
1 2 HDMI_SDA_CTL S

1
@R446
@ R446 4.7K_0402_5%~D PJP65
1 2 HDMI_SCL_CTL PAD-OPEN1x1m R1168
@R447
@ R447 4.7K_0402_5%~D 10K_0402_5%~D JHDMI1 CONN@
HDMI_HPD_SINK 1 2HDMI_HPD_SINK_R 19 HP_DET
18

2
B +5V B
ClosetoU19VCCpins 17 DDC/CEC_GND
+3.3V_RUN_HDMI HDMI_SDA_SINK 16
HDMI_SCL_SINK SDA
15 SCL

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 1 1 1 1 1 1 1 14 Reserved
HDMI_CEC 13 CEC

C354

C339

C340

C341

C342

C343

C344

C345
TMDSE_CON_CLK# 12 CK-

11
15
21
33
40
46
11 CK_shield
U19 2 2 2 2 2 2 2 2 TMDSE_CON_CLK 10 CK+
TMDSE_CON_N0 9

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
D0-
8 D0_shield
C346 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_P2 38 TMDSE_CON_P0 7
<48> TMDSE_GPU_P2 IN1p D0+
C347 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_N2 39 TMDSE_CON_N1 6
<48> TMDSE_GPU_N2 IN1n D1-
C348 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_P1 41 5
<48> TMDSE_GPU_P1 IN2p D1_shield
C349 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_N1 42 TMDSE_CON_P1 4 23
<48> TMDSE_GPU_N1 IN2n D1+ GND
C350 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_P0 44 23 TMDSE_RP_P2 TMDSE_CON_N2 3 22
<48> TMDSE_GPU_P0 IN3p OUT1p D2- GND
C351 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_N0 45 22 TMDSE_RP_N2 2 21
<48> TMDSE_GPU_N0 IN3n OUT1n D2_shield GND
C352 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_CLK 47 20 TMDSE_RP_P1 TMDSE_CON_P2 1 20
<48> TMDSE_GPU_CLK IN4p OUT2p D2+ GND
C353 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_CLK# 48 19 TMDSE_RP_N1
<48> TMDSE_GPU_CLK# IN4n OUT2n
17 TMDSE_RP_P0 SUYIN_100042GR019M23MZR
OUT3p TMDSE_RP_N0
OUT3n 16
+3.3V_RUN 2 14 TMDSE_RP_CLK
+5V_RUN POW OUT4p TMDSE_RP_CLK#
OUT4n 13
HDMI_HPD_SINK 30 HPD_SINK
2

1 2 26 1 2
0_0402_5%~D

+3.3V_RUN I2C_CTL_EN#
1

@ R457 4.7K_0402_5%~D @R451

@ R451 0_0402_5%~D
32 DLW21SN900HQ2L_0805_4P~D
R1163

@ D65
@D65 NC/DDCBUF_EN# TMDSE_RP_CLK TMDSE_CON_CLK
1 1 2 2
RB751V-40GTE-17_SOD323-2~D HDMI_OE# 25 7 DPE_GPU_HPD DPE_GPU_HPD <47>
NC/OE# HPD
2

R460 2 1 1.5K_0402_5%~D HDMI_SDA_SINK 8 TMDSE_RP_CLK# 4 3 TMDSE_CON_CLK#

1

+5V_HDMI_DDC SDA 4 3
R461 2 1 1.5K_0402_5%~D HDMI_SCL_SINK 9 SCL
29 TMDS_E_GPU_DDC# L19
SDAZ TMDS_E_GPU_DDC# <48>
HDMI_SDA_CTL 34 28 TMDS_E_GPU_DDC 1 2
+3.3V_RUN SDA_CTL/CFG1 SCLZ TMDS_E_GPU_DDC <48>
HDMI_SCL_CTL 35 @R459
@ R459 0_0402_5%~D
SCL_CTL/CFG0
1 2 PC0 3
R463 1 I2C_ADDR0/PC0
2 4.7K_0402_5%~D PC1 4 I2C_ADDR1/PC1
@ R464 4.7K_0402_5%~D
1 2 PC2 1
R465 4.7K_0402_5%~D GND/PC2
1 2
@R462
@ R462 0_0402_5%~D
6 DLW21SN900HQ2L_0805_4P~D
REXT TMDSE_RP_P0 TMDSE_CON_P0
1 2
GND10

1 2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

10 CEXT
1
2

TMDSE_RP_N0 4 3 TMDSE_CON_N0
R467 C355 PS121QFN48G_QFN48_7X7 4 3
5
12
18
24
27
31
36
37
43
49

499_0402_1%~D 2.2U_0402_6.3V6M~D L20

2
1 2
+3.3V_RUN @R466
@ R466 0_0402_5%~D
1

HDMI_CEC 2 1
R1165 10K_0402_5%~D
EQUALIZATION SETTING: @R468
@
1
R468
2
0_0402_5%~D
[PC2,PC1,PC0]=000, 12dB DLW21SN900HQ2L_0805_4P~D
TMDSE_RP_P1 1 2 TMDSE_CON_P1
[PC2,PC1,PC0]=001, 16dB 1 2

[PC2,PC1,PC0]=010, 10dB TMDSE_RP_N1 4 3 TMDSE_CON_N1

4 3
[PC2,PC1,PC0]=011, 7dB DPE_GPU_HPD 1
R1128
2
100K_0402_5%~D L21
A [PC2,PC1,PC0]=100, 1.5dB 1 2 A
@R469
@ R469 0_0402_5%~D
[PC2,PC1,PC0]=101, 4dB (Default)
[PC2,PC1,PC0]=110, 9dB
[PC2,PC1,PC0]=111, 7dB 1 2
@R470
@ R470 0_0402_5%~D
DLW21SN900HQ2L_0805_4P~D
TMDSE_RP_P2 1 2 TMDSE_CON_P2
1 2

TMDSE_RP_N2 4 3 TMDSE_CON_N2
4 3
L22
1 2
@R471
@ R471 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 26 of 77
2 1
 5 4 3 2 1

+3.3V_RUN +3.3V_RUN
AUX/DDC GPU for DPC to E-DOCK 2 1 C366
0.1U_0402_16V4Z~D
AUX/DDCGPUforDPDtoEͲDOCK 2
C371
1

0.1U_0402_16V4Z~D

C367 U23 C372 U29

0.1U_0402_10V7K~D 1 14 0.1U_0402_10V7K~D 1 14
DPC_AUX_C BE0 VCC BE0 VCC
<48> DPC_GPU_AUX/DDC 2 1 2 A0 BE3 13 <48> DPD_GPU_AUX/DDC 2 1DPD_GPU_AUX_C 2 A0 BE3 13
D DPC_DOCK_AUX DPC_GPU_AUX/DDC DPD_DOCK_AUX DPD_GPU_AUX/DDC D
<39> DPC_DOCK_AUX 3 B0 A3 12 <39> DPD_DOCK_AUX 3 B0 A3 12

4 BE1 B3 11 4 BE1 B3 11
2 1 DPC_AUX#_C 5 10 2 1DPD_GPU_AUX#_C 5 10
<48> DPC_GPU_AUX#/DDC A1 BE2 <48> DPD_GPU_AUX#/DDC A1 BE2
C368 0.1U_0402_10V7K~D C373 0.1U_0402_10V7K~D
DPC_DOCK_AUX# 6 9 DPC_GPU_AUX#/DDC DPD_DOCK_AUX# 6 9 DPD_GPU_AUX#/DDC
<39> DPC_DOCK_AUX# B1 A2 <39> DPD_DOCK_AUX# B1 A2
7 GND B2 8 7 GND B2 8

PI3C3125LEX_TSSOP14~D PI3C3125LEX_TSSOP14~D

+5V_RUN +5V_RUN

2 1 2 1
C369 0.1U_0402_16V4Z~D C370 0.1U_0402_16V4Z~D

1
P

P
NC

NC
DPC_CA_DET 2 4 DPC_CA_DET# DPD_CA_DET 2 4 DPD_CA_DET#
<39> DPC_CA_DET A Y <39> DPD_CA_DET A Y

G
U24 U25
NC7SZ04P5X_NL_SC70-5~D NC7SZ04P5X_NL_SC70-5~D

3
C C

+3.3V_RUN +3.3V_RUN
1

1
+15V_ALW +15V_ALW
R1539 R1062
2.2K_0402_5%~D 2.2K_0402_5%~D
2

2
1

1
+3.3V_ALW2 1 2 +3.3V_ALW2 1 2
R1537 @R1538
@ R1538 0_0402_5%~D R1063 @ R1064 0_0402_5%~D
6

6
100K_0402_5%~D 100K_0402_5%~D

Q113A Q111A
2

2
1

1
2 DMN66D0LDW-7_SOT363-6~D 2 DMN66D0LDW-7_SOT363-6~D
R1532 R1065
3

3
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D 100K_0402_5%~D
1

1
Q110B

Q109B
2

2
B DPC_DOCK_AUX DPD_DOCK_AUX B
5 5
+3.3V_RUN +3.3V_RUN
6

6
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D
4

4
1

1
Q110A

Q109A
DPC_CA_DET 2 R1530 DPD_CA_DET 2 R1066
2.2K_0402_5%~D 2.2K_0402_5%~D
1 1
1

1
2

2
C1174 C1175
0.01U_0402_16V7K~D 1 2 0.01U_0402_16V7K~D 1 2
2 @ R1523 0_0402_5%~D 2 @R1067
@ R1067 0_0402_5%~D
3

3
Q113B Q111B
5 DMN66D0LDW-7_SOT363-6~D 5 DMN66D0LDW-7_SOT363-6~D
4

4
DPC_DOCK_AUX# DPD_DOCK_AUX#

A A
1 2 DPD_CA_DET
R491 1M_0402_5%~D

1
R492
2 DPC_CA_DET
1M_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 27 of 77
5 4 3 2 1
 5 4 3 2 1

FreeFallSensor
+3.3V_RUN
D D
PJP53
+3.3V_RUN 2 1 +3.3V_RUN_FFS

10U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
PAD-OPEN1x1m
1 2 DDR_XDP_WAN_SMBDAT 1 1
R501 10K_0402_5%~D U26

C387

C388
DDR_XDP_WAN_SMBCLK
1
R502
2
10K_0402_5%~D
DE351DLTR
HDD_FALL_INT 2 2
1 2 1 VDD_IO
R503 100K_0402_5%~D 6 2
VDD GND
GND 4
HDD_FALL_INT 8 5
<17> HDD_FALL_INT FFS_INT2 INT 1 GND
9 INT 2 GND 10

12 SDO
<7,12,13,14,15,37> DDR_XDP_WAN_SMBDAT 13 SDA / SDI / SDO
14 SCL / SPC
<7,12,13,14,15,37> DDR_XDP_WAN_SMBCLK RSVD 3 +3.3V_RUN
7 CS RSVD 11
+3.3V_RUN +5V_HDD

DE351DLTR8_LGA14_3X5~D

1
@ R506
100K_0402_5%~D
2
G

2
FFS_INT2 3 1 1 2 FFS_INT2_Q
<18> FFS_INT2
S

C C
D16
Q29 SDM10U45-7_SOD523-2~D
SSM3K7002FU_SC70-3~D

HDDPWR
+5V_ALW
+15V_ALW

+3.3V_ALW2
ForHDDTemp.

1
@ R499

1
2
5
6
100K_0402_5%~D

1
JSATA1 CONN@ D @ Q27
1 @ R500
@R500 G

2
PSATA_PTX_DRX_P0_C C389 2 GND
<14> PSATA_PTX_DRX_P0_C 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0 2 RX+
100K_0402_5%~D HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
PSATA_PTX_DRX_N0_C C390 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0 3 S
<14> PSATA_PTX_DRX_N0_C RX-

DMN66D0LDW-7_SOT363-6~D
4 +5V_HDD @ +5V_RUN

4
GND

3
PSATA_PRX_DTX_N0_C 2 1 SATA_PRX_DTX_N0 5 PJP3
<14> PSATA_PRX_DTX_N0_C TX-

0.1U_0603_50V4Z~D
PSATA_PRX_DTX_P0_C C391 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6 @ 1 2
<14> PSATA_PRX_DTX_P0_C TX+

Q28B

10U_0805_10V4Z~D

100K_0402_5%~D
C392 0.01U_0402_16V7K~D 7
@ PJP71 GND JUMP_43X79
5 1 1

1
+3.3V_RUN 1 2 +3.3V_RUN_HDD 8 @
3.3V

6
DMN66D0LDW-7_SOT363-6~D

C393

C394

R504
B B
9

4
3.3V @
PAD-OPEN1x1m 10 3.3V 2 2
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Q28A
1 1 11 GND
@C1186
@

@C1185
@

HDD_DET# 12 2
<41> HDDC_EN

2
<14> HDD_DET# GND
C1186

C1185

13 GND
+5V_HDD 14

1
5V

1
2 2
15 5V
16 R505
17
5V
GND
100K_0402_5%~D +5V_HDD Source
FFS_INT2_Q 18 23
Reserved GND1
19 24

2
GND GND2
20 12V
21 12V
22 12V
JAE_SP100421-HDD

Main SATA +5V Default

+5V_HDD
1000P_0402_50V7K~D

1 1
C395

C396
0.1U_0402_16V4Z~D
2 2
A A

DELL CONFIDENTIAL/PROPRIETARY
Pleace near HDD CONN
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 28 of 77
5 4 3 2 1
 5 4 3 2 1

ForODD JSATA2 CONN@

+3.3V_ALW 2 1 1
<14> SATA_ODD_PTX_DRX_P1_C GND
0.01U_0402_16V7K~D C407 SATA_ODD_PTX_DRX_P1 2 A+
1 2 ZODD_WAKE# <14> SATA_ODD_PTX_DRX_N1_C 2 1 SATA_ODD_PTX_DRX_N1 3 A-
R510 10K_0402_5%~D 0.01U_0402_16V7K~D C406 4 GND
1 2 MOD_MD <14> SATA_ODD_PRX_DTX_N1_C 2 1 SATA_ODD_PRX_DTX_N1 5 B-
R516 10K_0402_5%~D 0.01U_0402_16V7K~D C405 SATA_ODD_PRX_DTX_P1 6 B+
<14> SATA_ODD_PRX_DTX_P1_C 2 1 7 GND
0.01U_0402_16V7K~D C404
D DEVICE_DET# D
<41> DEVICE_DET# 8 DP
1 2 +5V_MOD 9 +5V
+3.3V_ALW_PCH @CE7
@ CE7 150P_0402_50V8J~D 10
MOD_MD +5V
11 MD
12 GND
13 GND
1 2 USB30_SMI#
R514 100K_0402_5%~D 14 GND
<15> CLK_PCIE_EMB 15 REFCLK+
<15> CLK_PCIE_EMB# 16 REFCLK-
17 GND
<15> PCIE_PRX_EMBTX_P4 18 PETX+
<15> PCIE_PRX_EMBTX_N4 19 PETX-
+5V_MOD 20 GND
21 GND
0.1U_0402_10V7K~D 2 1 C409 PCIE_PTX_EMBRX_P4_C 22
<15> PCIE_PTX_EMBRX_P4 PERX+
1000P_0402_50V7K~D

0.1U_0402_10V7K~D 2 1 C408 PCIE_PTX_EMBRX_N4_C 23

<15> PCIE_PTX_EMBRX_N4 PERX-
0.1U_0402_16V4Z~D

1 1 24 GND
C397

C398

+5V_MOD 25 +5V
<15> EMBCLK_REQ# 26 CLKREQ#
2 2
<37,38,40> PCIE_WAKE# 27 WAKE#
<17> PLTRST_EMB# 28 PERST#
<41,53> BAY_SMBDAT 29 SMB_DATA GND1 32
<41,53> BAY_SMBCLK 30 SMB_CLK GND2 33
MOD_SATA_PCIE#_DET 31
<40> MOD_SATA_PCIE#_DET HPD +5VMOD Source +15V_ALW +5V_ALW
+3.3V_ALW 1 2
R1177 100K_0402_5%~D TYCO_2-2129116-1

1
Pleace near ODD CONN +3.3V_ALW2
R507
100K_0402_5%~D

1
2
5
6
C C
R509 D Q30

2
100K_0402_5%~D G
2 MOD_EN 3 SI3456DDV-T1-GE3_TSOP6~D
S

3
DMN66D0LDW-7_SOT363-6~D
+5V_MOD @ +5V_RUN

4
0.1U_0603_50V4Z~D
PJP4

Q31B
+3.3V_ALW 1 2
Q76

10U_0805_10V4Z~D
MODC_EN# 5 1

1
SSM3K7002FU_SC70-3~D 1 JUMP_43X79

6
DMN66D0LDW-7_SOT363-6~D

C400
R511

C401
S

MOD_MD 3 1 ZODD_WAKE# R515 100K_0402_5%~D

ZODD_WAKE# <40> 2

Q31A
100K_0402_5%~D
MODC_EC 2 2
<40> MODC_EN

2
G
2

1
MODC_EN#

1
USB30_EN R512
100K_0402_5%~D

Q123B Q123A

2
6
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
4 3 USB30_SMI#
USB30_SMI# <14>
MOD_SATA_PCIE#_DET 2
5

USB30_EN

1
B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 29 of 77
5 4 3 2 1
 2 1

place close to pin27 place close to pin38 L77

DVDD_IOshouldmatch BLM21PG600SN1D_0805~D
InternalSpeakersHeader withHDABuslevel
+VDDA_AVDD 1 2 +5V_RUN

10U_0805_10V6K~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D
+3.3V_RUN_DVDD +5V_RUN
1 1 1 1 1

C955

C956

C957

C1172

C1173
+VREFOUT_R

2
0_0805_5%~D
15milstrace JSPK1 CONN@ 2 2 2 2 2

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

10U_0805_10V6K~D

R1095
INT_SPK_L+ L91 1 2 BLM18BD121SN1D_2P~D INT_SPKL_L+ 1
2
1 1 1 1 1 PlaceC994,C952~C957closetoCodec
2

C994

C953

1U_0603_10V6K~D
INT_SPK_L- L92 1 2 BLM18BD121SN1D_2P~D INT_SPKR_L- 3 1

1
3

C952

C954
4 4 2 2 2 2

C1180
INT_SPK_R+ L93 1 2 BLM18BD121SN1D_2P~D INT_SPKR_R+ U72

0.1U_0402_16V4Z~D
5 GND 1 DVDD_CORE AVDD1 27
2

10U_0805_10V6K~D

0.1U_0402_16V4Z~D

10U_0805_10V6K~D
INT_SPK_R- L94 1 2 BLM18BD121SN1D_2P~D INT_SPKR_R- 6 38 1 1 1 1
GND AVDD2

C958

C959

C960

C961
TYCO_2-1775765-4 3 45 +VDDA_PVDD
DVDD_IO PVDD
PVDD 39
2 2 2 2
9 13 AUD_SENSE_A
DVDD SENSE_A AUD_SENSE_B
SENSE_B 14

28 MIC_IN_L 1 2 MIC_IN_LandMIC_IN_RR R161pop0ͲohmforComboJack,

PCH_AZ_CODEC_BITCLK PORTA_L MIC_IN_RR C1163 1U_0402_6.3V6K~D
<14> PCH_AZ_CODEC_BITCLK 6 BITCLK PORTA_R 29 MIC_IN_R <46> mustsymmetricinlayout pop1UFforE2backupcircuit
VrefOut_A 23 +VREFOUT

2
PESD5V0U2BT_SOT23-3~D

PESD5V0U2BT_SOT23-3~D
PCH_AZ_CODEC_SDOUT 5 1 2 +VREFOUT_R MIC_IN_RR 1 2
<14> PCH_AZ_CODEC_SDOUT SDATA_OUT

@ DE2

@ DE1
31 AUD_HP_OUT_L R1143 2.2K_0402_5%~D R161 0_0402_5%~D
PORTB_L AUD_HP_OUT_R AUD_HP_OUT_L <46> +VREFOUT_R 2 MIC_IN_R
<14> PCH_AZ_CODEC_SYNC 10 SYNC PORTB_R 32 AUD_HP_OUT_R <46> 1
PlaceR1096closetocodec D70 RB751V-40GTE-17_SOD323-2~D
1 2 PCH_AZ_SDIN0_R 8 40 INT_SPK_L+
B <14> PCH_AZ_CODEC_SDIN0 33_0402_5%~D SDATA_IN PORTD_+L INT_SPK_L- B
PORTD_-L 41
R1096 PCH_AZ_CODEC_RST# 11
<14> PCH_AZ_CODEC_RST# RESET#
44 INT_SPK_R+
PORTD_+R INT_SPK_R-
43

1
PORTD_-R
I2S_MCLK 1 2 I2S_MCLK_R 15 25
RE13 0_0402_5%~D I2S_MCLK MONO_OUT SPKR_R
2 1 1 2 SPKR <14>
I2S_BCLK 1 2 I2S_BCLK_R 16 12 AUD_PC_BEEP C1105 0.1U_0402_16V4Z~D R1119 100K_0402_5%~D
RE10 0_0402_5%~D I2S_SCLK PC_BEEP BEEP_R
2 1 1 2 BEEP <41>
I2S_DO 1 2 17 C1106 0.1U_0402_16V4Z~D R1120 100K_0402_5%~D
R1097 33_0402_5%~D I2S_DOUT DMIC_CLK_L 1
DMIC_CLK/GPIO 1 2 2 DMIC_CLK <24>
I2S_LRCLK 18 4 LE2 BLM18BB221SN1D_2P~D
I2S_LRCLK DMIC_0/GPIO 2 DMIC0 <24>

680P_0402_50V7K~D

680P_0402_50V7K~D

680P_0402_50V7K~D

680P_0402_50V7K~D
PlaceR1097closetocodec DMIC1/GPIO0/SPDIFOUT1 46 1 1 1 1
+3.3V_RUN +3.3V_RUN_DVDD I2S_DI# 24 48 1 2
I2S_DIN SPDIFOUT0//GPIO3/Aux_Out

C973

C974

C975

C976
Close to U72 pin5 Close to U72 pin6 @ PJP60 @ R1141 10K_0402_5%~D
1 2 CAP+ 36 1 2
@ R1142 10K_0402_5%~D 2 2 2 2
1
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK 19 C962
PAD-OPEN1x1m No Connect 4.7U_0603_10V6K~D
20 No Connect PlaceC962closetoCodec
1

2
CAP- 35
@ R1077 @ R1076 PlaceC963~C966closetoCodec
47_0402_5%~D 10_0402_5%~D 47 21
<40> AUD_NB_MUTE# EAPD VREFFILT
CAP2 22
+3.3V_RUN 34
2

V-
1 1 7 DVSS Vreg 37

4.7U_0603_10V6K~D

4.7U_0603_10V6K~D

1U_0603_10V6K~D

10U_0805_10V6K~D
1 1 1 1
@C978
@C978 @ C977 1 2 42 26
PVSS AVSS1

C963

C964

C965

C966
0.1U_0402_10V7K~D 10P_0402_50V8J~D R1099 10K_0402_5%~D 30
2 2 AVSS
BCLK: Audio serial data bus bit clock input/output 49 GND AVSS 33
2 2 2 2
LRCK: Audio serial data bus word clock input/output
92HD90B2X5NLGXYAX8_QFN48_7X7~D

+VDDA_AVDD Notes:
place at AGND and DGND plane
Place closely to Pin 13. R1083
KeepPVDDsupplyandspeakertracesroutedontheDGNDplane.
AUD_SENSE_A
2.49K_0402_1%~D 1 2 KeepawayfromAGNDandotheranalogsignals
2 1
C981 @ place at Codec bottom side +3.3V_RUN +3.3V_RUN
100P_0402_50V8J~D
1000P_0402_50V7K~D

@ PJP62
+3.3V_RUN +3.3V_RUN
39.2K_0402_1%~D

1 1 2 1 2
1

0.1U_0402_10V7K~D
C980

@
R352

R1086 C982
20K_0402_1%~D 100P_0402_50V8J~D PAD-OPEN1x1m
1

2
2

DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D
@ 1 2 2

C1103

@ D54

@ D55

@ D56

@ D57
@ R1088 R1087
2

100K_0402_5%~D 100K_0402_5%~D C983

100P_0402_50V8J~D
6

1 U73
2

16

1
VCC
2 5 I2S_BCLK 2 3
<46> AUD_MIC_SWITCH AUD_HP_NB_SENSE <40,46> 1A 1Y# DAI_BCLK# <39>
1
Q107A Q107B I2S_LRCLK 4 5
1

DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D @C967

@C967 2A 2Y# DAI_LRCK# <39>
Resistor SENSE_A SENSE_B
0.1U_0402_16V4Z~D I2S_DO 6 7
2 3A 3Y# DAI_DO# <39>

39.2K PORTA PORTE I2S_MCLK 10 9

4A 4Y# DAI_12MHZ# <39>
Add for solve pop noise and detect issue 12 5A 5Y# 11
20K PORTB PORTF +3.3V_RUN
14 13 I2S_DI#
6A 6Y#
A A
10K NA DMIC0 <40> EN_I2S_NB_CODEC# 1 OE1#

2
2 1 15 OE2# GND 8
Place closely to Pin 14 @ D58
+VDDA_AVDD 5.11K SPDIFOUT0 SPDIFOUT1(DMIC1) R1540 DA204U_SOT323-3~D
R1078 1K_0402_5%~D CD74HC366M96_SO16~D
2.49K_0402_1%~D
AUD_SENSE_B 2 1 2.49K PullͲuptoAVDD

1
1000P_0402_50V7K~D

1 DAI_DI <39>
1

+3.3V_RUN
C979

+3.3V_RUN
PORTA ExternalMIC
R1079 R1080
39.2K_0402_1%~D 20K_0402_1%~D 2
1

PORTB HeadPhoneOut
1

R1081
2

100K_0402_5%~D R1082
100K_0402_5%~D PORTC DockAudio
2

PORTD InternalSPK
<40> DOCK_HP_DET 2 5 DOCK_MIC_DET <40> DELL CONFIDENTIAL/PROPRIETARY
Q106A Q106B
Compal Electronics, Inc.
1

DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 30 of 77
2 1
 5 4 3 2 1

D D

SW1
POWER_SW#_MB 2 1
<41,42> POWER_SW#_MB

4 3

SKRBAAE010_4P~D

@ D23
3
1 PESD24VS2UT_SOT23-3~D
2

@ SW2
LAT_ON_SW_BTN# 2 1
<41> LAT_ON_SW_BTN#

4 3

SKRBAAE010_4P~D

C C

POWER & INSTANT ON SWITCH

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 31 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_LAN

+3.3V_RUN
1 2 TP_LAN_JTAG_TMS
@R545
@ R545 10K_0402_5%~D

1
1 2 TP_LAN_JTAG_TCK
@R546
@ R546 10K_0402_5%~D R547
10K_0402_5%~D

U31

2
Intel review feed back Default solution:
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ PCH +1.05V_M SVR - stuff R548, unstuff L29
<15> LANCLK_REQ# @ R1187 CLK_REQ_N MDI_PLUS0 LAN_TX0-
<17> PLTRST_LAN# 0_0402_5%~D 36 14 Also, option to use iSVR - stuff L29, unstuff R548
D PE_RST_N MDI_MINUS0 D
CLK_PCIE_LAN 44 17 LAN_TX1+
<15> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
CLK_PCIE_LAN# 45 18 LAN_TX1-
<15> CLK_PCIE_LAN#

PCIE
PE_CLKN MDI_MINUS1

MDI
<15> PCIE_PRX_GLANTX_P7 2 1 PCIE_PRX_GLANTX_P7_C
C458 0.1U_0402_10V7K~D 38 20 LAN_TX2+
PETp MDI_PLUS2 +1.0V_LAN +1.05V_M
<15> PCIE_PRX_GLANTX_N7 2 1 PCIE_PRX_GLANTX_N7_C 39 PETn MDI_MINUS2 21 LAN_TX2-
C459 0.1U_0402_10V7K~D @ R548
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P7_C 41 23 LAN_TX3+ L29 0_0805_5%~D
<15> PCIE_PTX_GLANRX_P7 PERp MDI_PLUS3
C460 0.1U_0402_10V7K~D 42 24 LAN_TX3- REGCTL_PNP10 1 2 1 2
PERn MDI_MINUS3 +3.3V_LAN

10U_0805_6.3V6M~D

0.1U_0402_10V7K~D
<15> PCIE_PTX_GLANRX_N7 1 2 PCIE_PTX_GLANRX_N7_C
1

C461 0.1U_0402_10V7K~D 4.7UH_CBC2012T4R7M_20%~D 1 1

C463
R549 0_0402_5%~D 28 6 VCT_LAN_R1 2 1 Idc max=330mA

SMBUS
@ R551 SMB_CLK RSVD_NC

C462
10K_0402_5%~D
<15> LAN_SMBCLK 1 2 LAN_SMBCLK_R 31 SMB_DATA
@ R550 0_0603_5%~D
<15> LAN_SMBDATA 1 2 LAN_SMBDATA_R RSVD_VCC3P3_1 1 +RSVD_VCC3P3_1 2 1 +3.3V_LAN
@ R552 0_0402_5%~D +RSVD_VCC3P3_2 R553 2 2 2
2 1 4.7K_0402_1%~D
2

RSVD_VCC3P3_2 R554 4.7K_0402_1%~D

SMBus Device Address 0xC8 VDD3P3_IN 5
1 2 LAN_DISABLE#_R 3
<18> PM_LANPHY_ENABLE LAN_DISABLE_N
@ R555 0_0402_5%~D 4 +3.3V_LAN_OUT
VDD3P3_OUT
<40> LAN_DISABLE#_R
VDD3P3_15 15 1
1

LOM_ACTLED_YEL# 26 19 Place R548, C462, C463 and L29 close to U31

@ R557 LOM_SPD100LED_ORG# LED0 VDD3P3_19 C464
27 LED1 29

LED
10K_0402_5%~D LOM_SPD10LED_GRN# VDD3P3_29 +1.0V_LAN 1U_0603_10V6K~D
25 LED2 2
47 +1.0V_LAN +3.3V_LAN
2

VDD1P0_47
VDD1P0_46 46
T142 PAD~D TP_LAN_JTAG_TDI 32 37
T143 PAD~D TP_LAN_JTAG_TDO JTAG_TDI VDD1P0_37
34 JTAG_TDO

JTAG

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

22U_0805_6.3VAM~D
TP_LAN_JTAG_TMS 33 43
JTAG_TMS VDD1P0_43

22U_0805_6.3VAM~D
TP_LAN_JTAG_TCK 35 1 1 1 1 1 1
JTAG_TCK

C1177
VDD1P0_11 11

C466

C467

C468

C469

C1178
C XTALO C
1 2 9 XTAL_OUT VDD1P0_40 40
@ R1144 0_0402_5%~D XTALI 2 2 2 2 2 2
10 XTAL_IN VDD1P0_22 22
Y3 16
25MHZ_12PF_X5H025000DC1H-H VDD1P0_16
VDD1P0_8 8
2 1 LAN_TEST_EN 30 TEST_EN
RES_BIAS 12 7 REGCTL_PNP10 Place C1178 close to pin5
RBIAS CTRL_1P0
18P_0402_50V8J~D

18P_0402_50V8J~D

2 2
VSS_EPAD 49
1

1
1K_0402_5%~D

3.01K_0402_1%~D
C470

C471

Note:
+3.3V_M
R561

R562

82579_QFN48_6X6~D +1.0V_LAN will work at 0.95V to 1.15V

1 1

+1.0V_LAN POWER OPTIONS

2

2
Shared with PCH @ R563
R562 Resistor Value: 1.05V SVR * Internal SRV 0_1206_5%~D
3.01 kohm for Hanksville-M LOM

1
2.37 kohm for Hanksville-D LOM STUFF: R548 STUFF: L29 Q34
NO STUFF: L29 NO STUFF: R548 +3.3V_ALW +3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
+15V_ALW

D
6

S
+3.3V_ALW2 5 4

1
+3.3V_LAN 2

10U_0805_6.3V6M~D

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D
R564 1 1 1 1
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

100K_0402_5%~D

C1164

C475

C476
2 2 2

3
1

2
2 2 2
C472

C473

C474

R565 ENAB_3VLAN
LAN ANALOG 100K_0402_5%~D

3
1 1 1

DMN66D0LDW-7_SOT363-6~D

2200P_0402_50V7K~D
B B
SWITCH

Q35B
39
30
21
14

1
8
4
1

U32 5

C477
VDD
VDD
VDD
VDD
VDD
VDD
VDD

6
DMN66D0LDW-7_SOT363-6~D
38 SW_LAN_TX0+
SW_LAN_TX0+ <33>

4
B0+ SW_LAN_TX0- 2
B0- 37 SW_LAN_TX0- <33>

Q35A
LAN_TX0+ 1 2 LAN_TX0+R 2
L30 12NH_0603CS-120EJTS_5%~D A0+ SW_LAN_TX1+
B1+ 34 SW_LAN_TX1+ <33> <41> AUX_ON 1 2 2
LAN_TX0- 1 2 LAN_TX0-R 3 33 SW_LAN_TX1- @ R566 0_0402_5%~D
A0- B1- SW_LAN_TX1- <33>
L31 12NH_0603CS-120EJTS_5%~D

1
29 SW_LAN_TX2+
LAN_TX1+ 1 LAN_TX1+R B2+ SW_LAN_TX2- SW_LAN_TX2+ <33>
2 6 A1+ B2- 28 SW_LAN_TX2- <33>
L33 12NH_0603CS-120EJTS_5%~D
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+
A1- B3+ SW_LAN_TX3+ <33>
L32 12NH_0603CS-120EJTS_5%~D 24 SW_LAN_TX3-
B3- SW_LAN_TX3- <33>
LAN_TX2+ 1 2 LAN_TX2+R 9 17 LAN_ACTLED_YEL# 1 2
A2+ LEDB0 LAN_ACTLED_YEL# <33> <16,40> SIO_SLP_LAN#
L34 12NH_0603CS-120EJTS_5%~D 18 LED_100_ORG# @R567
@ R567 0_0402_5%~D
LEDB1 LED_100_ORG# <33>
LAN_TX2- 1 2 LAN_TX2-R 10 41 LED_10_GRN#
A2- LEDB2 LED_10_GRN# <33>
L35 12NH_0603CS-120EJTS_5%~D
36 DOCK_LOM_TRD0+
C0+ DOCK_LOM_TRD0+ <39> +3.3V_LAN
LAN_TX3+ 1 2 LAN_TX3+R 11 35 DOCK_LOM_TRD0- C478
A3+ C0- DOCK_LOM_TRD0- <39>
L36 12NH_0603CS-120EJTS_5%~D 0.1U_0402_10V7K~D
LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+ 1 2
A3- C1+ DOCK_LOM_TRD1+ <39>
L37 12NH_0603CS-120EJTS_5%~D 31 DOCK_LOM_TRD1-
C1- DOCK_LOM_TRD1- <39>

5
DOCKED 13 27 DOCK_LOM_TRD2+
<40> DOCKED SEL C2+ DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <39> LOM_SPD100LED_ORG#
26 1

P
C2- DOCK_LOM_TRD2- <39> B
O 4 WLAN_LAN_DISB# <40>
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+ LOM_SPD10LED_GRN# 2
LEDA0 C3+ DOCK_LOM_TRD3+ <39> A

G
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD3-
A LEDA1 C3- DOCK_LOM_TRD3- <39> A
Layout Notice : Place bead as LOM_SPD10LED_GRN# 42 TC7SH08FU_SSOP5~D

3
LEDA2 DOCK_LOM_ACTLED_YEL# U15
close PI3L500 as possible LEDC0 19 DOCK_LOM_ACTLED_YEL# <39>
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <39>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <39>
43 PAD_GND DELL CONFIDENTIAL/PROPRIETARY
1: TO DOCK
FROM NIC DOCKED
0: TO RJ45 TO
Compal Electronics, Inc.
PI3L720ZHEX_TQFN42_9X3P5~D Title
DOCK
SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 32 of 77
5 4 3 2 1
 5 4 3 2 1

D D

T156

SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+

<32> SW_LAN_TX0+ TD1+ TX1+

SW_LAN_TX0- 2
<32> SW_LAN_TX0- TD1-
23 NB_LAN_TX0-
TX1-

+TRM_CT1 3 22 Z2805
TDCT1 TXCT1

+TRM_CT2 4 21 Z2807 +3.3V_LAN

SW_LAN_TX1+ TDCT2 TXCT2 NB_LAN_TX1+
<32> SW_LAN_TX1+ 5 TD2+ 1:1 TX2+ 20
0.47U_0603_10V7K~D

0.47U_0603_10V7K~D

C C

1 1

1U_0603_10V6K~D

0.1U_0402_10V7K~D

470P_0402_50V7K~D
C480

SW_LAN_TX1- 6 19 NB_LAN_TX1-
C479

<32> SW_LAN_TX1- TD2- TX2- 1 1 1

2 2

C481

C482

C1167
2 2 2

SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+

<32> SW_LAN_TX2+ TD3+ TX3+

SW_LAN_TX2- 8
<32> SW_LAN_TX2- TD3-
17 NB_LAN_TX2-
TX3-

+TRM_CT3 9 16 Z2806
TDCT3 TXCT3

+TRM_CT4 10 15 Z2808
TDCT4 TXCT4

75_0402_1%~D

75_0402_1%~D

75_0402_1%~D

75_0402_1%~D
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+
<32> SW_LAN_TX3+ TD4+ TX4+
0.47U_0603_10V7K~D

0.47U_0603_10V7K~D

1 1
+3.3V_LAN:20mils
C483

C484

SW_LAN_TX3- 12 13 NB_LAN_TX3-
2 2 <32> SW_LAN_TX3- TD4- TX4- +3.3V_LAN

1
350uH_IH-115-F~D JLOM1 CONN@

B B
<32> LAN_ACTLED_YEL# 1 2 10 Yellow LED-
R1166 150_0402_5%~D
GND

R571 2

R572 2

R573 2

R574 2
9 Yellow LED+
CHASSIS NB_LAN_TX3- 8 PR4-
NB_LAN_TX3+ 7
GND_CHASSIS PR4+
1 2
C485 1000P_1808_3KV7K~D NB_LAN_TX1- 6 PR2-
NB_LAN_TX2- 5 PR3-
NB_LAN_TX2+ 4 PR3+
NB_LAN_TX1+ 3 PR2+
NB_LAN_TX0- 2 PR1-
GND 14
NB_LAN_TX0+ 1 PR1+
GND 15
<32> LED_10_GRN# 1 2 11 Green LED-
R1164 150_0402_5%~D
<32> LED_100_ORG# 1 2 13 Orange LED-
R1167 150_0402_5%~D
12 Green-Orange LED+

TYCO_2010019-3

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 33 of 77
5 4 3 2 1
 5 4 3 2 1

Q36 +3.3V_ALW_PCH
USB_GPIO27 1 2 SI2301CDS-T1-GE3_SOT23-3~D +3.3V_ALW_USH
@ R575 0_0402_5%~D +3.3V_ALW +3.3V_ALW_USH
USBP7+ 2 RST_N

S
1 2 1 3 1

D
R576 1.5K_0402_5%~D R577 4.7K_0402_5%~D @ PJP56 U33D

2
+3.3V_ALW_USH 2 OVSTB
R580
PCB Footprint change to BCM5882KFBG_FBGA_196P-NH 1
R578 4.7K_0402_5%~D
2 1
BCM5882

G
2
1 2 PLTRST1#_USH 4.7K_0402_5%~D 1 2 FP_RESET# PAD-OPEN 2x2m~D REF_XIN G14 REFCLK_XTALIN UART_TX_GPIO_1 D4 UART_TX/GPIO1
@ R579 10K_0402_5%~D R582 4.7K_0402_5%~D REF_XOUT F14 C4 UART_RX/GPIO0
REFCLK_XTALOUT UART_RX_GPIO_0
1 2 USH_LPCEN 1 2 SPI_RST B3

UART
1
1@ R583 4.7K_0402_5%~D Q37 U33A R645 4.7K_0402_5%~D UART_CTS_GPIO_2 BT_COEX_STATUS2 FP_RESET# <23>
UART_RTS_GPIO_3 A3 BT_COEX_STATUS2 <42>

CLK
1 2 LPD# SSM3K7002FU_SC70-3~D @ R587 RST_N G1
BCM5882 RST_N

1
@ R584 4.7K_0402_5%~D D 0_0402_5%~D
1 2 IRQ_SERIRQ_R 2USB_GPIO27
<17> USBP7- 1 2 USBP7-_R P5 USBD_DN USBH_DN_0 P7 FP_USBD-
FP_USBD- <23>
R581 4.7K_0402_5%~D G 1 2 USBP7+_R P6 P8 FP_USBD+ L14
D <17> USBP7+ USBD_UP USBH_UP_0 FP_USBD+ <23> NC D
1 2 USH_SMBCLK S USB_GPIO27 N7 P9 USBH_OC0# 2 1 +3.3V_ALW_USH

3
R589 2.2K_0402_5%~D @ R588 USBD_ATTACH_GPIO_27 USBH_OC_0 R590 4.7K_0402_5%~D JTAG_CLK_USH L1 JTAG_TCK
1 2 USH_SMBDAT 0_0402_5%~D P11 JTAG_TDI_USH M1 J1 CONTACTLESS_DET#
R585 2.2K_0402_5%~D USBH_DN_1 JTAG_TDO_USH JTAG_TDI GPIO_4 SCC_CMDVCC_N_R
P12 N1 D2

JTAG
USBH_UP_1 JTAG_TDO GPIO_14
1 2 BCM5882_ALERT# <15> CLK_PCI_TPM
CLK_PCI_TPM P2 LCLK USBH_OC_1 P10 USBH_OC1 JTAG_TMS_USH N2 JTAG_TMS GPIO_15 C2 BCM5882_GPIO15
R592 2.2K_0402_5%~D LPC_LAD0 R593 1 2 0_0402_5%~D N3 JTAG_RST#_USH L3 B1 BT_PRI_STATUS
<14,35,40,41> LPC_LAD0 LAD0_GPIO_20 JTAG_TRSTN GPIO_16 BT_PRI_STATUS <42>
1 2 USH_PWR_STATE# <14,35,40,41> LPC_LAD1
LPC_LAD1 R594 1 2 0_0402_5%~D M4 LAD1_GPIO_21
JTAG_CLK_USH JTCE_USH L2 JTCE
R586 4.7K_0402_5%~D LPC_LAD2 R595 1 2 0_0402_5%~D K5 @ R591
<14,35,40,41> LPC_LAD2 LAD2_GPIO_22
1 2 USBH_OC1 LPC_LAD3 R597 1 2 0_0402_5%~D N4 G3 SPI_CLK 0_0402_5%~D D3 CLKOUT

@
<14,35,40,41> LPC_LAD3 LAD3_GPIO_23 SSP_CLK0_GPIO_6 CLKOUT T144PAD~D

2
R596 4.7K_0402_5%~D LPC_LFRAME# R598 1 2 0_0402_5%~D K4 G2 SPI_CS 1 2 OVSTB E1
<14,35,40,41> LPC_LFRAME# IRQ_SERIRQ_R LFRAME_N_GPIO_18 SSP_FSS0_GPIO_7 SPI_RXD @ R601 OVSTB
<14,35,40,41> IRQ_SERIRQ 1 2 L4 LSERIRQ_GPIO_19 SSP_RXD0_GPIO_8 H1
@ R600 0_0402_5%~D H2 SPI_TXD JTAG_TDI_USH 0_0402_5%~D C1 SPI_RST
CLK_PCI_TPM PLTRST1#_USH SSP_TXD0_GPIO_9 SCANACCMODE RSTOUT_N
1 2 M3 E3

@
<17> PLTRST_USH# LRESET_N_GPIO_17 PAD~D T145 SCANACCMODE

SPI
@ R602 0_0402_5%~D USH_LPCEN M5 C3 BCMGPIO_10

@@@@
T146PAD~D

LPC

1
LPCEN SSP_CLK1_GPIO_10
1

1 2 LPD# N6 B2 BCMGPIO_11 T147PAD~D JTAG_TDO_USH

<35,40> SP_TPM_LPC_EN LPCPD_N_GPIO_24 SSP_FSS1_GPIO_11
@ R603 @ R604 0_0402_5%~D A2 BCMGPIO_12 @ R599 SBOOT E2 J13 POR_MONITOR

@
SSP_RXD1_GPIO_12 T148PAD~D SECURE_BOOT POR_MONITOR T149PAD~D
10_0402_5%~D A1 BCMGPIO_13 T150PAD~D 0_0402_5%~D
USH_SMBCLK SSP_TXD1_GPIO_13
<41> USH_SMBCLK M9 SMBCLK 1 2
USH_SMBDAT L9 USH_TESTMODE D1 K11 SWV

@
<41> USH_SMBDAT T151PAD~D
PCI_TPM_TERM 2

BCM5882_ALERT# SMBDAT JTAG_TMS_USH TESTMODE SWV

<40> BCM5882_ALERT# K9 SMBALERT_N

Smard Card
SC_DET R606 1 2 150_0402_5%~D M7 M11@ R607 2 1 0_0402_5%~D BCM5882_SCCLK
SMB_GPIO_0 SC_CLK

2
BT_COEX_STATUS2 1 2 SMB_GPIO1 N8 M12@ R608 2 1 0_0402_5%~D AUX1UC POR_EXTR J14 C13 PLL_TESTOUT

@
SMB_GPIO_1 SC_FCB POR_EXTR PLL_TESTOUT T153PAD~D
@ R1581 0_0402_5%~D F2 @
@R609
R609 2 1 0_0402_5%~D BCM5882_GPIO25 JTAG_RST#_USH @ R626
SC_SEL5V_GPIO_25
4.7P_0402_50V8C~D

1 2JTAG_RST#_USH SC_SEL18V_GPIO_26 F1 @ R611 2 1 0_0402_5%~D BCM5882_GPIO26 @ R605 1K_0402_5%~D HF_RX_TEST0

R610 1K_0402_5%~D 2 USH_PWR_STATE#_R 0_0402_5%~D @ R621 HF_RX_TEST2

SM BUS
<40> USH_PWR_STATE# 1 L7 WAKEUP_N SC_DET M2@ R614 2 1 0_0402_5%~D BCM5882_SCDET
1 2 USH_LPCEN @ R613 0_0402_5%~D L11@ R616 2 1 0_0402_5%~D BCM5882_IO 1 2 0_0402_5%~D BCM5882KFBG_FBGA196~D

1
SC_IO @ R620 2
2@ R615 4.7K_0402_5%~D 1 2 K1 M10 1 0_0402_5%~D BCM5882_SCRST 1 2
R619 1K_0402_5%~D IDDQ_EN SC_RST JTCE_USH
2 SC_PWR_N14 N14 +SC_PWR 1 2
@ C486

1 2 P1 P14 HF_RX_TEST1 @ R618 0_0402_5%~D

R622 1K_0402_5%~D CORE_PWRDN SC_PWR_P14 SC_TEST
SC_VCC L10 2 1 SCC_CMDVCC_N U33C HF_RX_TEST3
1 2 E12 @ R623 0_0402_5%~D

C
1 R624 1K_0402_5%~D ALDO_PWRDN
@ R625 1 2 0_0402_5%~D RFTAG_VRXP A6
BCM5882 A8 RFREADER_TXP1 C
HF_RFIDTAG_VRX_P HF_TX_P
1 2 REF_XOUT @ R628 1 2 0_0402_5%~D RFTAG_VRXN B6 HF_RFIDTAG_VRX_N HF_TX_N B8 RFREADER_TXN1
@ R627 0_0402_5%~D
C5 A10 RFREADER_RXP
REF_XIN BCM5882KFBG_FBGA196~D HF_RFIDTAG_VTX HF_RX_P RFREADER_RXN
1 2 All XTAL components and traces should be +3.3V_ALW_USH
C487 should be placed HF_RX_N B10
@ R612 10M_0402_5%~D
placed/layout on top layer. The gnd/pwr closer to pin A5
Y4 layer below will provide shielding from 1 2 A5 B9 HF_RX_TEST0
XI XO +1.2V_ALW_AVDD +2.5V_ALW_AVDD C487 0.01U_0402_16V7K~D HF_RFIDTAG_VREF HF_RX_TEST0 HF_RX_TEST1
1 IN OUT 3 27.12Mhz interference which might affect HF_RX_TEST1 C9

4.7K_0402_5%~D

5.1M_0402_5%~D
+1.2V_ALW_AVDD B4 C10 HF_RX_TEST2
cellular certification. HF_RFIDTAG_DVDD1P2 HF_RX_TEST2

2
2 4 E9 HF_RX_TEST3
GND GND HF_RX_TEST3

R629

R630

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

10U_0603_6.3V6M~D
1 1
27.12MHZ_12PF_1N227120CC0B~D +2.5V_ALW_AVDD C6 D7 +RFID_AVDD1P2
C492 C493 +3.3V_ALW_SC +3.3V_ALW +5V_ALW_SC +5V_ALW HF_RFIDTAG_AVDD2P5_C6 HF_TX_AVDD1P2
2 2 1 2 2 1 1 E6 HF_RFIDTAG_AVDD2P5_E6 HF_RX_AVDD1P2 F8

C490

C491
12P_0402_50V8J~D 15P_0402_50V8J~D @ PJP63 @ PJP64 D10

1
2 2 HF_RX_ADC_AVDD1P2

C494

C495

C488

C496

C489
1 2 1 2
F9 +RFID_AVDD2P5
SBOOT 1 1 2 1 1 2 2 HF_RX_AVDD2P5
D6 HF_RFIDTAG_AVSS_D6 HF_TX_AVDD2P5 A7
PAD-OPEN1x1m PAD-OPEN1x1m POR_EXTR B5
Smart Card +3.3V_ALW_SC
HF_RFIDTAG_AVSS_B5
HF_TX_AVDD3P3_D8 D8 +RFID_AVDD3P3

3.3M_0402_5%~D
A4 HF_RFIDTAG_DVSS HF_TX_AVDD3P3_B7 B7

2
+3.3V_ALW_SC

R634
1 2 PORADJ HF_TX_AVSS_C7 C7
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1 2 PORADJ @ R631 4.7K_0402_5%~D 1 1 1 HF_TX_AVSS_C8 C8

R632 4.7K_0402_5%~D 1 2 CLKDIV2 +5V_ALW_SC E7

1
HF_TX_AVSS_E7

1
C497

C498

C499

1 2 CLKDIV1 R633 4.7K_0402_5%~D RFID MODE

R635 4.7K_0402_5%~D R636 A9
2 2 2 HF_RX_AVSS_A9
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

15K_0402_1%~D Component VOLTAGE CURRENT B11

HF_RX_AVSS_B11
2 1
U34 D25-D28 POP NOPOP E8

2
HF_RX_ADC_AVSS1
C500

C501

1 RFREADER_RXP 1 2 RFREADER_RXP_C D9
B PORADJ VDD(intf) C502 0.1U_0402_16V4Z~D L39 HF_RX_ADC_AVSS2 B
18 PORadj VDD 17 R636,R644 3K NOPOP
CLKDIV1 1 2 150NH_0805CS-151EGTS_2%~D
6 CLKDIV1 +3.3V_ALW_USH 3
CLKDIV2 7 16 1 RFREADER_TXP1 1 2 BCM5882KFBG_FBGA196~D
SCC_CMDVCC_N_R CLKDIV2 VDDP
2

390P_0603_50V8G~D

390P_0603_50V8G~D
BCM5882_SCRST 3 15 +SC_VCC 1 1
RSTIN VCC

C503

C504
2 1SCC_CMDVCC_N 5 CMDVCCN
@ D25 DA204U_SOT323-3~D +3.3V_ALW_USH 3
BCM5882_GPIO25 2 14 R638 1 2 0_0402_5%~D SC_RST 1
@ R637 BCM5882_GPIO26 EN_5V/3VN RST R639 22_0402_5%~D SC_CLK
4 13 1 2 +3.3V_ALW_USH 3 2
0_0402_5%~D
AUX1UC
AUX2UC
21
EN_1.8VN

AUX1UC
CLK
I/O
AUX1
9
10
R640
R641
R642
1
1
2
2
100_0402_5%~D
0_0402_5%~D
0_0402_5%~D
SC_IO
SC_C4
SC_C8
2
1
@ D26
DA204U_SOT323-3~D
2 2
RFID
22 11 1 2
@

PAD~D T154 AUX2UC AUX2

BCM5882_IO 20 8 R643 1 2 0_0402_5%~D SC_DET @ D27 DA204U_SOT323-3~D
BCM5882_SCDET I/OUC PRESN JCS1 CONN@
19 OFFN RFREADER_RXN 1 2 RFREADER_RXN_C 1
BCM5882_SCCLK 23 C505 0.1U_0402_16V4Z~D RFREADER_TXN1_PI 1
XTAL1 XTAL2 24 2 2
+SC_VCC
10P_0402_50V8J~D

10P_0402_50V8J~D

2 2 3 3

1
25 12 +3.3V_ALW 4
GPAD GND 4
.47U_0402_6.3V6-K~D

C506

C507

CONN@ R644 RFREADER_TXP1_PI 5 7

JBCM1 15K_0402_1%~D 5 G1
TDA8034HN_HVQFN24_4X4~D 2 <18> CONTACTLESS_DET# 6 6 G2 8
1 1
1 1
C508

UART_RX/GPIO0 2 TYCO_2041084-6~D

2
UART_TX/GPIO1 2 L40
+SC_VCC
SC_VCC should be 3X wide as 1
3 3 G1 5
4 6 150NH_0805CS-151EGTS_2%~D
regular SC trace width to carry 4 G2 RFREADER_TXN1 1 2
~60mA max. current per ISO spec +3.3V_ALW_USH MOLEX_53398-0471~D connectorlist:2041084Ͳ6

390P_0603_50V8G~D

390P_0603_50V8G~D
C1031 and C646 should be p 1 1
10U_0805_10V4Z~D

0.22U_0402_10V6K~D

0.1U_0402_16V4Z~D

C511

C512
laced very close to SC cage pin +3.3V_ALW_USH 3
1 2 Place C508 close 1
@ C509

to U33 pin15 1 2
2 2 Hardware enable for USH TPM:Populate R583,
C510

No Stuff R615.
C513

D28 @
2 1 JSC1 CONN@ +3.3V_ALW_USH DA204U_SOT323-3~D
A 2
Hardware disable for USH TPM:No Stuff A
1
2
1 R583, Populate R615.
2
0.1U_0402_16V4Z~D

SC_RST 3 @ U35 U36

3 SPI_CS SPI_TXD SPI_RXD +3.3V_ALW_USH +2.5V_ALW_AVDD +1.2V_ALW_AVDD
4 4 1 /CS VCC 8 1 D Q 8
SC_CLK 5 SPI_CLK 2 7 L41 BLM18BB100SN1D_2P~D L42 BLM18BB100SN1D_2P~D L43 BLM18BB100SN1D_2P~D
SC_IO 6
5
6
SPI_RXD 2 DO /HOLD 7 SPI_RST
1
@ SPI_RST 3
C
RESET#
VSS
VCC 6 2 1 +RFID_AVDD3P3 2 1 +RFID_AVDD2P5 2 1 +RFID_AVDD1P2 DELL CONFIDENTIAL/PROPRIETARY
C556

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
SC_C4 7 SPI_CS 4 5 BCM5882_GPIO15
7 S# W#
3.3U_0603_10V6K~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D
SC_C8 BCM5882_GPIO15 SPI_CLK
SC_DET
8
9
8 3 /WP CLK 6
2 M45PE16-VMW6TG_SO8W8~D 1 2 1 2 2 1 1 1 1
Compal Electronics, Inc.
9 SPI_TXD Title
1 2 10 10 4 GND DIO 5
C516

C518

C519
C515

C517

C520

C521

C514

C522
R646 11 GND
BCM5882_GPIO15 1 2 SCHEMATICS,MB A6561
1.5K_0402_5%~D W25X32VSSIG_SO8~D R647 4.7K_0402_5%~D 2 1 2 1 1 2 2 2 2 Size Document Number Rev
12 GND B
FCI_10089709-010010LF~D 401931
Date: Thursday, January 13, 2011 Sheet 34 of 77
5 4 3 2 1
 5 4 3 2 1

U33B

H14
BCM5882
+1.2V_ALW_PLL AVDD_1P2I_REF
+1.2V_ALW_AVDD A11 AVDD_1P2O_A11
A12 AVDD_1P2O_A12 AVSS_LDO12 C11
+2.5V_ALW_AVDD
H13 AVDD_2P5I AVSS_LDO25_B13 B13
E10 AVDD_2P5O_E10 AVSS_LDO25_C12 C12
+3.3V_ALW_USH E11 AVDD_2P5O_E11
AVSS_PLL B14
A13 AVDD25_LDO12_A13

4.7U_0603_6.3V6K~D
B12 AVDD25_LDO12_B12 AVSS_REF F13
D D

1 PLL_AVSS D12
+1.2V_ALW_PLL A14 AVDD25_PLL_A14

C523
PLL_DVSS E13
+3.3V_ALW_USH 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
1 1 1 D11 AVDD33_LDO25

C524

C525

C526
POR_AVSS G13

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
+SC_PWR P13 OTP_PWR
2 2 2
2 2 2 2 2 2 2 1

C534

1U_0402_6.3V6K~D

0.1U_0402_16V4Z~D
C527

C528

C529

C530

C531

C532

C533
1 2 +1.2V_ALW_PLL D14 PLL_AVDD_1P2I
E14 PLL_AVDD_1P2O
1 1 1 1 1 1 1 2

C1161

C535
C14 PLL_DVDD_1P2I VSSC_F4 F4
VSSC_F5 F5
2 1
D13 VDDC_D13 VSSC_F6 F6
+VDDC_5882 F3 F7
VDDC_F3 VSSC_F7
J4 VDDC_J4 VSSC_F10 F10
J5 VDDC_J5 VSSC_F11 F11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
J6 VDDC_J6 VSSC_F12 F12
2 2 2 2 2 2 2 J7 VDDC_J7 VSSC_G5 G5
J8 VDDC_J8 VSSC_G6 G6

C536

C537

C538

C539

C540

C541

C542
J10 VDDC_J10 VSSC_G7 G7
+VDDC_5882 J11 G8
1 1 1 1 1 1 1 VDDC_J11 VSSC_G8
K7 VDDC_K7 VSSC_G9 G9
+3.3V_ALW_USH K8 G10
VDDC_K8 VSSC_G10
VSSC_G11 G11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
E4 VDDO_33_E4 VSSC_G12 G12
2 2 2 2 J2 VDDO_33_J2 VSSC_H5 H5
K3 VDDO_33_K3 VSSC_H6 H6

C543

C544

C545

C546
L8 VDDO_33_L8 VSSC_H7 H7
C C
N10 VDDO_33_N10 VSSC_H8 H8
1 1 1 1
VSSC_H9 H9
G4 VDDO_33CORE_G4 VSSC_H10 H10
H3 VDDO_33CORE_H3 VSSC_H11 H11
H4 VDDO_33CORE_H4 VSSC_H12 H12
J3 VDDO_33CORE_J3 VSSC_J9 J9
VSSC_J12 J12
M13 VDDO_33SC_M13 VSSC_K2 K2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
N13 VDDO_33SC_N13 VSSC_K6 K6
2 2 1 VSSC_K13 K13
L6 VDDO_LPC_L6 VSSC_K14 K14

C547

C548

C549
M6 VDDO_LPC_M6 VSSC_L5 L5
VSSC_M8 M8
1 1 2
VSSC_M14 M14
K10 VDDO_SC_K10 VSSC_N9 N9
K12 VDDO_SC_K12 VSSC_N11 N11
L12 VDDO_SC_L12 VSSC_N12 N12
L13 VDDO_SC_L13 VSSC_P3 P3
VSSC_P4 P4
D5 VDDO_VAR_D5
E5 VDDO_VAR_E5
CLK_PCI_TPM_CHA
LOW:Power Down Mode N5 VESD
1

High:Working Mode
@
RE5 +3.3V_RUN 4@ +3.3V_RUN_TCM BCM5882KFBG_FBGA196~D
33_0402_5%~D China TCM: NationZ & Jetway co-lay PJP61
1 2
2

1 +3.3V_RUN_TCM
@ PAD-OPEN1x1m
CE3 4@ U37
B 27P_0402_50V8J~D B
2
10
VDD_0
19
USHBCM5882andChinaTCMZ8H172TOption
VDD_1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
VDD_2 24 PART/PIN RefDes TCMEnable TPMEnable ALLTPM/TCMDisable
4@ C551

4@ C552

4@ C553

4@ C550
2 2 2 1

1 2 C_TPM_LPC_EN 28
TCMcircuit All4@ POP @ @
<34,40> SP_TPM_LPC_EN LPCPD#
4@ R650 1 2 0_0402_5%~D LPC_LAD0_R 26 11
<14,34,40,41> LPC_LAD0
4@ R649 1 2 0_0402_5%~D LPC_LAD1_R 23
LAD0 GND_11
18
1 1 1 2 PUR583 @ POP @
<14,34,40,41> LPC_LAD1
4@ R648 1 2 0_0402_5%~D LPC_LAD2_R 20
LAD1 GND_18
25
USH_LPCEN
<14,34,40,41> LPC_LAD2
4@ R651 1 2 0_0402_5%~D LPC_LAD3_R 17
LAD2 GND_25
4
PDR615 POP @ @
<14,34,40,41> LPC_LAD3 LAD3 GND_4
4@ R652 0_0402_5%~D
SIO5028Ͳ>SP_TPM_LPC_EN PUR772 @ @ @
+3.3V_RUN_TCM
21 5 JETWAY_PIN5 PURH268 @ POP POP
<15> CLK_PCI_TPM_CHA
1 2 LPC_LFRAME#_R 22
LCLK NC_5
12
PCHGPIO39Ͳ>TPM_ID1
<14,34,40,41> LPC_LFRAME#
4@ R653 1 2 0_0402_5%~D PCI_RST#_R 16
LFRAME# NC_12
13 JETWAY_CLK14M PDRH271 POP @ @
<14,17,37,38,40,41> PCH_PLTRST#_EC LRESET# NC_13 JETWAY_CLK14M <15>
4@ R654 0_0402_5%~D 27
<14,34,40,41> IRQ_SERIRQ
1 2 CLKRUN#_R 15
SERIRQ
1
PURH267 @ POP @
1
<16,40,41> CLKRUN#
2 4@ R655 0_0402_5%~D 7
CLKRUN# NC_1
2
PCHGPIO38Ͳ>TPM_ID0
@R656
@ R656 4.7K_0402_5%~D TCM_BA1 3
PP NC_2
6
PDRH270 POP @ POP
TCM_BA0 BA_1 NC_6
9 BA_0 NC_8 8
14 JETWAY_CLK14M
+3.3V_RUN_TCM NC_P
1

1
4@ @
C554 RE6
1

1U_0402_6.3V6K~D 33_0402_5%~D
@ R657
@R657 @R658
@ R658 SSX44-B_TSSOP28~D 2 JETWAY_PIN5
2

10K_0402_5%~D 10K_0402_5%~D
1 2
@
2

A CE4 @C555
@C555 A
TCM_BA0
TCM Vender POP 27P_0402_50V8J~D 0.1U_0402_16V4Z~D
TCM_BA1 2 1
NationZ R660, R659, C554, C550
Jetway C555, RH315 DELL CONFIDENTIAL/PROPRIETARY
1

4@ R659 R660 4@
1K_0402_5%~D 1K_0402_5%~D Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
SCHEMATICS,MB A6561
2

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 35 of 77
5 4 3 2 1
 A B C D E

NOTE1:
THESE 1394 SIGNALS ARE HIGH SPEED
DIFFERENTIAL PAIRS AND MUST BE KEPT EQUAL
LENGTH WITH A DIFFERENTIAL IMPEDANCE (Z0)
OF 110 OHMS.

NOTE2:
If used OZ600RJ1-A R680 need change to 5.1K ohm_1%.
If used OZ600RJ1-B R680 need change to 191 ohm _1%.
+1.5V_RUN @ R678 1 2 0_0402_5%~D
NOTE3:
If used OZ600RJ1-A POP R679 JUMP +3.3V_RUN. +3.3V_RUN 1 2 +MMI_VCC_IN +SKT_VCC
@ R679 0_0402_5%~D

0.1U_0402_10V7K~D
If used OZ600RJ1-B CAN POP R679 or R678 JUMP +3.3V_RUN or +1.5V_RUN. 1 1
1.5V_RUN for POWER SAVING MODE. 1 1

C576
C573 C574 C575
1 1
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 2 2
2 2

+3.3V_RUN
@ PJP59 +MMI_DVDD
1 2 +3.3V_RUN_OZ600 1 1

0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
PAD-OPEN1x1m L47 C577 C578
1 1 1 2 +MMI_1394_VCCH 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D
2 2

C579

C580
BLM18AG601SN1D_0603~D

BLM18AG601SN1D_0603~D

0.1U_0402_10V7K~D
2 2 +MMI_PE_VDDH
1 2
L46 1

C582
+MMI_AVDD

0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
1 1 1 1

C583
C581 C1184
2

C584
0.1U_0402_10V7K~D 0.01U_0402_16V7K~D
2 2 2 2

28
33

34

24

10

35

11
42
1

9
U39

IO_VOUT
PE_VDDH

1394_VDDH
1394_VDDH

3.3VDDH

MMI_VCC_IN

VDDH

DVDD
DVDD

AVDD
L45 @ SD/MMC_CLK_R 2 1 SD/MMC_CLK
CPB- 4 3 TPB- RE7 33_0402_5%~D
4 3

1
2 1 4 25 +3.3V_RUN_CARD @
CPB+ 1 TPB+ R680 191_0402_1%~D PE_REXT MMI_VCC_OUT RE8
1 2 2
33_0402_5%~D
DLW21SN900HQ2L_0805_4P~D 1 2 PCIE_PTX_MMIRX_N6_C 5
<15> PCIE_PTX_MMIRX_N6

2
C586 0.1U_0402_10V7K~D PE_RXM
COMMON MODE COKE COIL IS OPTIONAL FOR EMI PURPOSE. 6 PE_RXP XD_CD# 15
1 2 PCIE_PTX_MMIRX_P6_C 16 MS_CD# 1
<15> PCIE_PTX_MMIRX_P6 MS_CD#
L48 @ C587 0.1U_0402_10V7K~D 17 SD/MMCCD# @
CPA- TPA- PCIE_PRX_MMITX_P6_C SD_CD# CE5
4 4 3 3 <15> PCIE_PRX_MMITX_P6 2 1 7 PE_TXP
C588 0.1U_0402_10V7K~D 27P_0402_50V8J~D
2
2 2
CPA+ 1 2 TPA+ 2 1 PCIE_PRX_MMITX_N6_C 8 14 SDWP
1 2 <15> PCIE_PRX_MMITX_N6 C585 0.1U_0402_10V7K~D PE_TXM SD_WPI/XD_WPO
XD_RE# 13
DLW21SN900HQ2L_0805_4P~D 36 SD/MMC_CLK_R
MMI_CLK/XD_CE#
<15> CLK_PCIE_MMI# 2 PE_REFCLKM XD_WE# 12
3 37 SD/MMCCMD_R 1 2 SD/MMCCMD
<15> CLK_PCIE_MMI PE_REFCLKP MMI_BS/CMD/ALE R1206 33_0402_5%~D
<17> PLTRST_MMI# 18 PE_RST#

<15> MMICLK_REQ# 22 MULTI_IO2

38 SD/MMCDAT7_R 1 2 SD/MMCDAT7
MMI_D7 SD/MMCDAT6_R R1198 33_0402_5%~D SD/MMCDAT6
MMI_D6 39 1 2
40 SD/MMCDAT5_R R1199 1 2 33_0402_5%~D SD/MMCDAT5
J1394 CONN@ MMI_D5 SD/MMCDAT4_R R1200 33_0402_5%~D SD/MMCDAT4
MMI_D4 41 1 2
1 CPB- 1 2 TPB- 26 43 SD/MMCDAT3_R R1201 1 2 33_0402_5%~D SD/MMCDAT3
TPB- CPB+@ R1055 TPB+ 1394_TPBN MMI_D3 MS_XD_D2_R MS_XD_D2
TPB+ 2 1 2 0_0402_5%~D 27 1394_TPBP MS_XD_D2 44 R1202 1 2 33_0402_5%~D
5 3 CPA-@ R1056 1 2 0_0402_5%~D TPA- 29 45 SD/MMCDAT2_R R1585 1 2 33_0402_5%~D SD/MMCDAT2
GND TPA- CPA+@ R1057 TPA+ 1394_TPAN SD_D2/XD_RB# MS_XD_D1_R MS_XD_D1
6 GND TPA+ 4 1 2 0_0402_5%~D 30 1394_TPAP MS_XD_D1 46 R1203 1 2 33_0402_5%~D
@ R1058 0_0402_5%~D 31 47 SD/MMCDAT1_R R1586 1 2 33_0402_5%~D SD/MMCDAT1
TYCO_2010017-1 1394_TPBIAS SD_D1/XD_CLE SD/MMCDAT0_R R1204 33_0402_5%~D SD/MMCDAT0
53.6_0402_1%~D

53.6_0402_1%~D

53.6_0402_1%~D

53.6_0402_1%~D

MMI_D0 48 1 2
R1205 33_0402_5%~D
1

1394_XI 19
1394_XI
R683

R684

R685

R686

1394_XO 20
1394_XO

1 2 +1394_REF 32
2

R687 5.9K_0402_1%~D 1394_REF

MULTI_IO1 23
270P_0402_50V7K~D
5.11K_0402_1%~D

1U_0402_6.3V6K~D
1

21 +3.3V_RUN_CARD
1 1 1394_CPS
R690

GPAD
C589

C590

JSD1 CONN@
7 VDD
2 2
9 44
2

OZ600RJ1LN-B_QFN48_6X6~D VCC VCC

49

0.1U_0402_16V4Z~D

4.7U_0603_10V6K~D
1 1 SD/MMCDAT0 22
3
SD/MMCDAT1 DAT0 3
23 DAT1 CD 27

C570

C572
SD/MMCDAT2 1 28
SD/MMCDAT3 DAT2 R/-B
2 CD/DAT3 -RE 29
PLACE THESE PARTS NEAR OZ600RJ1 NOTE7: 2 2 SD/MMCDAT4 3 DAT4 -CE 30
TERMINAL 49 (GND) IS THE EXPOSED PAD SD/MMCDAT5 5 31
SD/MMCDAT6 DAT5 CLE
ON THE BOTTOM OF PACKAGE AND MUST BE 19 DAT6 ALE 32
SOLDERED TO GND OF PCB. SD/MMCDAT7 21 33
C591 1 1394_XI DAT7 -WE
2 6.8P_0402_50V8D~D -WP 34
SD/MMCCMD 4 CMD
1

SD/MMC_CLK 18
Y5 CLK
24 COM(SW) D0 36
24.576MHZ_12PF_1YG24576CE1C~D SD/MMCCD# 25 37
SDWP CD(SW) D1
45 38
2

C592 1 1394_XO WP(SW) D2

2 6.8P_0402_50V8D~D R1060 1 2 0_0402_5%~D D3 39
SD/MMCDAT0 14 40
MS_XD_D1 DATA0 D4
15 DATA1 D5 41
MS_XD_D2 13 42
SD/MMCDAT3 DATA2 D6
11 DATA3 D7 43

SD/MMC_CLK 10
MS_CD# SCLK
12 INS GND 26
SD/MMCCMD 16 35
BS GND
6 VSS GND1 46
8 VSS GND2 47
17 VSS GND3 48
20 VSS GND4 49

T-SOL_152-1300302601_NR

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 36 of 77
A B C D E
 5 4 3 2 1

+3.3V_RUN +3.3V_PCIE_WWAN +3.3V_ALW_PCH

PCIE_MCARD1_DET# 1 2
1 2 R692 100K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D
USB_MCARD2_DET# 2 1 @ R693 0_0402_5%~D

1
@ R1159

@ R1160
R694 100K_0402_5%~D
1 2 WLAN_RADIO_DIS#_R
<40> WLAN_RADIO_DIS#
D31
+3.3V_PCIE_WWAN RB751S40T1_SOD523-2~D

2
2 1 WWAN_SMBCLK

PCIE_MCARD2_DET# 1 2
<7,12,13,14,15,28> DDR_XDP_WAN_SMBCLK

<7,12,13,14,15,28> DDR_XDP_WAN_SMBDAT
@R1157
@ R1157
2 1
0_0402_5%~D
WWAN_SMBDAT
Mini WLAN/WIMAX H=4
D R695 100K_0402_5%~D @R1158
@ R1158 0_0402_5%~D D
USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET# +3.3V_RUN
@ R698 0_0402_5%~D

USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET#
Mini WWAN/GPS/LTE/UWB H=5.2 +3.3V_WLAN +3.3V_WLAN

@ R697 0_0402_5%~D JMINI2 +1.5V_RUN PCIE_MCARD1_DET# 1 2

+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN <29,38,40> PCIE_WAKE# PCIE_WAKE# 1 2 @ R699 100K_0402_5%~D
JMINI1 COEX2_WLAN_ACTIVE 1 2 USB_MCARD1_DET#
<42> COEX2_WLAN_ACTIVE 1 2 3 3 4 4 1 2
1 2 COEX1_BT_ACTIVE @ R7001 2 0_0402_5%~D 5 6 R701 100K_0402_5%~D
1 2 <42> COEX1_BT_ACTIVE @ R702 0_0402_5%~D 5 6
3 3 4 4 <15> MINI2CLK_REQ# 7 7 8 8
5 5 6 6 +1.5V_RUN 9 9 10 10 1 2
MINI1CLK_REQ# 7 8 +SIM_PWR 11 12
<15> MINI1CLK_REQ# 7 8 <15> CLK_PCIE_MINI2# 11 12
9 10 UIM_DATA 13 14 MSDATA C595 4700P_0402_25V7K~D
9 10 <15> CLK_PCIE_MINI2 13 14
CLK_PCIE_MINI1# 11 12 UIM_CLK 15 16
<15> CLK_PCIE_MINI1# 11 12 15 16 HOST_DEBUG_TX <41>
CLK_PCIE_MINI1 13 14 UIM_RESET
<15> CLK_PCIE_MINI1 13 14 UIM_VPP
15 15 16 16
<41> HOST_DEBUG_RX 17 17 18 18
19 20 WLAN_RADIO_DIS#_R
<41> MSCLK 19 20
17 17 18 18 21 21 22 22 2 1 PCH_PLTRST#_EC
19 20 WWAN_RADIO_DIS# PCIE_PRX_WLANTX_N2 23 24 @ R703 0_0402_5%~D
19 20 WWAN_RADIO_DIS# <40> <15> PCIE_PRX_WLANTX_N2 23 24
21 22 1 2 PCIE_PRX_WLANTX_P2 25 26
21 22 PCH_PLTRST#_EC <14,17,35,38,40,41> <15> PCIE_PRX_WLANTX_P2 25 26
PCIE_PRX_WANTX_N1 23 24 @R704
@ R704 0_0402_5%~D 27 28
<15> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 23 24 0.1U_0402_10V7K~D 27 28
<15> PCIE_PRX_WANTX_P1 25 25 26 26 29 29 30 30
27 28 C596 1 2 PCIE_PTX_WLANRX_N2_C 31 32
27 28 <15> PCIE_PTX_WLANRX_N2 31 32
0.1U_0402_10V7K~D 29 30 WWAN_SMBCLK C598 1 2 PCIE_PTX_WLANRX_P2_C 33 34
29 30 <15> PCIE_PTX_WLANRX_P2 33 34
<15> PCIE_PTX_WANRX_N1
C597 1 2PCIE_PTX_WANRX_N1_C 31 31 32 32 WWAN_SMBDAT 0.1U_0402_10V7K~D 35 35 36 36 USBP4-
USBP4- <17>
C599 1 2PCIE_PTX_WANRX_P1_C 33 34 PCIE_MCARD1_DET# 37 38 USBP4+
<15> PCIE_PTX_WANRX_P1 33 34 <18> PCIE_MCARD1_DET# 37 38 USBP4+ <17>
0.1U_0402_10V7K~D 35 36 USBP5- COEX2_WLAN_ACTIVE 39 40 USB_MCARD1_DET#
35 36 USBP5- <17> 39 40 USB_MCARD1_DET# <14,18>
<17> PCIE_MCARD2_DET#_R 1 2 PCIE_MCARD2_DET# 37 37 38 38 USBP5+
USBP5+ <17> 41 41 42 42 WIMAX_LED#
@R725
@ R725 0_0402_5%~D 39 40 USB_MCARD2_DET# 1 43 44 WLAN_LED#
39 40 USB_MCARD2_DET# <18> 43 44
41 42 LED_WWAN_OUT# 45 46
41 42 <15> PCH_CL_CLK1 45 46
43 44 @C600
@ C600 47 48 1 2 MSDATA
C 43 44 <15> PCH_CL_DATA1 47 48 MSDATA <41> C
45 46 33P_0402_50V8J~D 1 2 49 50 @ R706 0_0402_5%~D
45 46 2 <15> PCH_CL_RST1# 49 50
47 48 @ R707 0_0402_5%~D 51 52
+3.3V_PCIE_WWAN 47 48 51 52 +3.3V_WLAN
49 49 50 50 53 G1 G2 54
51 51 52 52
53 G1 G2 54
0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

33P_0402_50V8J~D

22U_0805_6.3VAM~D

33P_0402_50V8J~D

330U_D2E_6.3VM_R25~D

330U_D2E_6.3VM_R25~D

LOTES_AAA-PCI-047-P10-A
+1.5V_RUN +3.3V_WLAN CONN@
1 1

100K_0402_5%~D

100K_0402_5%~D
1 1 1 1 1 @ LOTES_AAA-PCI-047-P10-A

2
+ + CONN@
C610

C611

C612

C613

C614

C615

C1176

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D

R718

R705
2 2 2 2 2 2 2 +3.3V_PCIE_WWAN 1 1 1 1 1 1 1 1

5
DMN66D0LDW-7_SOT363-6~D

@ C603

1
C601

C602

C604

C605

C606

C607

C608
WIMAX_LED# 4 3 WIRELESS_LED#
2 2 2 2 2 2 2 2
Q124B
100K_0402_5%~D
2

2
DMN66D0LDW-7_SOT363-6~D
R719

WLAN_LED# 1 6
2

+1.5V_RUN
G

Q124A
1

LED_WWAN_OUT# 3 1 WIRELESS_LED# <40,44>

S

D
33P_0402_50V8J~D

0.047U_0402_16V4Z~D

Q77
1 1 SSM3K7002FU_SC70-3~D 1/2 Minicard Flash Card H=4
C593

C594

+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
USB_MCARD3_DET# 1 2 PCIE_MCARD3_DET#
2 2 JMINI3 @R708
@ R708 0_0402_5%~D
B
Primary Power Aux Power B
PWR Voltage PCIE_WAKE# 1 2
COEX2_WLAN_ACTIVE 1 2
1 2 3 4
Rail Tolerance Peak Normal Normal @ R709 0_0402_5%~D 5
3 4
6 +1.5V_RUN
MINI3CLK_REQ# 5 6
<15> MINI3CLK_REQ# 7 7 8 8
9 10 Confirm with DELL about UWB
+SIM_PWR
SIM Card Push-Push +3.3V +-9% 1000 750 <15> CLK_PCIE_MINI3#
<15> CLK_PCIE_MINI3
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
11
13
9
11
13
10
12
14
12
14
250 (Wake enable) 15 15 16 16
+3.3Vaux +-9% 330 250 5 (Not wake enable)
JSIM1 CONN@
1 VCC GND 5 17 17 18 18
UIM_RESET 2 6 UIM_VPP +1.5V +-5% 500 375 NA 19 20
UIM_CLK RST VPP UIM_DATA 19 20
3 CLK I/O 7 21 21 22 22 2 1 PCH_PLTRST#_EC
4 8 PCIE_PRX_WPANTX_N5 23 24 R710 @ 0_0402_5%~D
NC NC <15> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 23 24
GND 9 <15> PCIE_PRX_WPANTX_P5 25 25 26 26
GND 10 27 27 28 28
1 0.1U_0402_10V7K~D 29 30
MOLEX_475531001~D C617 1 PCIE_PTX_WPANRX_N5_C 29 30
<15> PCIE_PTX_WPANRX_N5 2 31 31 32 32
C616 C618 1 PCIE_PTX_WPANRX_P5_C
2 33 34
1U_0402_6.3V6K~D <15> PCIE_PTX_WPANRX_P5 33 34
0.1U_0402_10V7K~D 35 36 USBP6-
2 35 36 USBP6- <17>
PCIE_MCARD3_DET# 37 38 USBP6+
<18> PCIE_MCARD3_DET# 37 38 USBP6+ <17>
39 40 USB_MCARD3_DET#
39 40
+3.3V_RUN 1 2 41 41 42 42
U40 @ R711 100K_0402_5%~D 43 44 2 1 +3.3V_ALW_PCH
+1.5V_RUN +3.3V_PCIE_FLASH 43 44 @ R712 100K_0402_5%~D
45 45 46 46
47 47 48 48
UIM_RESET 1 6 UIM_VPP 49 50 WPAN Noise
49 50
51 51 52 52
0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D

53 54 USB_MCARD3_DET#
G1 G2
2 5 +SIM_PWR
1 1 1 1 1 1 1 1 1
@C621
@

LOTES_AAA-PCI-047-P10-A @
C619

C620

C621

C622

C623

C624

C625

C626

A UIM_CLK UIM_DATA CONN@ C627 A

3 4
4700P_0402_25V7K~D
2 2 2 2 2 2 2 2 2
33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

1 1 1 1
@C628
@

@C629
@

@C630
@

@C631
@

SRV05-4.TCT_SOT23-6~D
DELL CONFIDENTIAL/PROPRIETARY
C628

C629

C630

C631

2 2 2 2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 37 of 77
5 4 3 2 1
 5 4 3 2 1

PowerControlforMinicard1 ExpressCardPWRS/W
+15V_ALW +3.3V_ALW +3.3V_WLAN +1.5V_RUN +3.3V_RUN +3.3V_SUS

D +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD D

D
100K_0402_5%~D
6

S
1
100K_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
5 4

R714
2

R713

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
1 Q38 1 1 1
SI3456DDV-T1-GE3_TSOP6~D

C635

C634

C633
1 1 1 1 1 1

3
R715
2
2 2 2

DMN66D0LDW-7_SOT363-6~D

C642

C643

C639

C641

C636

C638
20K_0402_5%~D

4700P_0402_25V7K~D
2 2 2 2 2 2
1

2
Q39B

C632
5 U41
17 AUXIN AUXOUT 15
6

Q39A 2
4 2 3.3VIN 3.3VOUT 3
DMN66D0LDW-7_SOT363-6~D 12 11
1.5VIN 1.5VOUT
2 20 8 CARD_RESET#
<40> AUX_EN_WOWL SHDN# PERST#
<11,40,43,56,64> RUN_ON 1 2 EXPRCRD_STBY_R# 1 STBY# CPPE# 10 EXPRCRD_CPPE#
1

<14,17,35,37,40,41> PCH_PLTRST#_EC @ R717 0_0402_5%~D

PCH_PLTRST#_EC 6 9 CPUSB#
1

SYSRST# CPUSB#
19 OC#
R716
100K_0402_5%~D +3.3V_RUN 4 NC
+3.3V_CARD 5 18
2

NC RCLKEN
+1.5V_CARD 13 NC
+1.5V_RUN 14 NC GND 7
16 NC PAD 21

TPS2231MRGPR-2_QFN20_4X4~D

C PowerControlforMinicard2 C

+3.3V_ALW +3.3V_PCIE_WWAN

+15V_ALW Q40
SI3456DDV-T1-GE3_TSOP6~D
100K_0402_5%~D

@ R720
D

6 0_0805_5%~D
S
1
100K_0402_5%~D

5 4 1 2 +3.3V_RUN
1

R722

2 +1.5V_CARD: Max. 650mA, Average 500mA

R721

1
1
ExpressCardBTBConn. +3.3V_CARD: Max. 1300mA, Average 1000mA
G

R723
2

1K_0402_5%~D
2

DMN66D0LDW-7_SOT363-6~D
3

4700P_0402_25V7K~D

1
+3.3V_SUS
Q41B

+1.5V_CARD
1

D
C644

SSM3K7002FU_SC70-3~D

MCARD_WWAN_PWREN# 5
Q73

2 MCARD_WWAN_PWREN#
6

Q41A 2 G
4

2.2K_0402_5%~D

2.2K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D S 1
3

1
R731

R732
2 1 2 C645
<40> MCARD_WWAN_PWREN 0.1U_0402_16V4Z~D
@R724
@ R724 0_0402_5%~D
1

2
1

R726

2
100K_0402_5%~D 1 2
@ R727
@R727 0_0402_5%~D
1 1 JEXP1 CONN@
<17> USBP10- 2 2
2

1 GND1
USBP10_D- 2
B USBP10_D+ USB_D- B
<17> USBP10+ 4 4 3 3 3 USB_D+
CPUSB# 4
PowerControlforMinicard3 L49 DLW21SN900SQ2_0805~D

CARD_SMBCLK
5
6
CPUSB#
RESERVED
RESERVED
<41> CARD_SMBCLK 7 SMB_CLK
CARD_SMBDAT 8
<41> CARD_SMBDAT SMB_DAT
9 +1.5V
10 +1.5V
+15V_ALW +3.3V_ALW Q42 +3.3V_PCIE_FLASH 11
SI3456DDV-T1-GE3_TSOP6~D <29,37,40> PCIE_WAKE# WAKE#
+3.3V_CARDAUX 12 +3.3VAUX
100K_0402_5%~D

CARD_RESET# 13 PERST#
D

6 14
S

+3.3V_CARD +3.3V
1
100K_0402_5%~D

5 4 1 15 +3.3V
1

R729

2 <15> EXPCLK_REQ# 16 CLKREQ#

R728

1 C646 EXPRCRD_CPPE# 17 CPPE#

1

0.1U_0402_16V4Z~D 18
G

2 <15> CLK_PCIE_EXP# REFCLK-

R730 1 19
<15> CLK_PCIE_EXP
2

20K_0402_5%~D REFCLK+
20
2

GND
DMN66D0LDW-7_SOT363-6~D

C649 <15> PCIE_PRX_EXPTX_N3 21 PER_N0

3

4700P_0402_25V7K~D

0.1U_0402_16V4Z~D <15> PCIE_PRX_EXPTX_P3 22

2

2 C647 0.1U_0402_10V7K~D PER_P0

1 23 GND
Q43B

<15> PCIE_PTX_EXPRX_N3 1 2 PCIE_PTX_EXPRX_N3_C 24 PET_N0

C650

5 <15> PCIE_PTX_EXPRX_P3 1 2 PCIE_PTX_EXPRX_P3_C 25 PET_P0

26 GND
6

Q43A 2 C648 0.1U_0402_10V7K~D

4

DMN66D0LDW-7_SOT363-6~D 27 GND
28 GND
<40> MCARD_MISC_PWREN 2 29 GND
30 GND
1

T-SOL_5421005002000-9_NR
R733
A 100K_0402_5%~D A
2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 38 of 77
5 4 3 2 1
 2 1

CONN@

JDOCK1

DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <40,63>
<32> DOCK_LOM_SPD10LED_GRN# 3 3 4 4 DOCK_LOM_SPD100LED_ORG# <32>
DPD_CA_DET 5 6 DPC_CA_DET
<27> DPD_CA_DET 5 6 DPC_CA_DET <27> DPC_GPU_HPD
7 7 8 8
C690 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P0_C 9 10 DPC_GPU_LANE_P0_C C691 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_P0 9 10 DPC_GPU_LANE_P0 <48>
C679 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_N0_C 11 12 DPC_GPU_LANE_N0_C C680 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_N0 11 12 DPC_GPU_LANE_N0 <48>
13 13 14 14

2
C681 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P1_C 15 16 DPC_GPU_LANE_P1_C C682 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_P1 15 16 DPC_GPU_LANE_P1 <48>
C683 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_N1_C 17 18 DPC_GPU_LANE_N1_C C684 2 1 0.1U_0402_10V7K~D R758
<48> DPD_GPU_LANE_N1 17 18 DPC_GPU_LANE_N1 <48>
19 19 20 20 100K_0402_1%~D
C692 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P2_C 21 22 DPC_GPU_LANE_P2_C C693 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_P2 21 22 DPC_GPU_LANE_P2 <48>
C685 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_N2_C 23 24 DPC_GPU_LANE_N2_C C686 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_N2

1
23 24 DPC_GPU_LANE_N2 <48>
25 25 26 26
C687 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P3_C 27 28 DPC_GPU_LANE_P3_C C688 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_P3 27 28 DPC_GPU_LANE_P3 <48>
C689 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_N3_C 29 30 DPC_GPU_LANE_N3_C C694 2 1 0.1U_0402_10V7K~D
<48> DPD_GPU_LANE_N3 29 30 DPC_GPU_LANE_N3 <48>
31 31 32 32
DPD_DOCK_AUX 33 34 DPC_DOCK_AUX
<27> DPD_DOCK_AUX 33 34 DPC_DOCK_AUX <27>
DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX#
<27> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <27>
37 37 38 38
DPD_GPU_HPD DPD_GPU_HPD 39 40 DPC_GPU_HPD
<47> DPD_GPU_HPD 39 40 DPC_GPU_HPD <47>
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <63>

0.033U_0402_16V7K~D

0.033U_0402_16V7K~D
1 43 43 44 44 1
BLUE_DOCK 45 46
<25> BLUE_DOCK 45 46 DAT_DDC2_DOCK <25>
2

C695

C696
B B
47 47 48 48 CLK_DDC2_DOCK <25>
R757 49 50 Close to DOCK
2 49 50 2
100K_0402_1%~D 51 51 52 52 Its for Enhance ESD on dock issue.
@ RED_DOCK 53 54 SATA_PRX_DKTX_P5 2 1 @
<25> RED_DOCK 53 54 SATA_PRX_DKTX_P5_C <14>
Close to DOCK 55 56 SATA_PRX_DKTX_N5 C697 2 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C <14>
1

55 56 C698 0.01U_0402_16V7K~D
Its for Enhance ESD on dock issue. 57 57 58 58
GREEN_DOCK 59 60 SATA_PTX_DKRX_P5 1 2
<25> GREEN_DOCK 59 60 SATA_PTX_DKRX_P5_C <14>
61 62 SATA_PTX_DKRX_N5 C699 1 2 0.01U_0402_16V7K~D
61 62 C700 0.01U_0402_16V7K~D SATA_PTX_DKRX_N5_C <14>
63 63 64 64
<25> HSYNC_DOCK 65 65 66 66 USBP8+ <17>
<25> VSYNC_DOCK 67 67 68 68 USBP8- <17>
69 69 70 70
<41> CLK_MSE 71 71 72 72 USBP9+ <17>
<41> DAT_MSE 73 73 74 74 USBP9- <17>
75 75 76 76
<30> DAI_BCLK# 77 77 78 78 CLK_KBD <41>
<30> DAI_LRCK# 79 79 80 80 DAT_KBD <41>
81 81 82 82
<30> DAI_DI 83 83 84 84
<30> DAI_DO# 85 85 86 86
87 87 88 88
<30> DAI_12MHZ# 89 89 90 90
91 91 92 92
93 93 94 94
95 95 96 96
<40> D_LAD0 97 97 98 98 BREATH_LED# <41,44>
<40> D_LAD1 99 99 100 100 DOCK_LOM_ACTLED_YEL# <32>
101 101 102 102
<40> D_LAD2 103 103 104 104 DOCK_LOM_TRD0+ <32>
<40> D_LAD3 105 105 106 106 DOCK_LOM_TRD0- <32>
107 107 108 108
109 110 +3.3V_ALW
<40> D_LFRAME# 109 110 DOCK_LOM_TRD1+ <32> +LOM_VCT
<40> D_CLKRUN# 111 111 112 112 DOCK_LOM_TRD1- <32>
113 113 114 114
115 116 1 DOCK_DET# 1 2
<40> D_SERIRQ 115 116
117 118 +LOM_VCT R755 100K_0402_5%~D
<40> D_DLDRQ1# 117 118
119 120 C701
119 120 1U_0402_6.3V6K~D
<17> CLK_PCI_DOCK 121 121 122 122 DOCK_LOM_TRD2+ <32> 2
123 123 124 124 DOCK_LOM_TRD2- <32>
125 125 126 126
<41> DOCK_SMB_CLK 127 127 128 128 DOCK_LOM_TRD3+ <32>
<41> DOCK_SMB_DAT 129 129 130 130 DOCK_LOM_TRD3- <32>
131 131 132 132
<41,53,63> DOCK_SMB_ALERT# 133 133 134 134 DOCK_DCIN_IS+ <61>
<53> DOCK_PSID 135 135 136 136 DOCK_DCIN_IS- <61>
137 137 138 138
139 140 D32
<41> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <41>
141 142 RB751S40T1_SOD523-2~D
SLICE_BAT_PRES# 141 142 DOCK_DET_R#
<40,53,63> SLICE_BAT_PRES# 143 143 144 144 1 2 DOCK_DET# <40>
145 GND1 PWR2 149 +DOCK_PWR_BAR
+DOCK_PWR_BAR 146 PWR1 PWR2 150
147 PWR1 PWR2 151
3

2
SM24.TCT_SOT23-3~D

148 PWR1 GND2 152

4.7U_0805_25V6K~D

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D
C703
1
C702

D33

1 @ 1 153 159
Shield_G Shield_G
154 Shield_G Shield_G 160
CE6

@ 155 161
Shield_G Shield_G 2
156 162
1

2 2 Shield_G Shield_G
157 Shield_G Shield_G 163
158 Shield_G Shield_G 164

DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK

JAE_WD2F144WB1

1
A A
@ RE11
@RE11 @ RE12 R756
10_0402_5%~D 10_0402_5%~D 33_0402_5%~D

2
1 1 1
@CE8
@CE8 @CE9
@CE9 C704
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D 12P_0402_50V8J~D
2 2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 39 of 77
2 1
 5 4 3 2 1

+3.3V_ALW

1 2 DYN_TURB_PWR_ALRT#
R796 10K_0402_5%~D
1 2 PCIE_WAKE#
R759 10K_0402_5%~D
+3.3V_ALW

1 2 DCIN_CBL_DET#
R761 100K_0402_5%~D
1 1 1 1 1 1

1 2 CPU_DETECT# C705 C706 C707 C708 C709 C710

R763 100K_0402_5%~D 10U_0805_6.3V6M~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2 2 2 2
D SLICE_BAT_PRES# D
1 2
R760 100K_0402_5%~D

A17
B30
A43
A54
B5
U46 +3.3V_ALW
+3.3V_ALW2

VCC1
VCC1
VCC1
VCC1
VCC1
ACAV_IN_NB <41,61,63> 1 2 C711
CRT_SWITCH B52 B63 SIO_SLP_A# 0.1U_0402_16V4Z~D
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,57>

5
1 2 USB_SIDE_EN# MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON
<45> MDC_RST_DIS# GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON <56>
R768 10K_0402_5%~D MCARD_MISC_PWREN B53 A61 1

P
<38> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16> B
1 2 ESATA_USB_PWR_EN# DCIN_CBL_DET# A50 B65
R769 10K_0402_5%~D
<53> DCIN_CBL_DET#
LID_CL_SIO# GPIOA3 GPIOI4 SIO_SLP_S3# <16> O 4D34 2 1 DOCK_AC_OFF <39,63>
B54 GPIOA4 GPIOI5 A62 IMVP_PWRGD <59> 2 A

G
GPU_DEEP_CLKDWN A51 B66 1 2 RB751S40T1_SOD523-2~D
<47> GPU_DEEP_CLKDWN GPIOA5 GPIOI6 IMVP_VR_ON <59>

1
PCIE_WAKE# B55 A63 @R765
@ R765 0_0402_5%~D U47
<29,37,38> PCIE_WAKE#

3
GPU_CLKDWN GPIOA6 GPIOI7 DOCK_AC_OFF_EC TC7SH08FU_SSOP5~D R770
<47> GPU_CLKDWN A52 GPIOA7
B67 33K_0402_5%~D
+3.3V_RUN USB_SIDE_EN# GPIOJ0 AUX_EN_WOWL <38> DOCK_AC_OFF_EC <63> +3.3V_ALW
<46> USB_SIDE_EN# A33 GPIOB0 GPIOJ1/TACH1 A64 WLAN_LAN_DISB# <32>
EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# SIO_SLP_LAN# <16,32>

2
USH_PWR_STATE# GPIOB1 GPIOJ2/TACH2 SIO_SLP_SUS#
<34> USH_PWR_STATE# A34 GPOC2 GPIOJ3 B6 SIO_SLP_SUS# <16>
<63> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6
PANEL_BKEN_EC GPOC3 GPIOJ4 MODC_EN GPIO_PSID_SELECT <53>
<24> PANEL_BKEN_EC A35 GPOC4 GPIOJ5 B7 MODC_EN <29>
1 2 WIRELESS_ON#/OFF B38 A7 DOCK_HP_DET
<16,24> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <30>
R766 100K_0402_5%~D LCD_TST A36 B8 DOCK_MIC_DET WLAN_LAN_DISB# 2 1
<24> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <30>
1 2 SP_TPM_LPC_EN PSID_DISABLE# A37 R771 100K_0402_5%~D
@R772
@ R772 10K_0402_5%~D <53> PSID_DISABLE# PBAT_PRES# GPIOC7 ME_FWP
<53,63> PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP <14>
1 2 LCD_TST DOCKED A38 B9 MASK_SATA_LED# MIC_MUTE# 2 1
<32> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <44>
R767 100K_0402_5%~D DOCK_DET# B41 B10 R773 100K_0402_5%~D
<39> DOCK_DET# GPIOC0 GPIOK2 1.8V_RUN_PWRGD <56>
AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT#
<30> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <44>
MCARD_WWAN_PWREN B42 B11 TEMP_ALERT#_R 1 2TEMP_ALERT#
<38> MCARD_WWAN_PWREN GPIOB6 GPIOK4 @ R738 TEMP_ALERT# <14,18>
1 2 SYS_LED_MASK# LCD_VCC_TEST_EN A40 A11 RUN_ON 0_0402_5%~D +3.3V_RUN
<24> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <11,38,43,56,64>
R775 10K_0402_5%~D CCD_OFF B43 B12 2 1MIC_MUTE#
<24> CCD_OFF GPIOB4 GPIOK6 MIC_MUTE# <46>
1 2 DGPU_PWR_EN AUD_HP_NB_SENSE A41 A12 @ R806 1K_0402_5%~D
<30,46> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <14>
R1582 100K_0402_5%~D ESATA_USB_PWR_EN# B44 D_CLKRUN# 2 1
C <45> ESATA_USB_PWR_EN# GPIOB2 C
1 2 GFX_MEM_VTT_ON B60 R777 100K_0402_5%~D
R1583 100K_0402_5%~D GPIOL0/PWM7 GPIOL1 1 D_SERIRQ
GPIOL1/PWM8 A57 2 2 1
1 2 DP_HDMI_HPD MODULE_ON B32 B64 R1568 10K_0402_5%~D R780 100K_0402_5%~D
<63> MODULE_ON GPIOD1 GPIOL2/PWM0
R1154 100K_0402_5%~D <63> SLICE_BAT_ON SLICE_BAT_ON A31 B68 D_DLDRQ1# 2 1
SLICE_BAT_PRES# GPIOD2 GPIOL3/PWM1 R782 100K_0402_5%~D
<39,53,63> SLICE_BAT_PRES# B33 GPIOD3 GPIOL4/PWM3 A9
MODULE_BATT_PRES# B15 B1
<53,63> MODULE_BATT_PRES# CHARGE_MODULE_BATT GPIOD4 GPIOL5/PWM2
<63> CHARGE_MODULE_BATT A15 GPIOD5 GPIOL6 A18
CHARGE_PBATT B16 A44
<63> CHARGE_PBATT DEFAULT_OVRDE GPIOD6 GPIOL7/PWM5 RUN_ON
<63> DEFAULT_OVRDE A16 GPIOD7 2 1
B34 R786 100K_0402_5%~D
GPIOM1
GPIOM3/PWM4 B39
<44> VOL_MUTE_LED# A1 B51 CPU_VTT_ON 2 1
GPIOE0/RXD GPIOM4/PWM6 R789 100K_0402_5%~D
B2 GPIOE1/TXD
GFX_MEM_VTT_ON A2
<50> GFX_MEM_VTT_ON GPIOE2/RTS# LPC_LAD[0..3] <14,34,35,41>
MCARD_PCIE_SATA# B3 A27 LPC_LAD0 0.75V_DDR_VTT_ON 2 1
PAD~D T168 @ CPU_DETECT# GPIOE3/DSR# LAD0 LPC_LAD1 R790 100K_0402_5%~D
<7> CPU_DETECT# A3 GPIOE4/CTS# LAD1 A26
DGPU_PWR_EN B45 B26 LPC_LAD2 SLICE_BAT_ON 2 1
<64> DGPU_PWR_EN MOD_SATA_PCIE#_DET GPIOE5/DTR# LAD2 LPC_LAD3 R791 100K_0402_5%~D
<29> MOD_SATA_PCIE#_DET A42 GPIOE6/RI# LAD3 B25
DP_HDMI_HPD B4 A21 LPC_LFRAME#
<47> DP_HDMI_HPD GPIOE7/DCD# LFRAME# LPC_LFRAME# <14,34,35,41>
B22 PCH_PLTRST#_EC
LRESET# PCH_PLTRST#_EC <14,17,35,37,38,41>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <17>
ZODD_WAKE# A59 B20 CLKRUN#
<29> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <16,35,41>
BCM5882_ALERT# B62 A23 LPC_LDRQ0#
<34> BCM5882_ALERT# GPIOF1 LDRQ0# LPC_LDRQ0# <14>
A58 A22 LPC_LDRQ1#
<16> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <14>
EDID_SELECT# B61 B21 IRQ_SERIRQ
<25> EDID_SELECT# GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <14,34,35,41>
DGPU_PWROK A56 A32 CLK_SIO_14M
<18,64> DGPU_PWROK GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <15>
VGA_ID B59 B35 EC_32KHZ_ECE5048 <41>
3.3V_RUN_GFX_ON GPIOF5 CLK32/GPIOM2
<15,50> 3.3V_RUN_GFX_ON A55 GPIOF6
SLP_ME_CSW_DEV# B58
<14,18> SLP_ME_CSW_DEV# GPIOF7
B29 D_LAD0
DLAD0 D_LAD1 D_LAD0 <39>
DLAD1 B28 D_LAD1 <39>
LAN_DISABLE#_R B47 A25 D_LAD2
B <32> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <39> B
CHARGE_EN A45 A24 D_LAD3
<63> CHARGE_EN GPIOG1 DLAD3 D_LAD3 <39>
<44> SYS_LED_MASK# SYS_LED_MASK# B48 B23 D_LFRAME#
GPIOG2 DLFRAME# D_LFRAME# <39>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
<61> DYN_TURB_PWR_ALRT# GPIOG3 DCLKRUN# D_CLKRUN# <39>
<14,18> SIO_EXT_WAKE# R7971
@R797
@ 20_0402_5%~D B49 B24 D_DLDRQ1#
GPIOG4 DLDRQ1# D_DLDRQ1# <39>
WIRELESS_LED# A47 A20 D_SERIRQ
+3.3V_ALW <37,44> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <39>
PCH_PCIE_WAKE# B50
<16> PCH_PCIE_WAKE# WLAN_RADIO_DIS# GPIOG6
<37> WLAN_RADIO_DIS# A48 GPIOG7/TACH6
A29 BC_INT#_ECE5048
BC_INT# BC_INT#_ECE5048 <41>
B31 BC_DAT_ECE5048
BC_DAT BC_DAT_ECE5048 <41>
WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048
<46> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <41>
1 2 VGA_ID BT_RADIO_DIS# A13
<42> BT_RADIO_DIS# GPIOH1
@ R800 100K_0402_5%~D WWAN_RADIO_DIS# A53
<37> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
SYS_PWROK B57 A4 RUNPWROK
<7,16> SYS_PWROK SYSOPT0/GPIOH3 PWRGD RUNPWROK <7,41>
DGPU_SELECT# B14
<23,25> DGPU_SELECT# GPIOH4
DGPU_DI_INT# A14 B56 SP_TPM_LPC_EN
<47> DGPU_DI_INT# GPIOH5 OUT65 SP_TPM_LPC_EN <34,35>
CPU_VTT_ON B17 +3.3V_ALW
<58,62> CPU_VTT_ON GPIOH6
<16> PCH_DPWROK 1 2 B18 GPIOH7
VGA_ID 1 2 @ R802 0_0402_5%~D B19 2 1
R803 100K_0402_5%~D TEST_PIN R804 1K_0402_5%~D

1
B46 +CAP_LDO
CAP_LDO CLK_SIO_14M CLK_PCI_5048 R805
1 +CAP_LDO trace width 20 mils
B27 100K_0402_5%~D
VSS C714
EP C1

1
VGA_ID0 4.7U_0603_6.3V6K~D @ R795

2
DB Version 0.4 2 @ R794 10_0402_5%~D
Discrete 0 ECE5028-LZY_DQFN132_11X11~D 10_0402_5%~D LID_CL_SIO# 2 1 LID_CL# <44,46>
R807 10_0402_5%~D
UMA 1 1

2
1 1 C716
0.047U_0402_16V4Z~D
@C712
@ C712 @ C713
@C713 2
A 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D A
2 2
ME_FWPPCHhasinternal20KPD.
(suspendpowerrail)
ME_FWP DELL CONFIDENTIAL/PROPRIETARY
2

@ R793 Compal Electronics, Inc.

1K_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
1

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 40 of 77
5 4 3 2 1
 5 4 3 2 1

+RTC_CELL
+3.3V_ALW +3.3V_ALW
H_PROCHOT# <7,59>

1
C720 @ C721
1 2 0.1U_0402_16V4Z~D 1 2 R810 1U_0402_6.3V6K~D
@ R1179 10K_0402_5%~D 100K_0402_5%~D 1 2

1
U50 D

2
1.05V_VTTPWRGD 1 PROCHOT#_EC 2 @ Q47

P
<58,62> 1.05V_VTTPWRGD B
4 1.05V_0.8V_PWROK G SSM3K7002FU_SC70-3~D POWER_SW_IN# 1 2
O 1.05V_0.8V_PWROK <14,59> <22> POWER_SW_IN# POWER_SW#_MB <31,42>
0.8V_VCCPWROK 2 1 2 S 1 R811 10K_0402_5%~D
<62> 0.8V_VCCPWROK

3
A

G
+3.3V_ALW @ R812 100K_0402_5%~D
TC7SH08FU_SSOP5~D C722

3
+RTC_CELL R815 +3.3V_ALW 1U_0402_6.3V6K~D
0_0402_5%~D 1 2 2
1 2 +RTC_CELL_VBAT R1180 0_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_6.3V6M~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 2 BC_DAT_ECE5048 1
R814 100K_0402_5%~D
2 1 BC_DAT_EMC4022 C723 1 1 1 1 1 1 1 1 1 +RTC_CELL
D D
R816 100K_0402_5%~D 0.1U_0402_16V4Z~D
2

C724

C727

C728

C729

C730

C731

C725

C726

C732

1
@ C733
2 2 2 2 2 2 2 2 2 R819 1U_0402_6.3V6K~D
2 1 BC_DAT_ECE1117 100K_0402_5%~D 1 2

B64

A11
A22
B35
A41
A58
A52

A26
R817 100K_0402_5%~D U51

B3

2
1 2 PBAT_SMBDAT

VBAT

VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
R818 2.2K_0402_5%~D DOCK_PWR_SW# 1 2
<22> DOCK_PWR_SW# DOCK_PWR_BTN# <39>
1 2 PBAT_SMBCLK 1 R825 10K_0402_5%~D
R820 2.2K_0402_5%~D
2 1 LPC_LDRQ#_MEC PS/2 INTERFACE MISC INTERFACE C734
@ R821 100K_0402_5%~D SML1_SMBDATA A5 A10 SYSTEM_ID 1U_0402_6.3V6K~D
<15> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1 2
SML1_SMBCLK B6 B10 BOARD_ID
<15> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2
1 2 CHARGER_SMBDAT CLK_TP_SIO A37 B14 DDR_ON
<42> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON <55,56>
R827 2.2K_0402_5%~D DAT_TP_SIO B40 B44 HOST_DEBUG_TX
<42> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX <37>
1 2 CHARGER_SMBCLK CLK_KBD A38 B46 HOST_DEBUG_RX
<39> CLK_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX HOST_DEBUG_RX <37>
R828 2.2K_0402_5%~D DAT_KBD B41 B26 RUNPWROK
<39> DAT_KBD GPIO113/PS2_DAT1A VCC_PRWGD RUNPWROK <7,40>
2 1 DOCK_SMB_ALERT# CLK_MSE A39 A25 EN_INVPWR
<39> CLK_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <24>
R762 10K_0402_5%~D DAT_MSE B42 B36 +RTC_CELL
<39> DAT_MSE GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK PCH_SATA_MOD_EN# <14>
+3.3V_RUN PBAT_SMBDAT B59 B37
<53> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO TOUCH_SCREEN_PD# <24>
PBAT_SMBCLK A56 B38 XFR_ID_BIT#
<53> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI

1
1 2 GPU_SMBDAT A34 DDR_HVREF_RST_GATE @ C738
R829 2.2K_0402_5%~D GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE <7> R870 1U_0402_6.3V6K~D
GPIO104/HSPI_MISO A35 DYN_TUR_CURRNT_SET# <61>
1 2 GPU_SMBCLK A36 CPU1.5V_S3_GATE 100K_0402_5%~D 1 2
R822 2.2K_0402_5%~D GPIO106/HSPI_MOSI MSDATA CPU1.5V_S3_GATE <11>
JTAG INTERFACE GPIO116/MSDATA A40 MSDATA <37>
JTAG_TDI A51 B43 MSCLK
MSCLK <37>

2
JTAG_TDO GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK SIO_A20GATE
B55 GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M A45 SIO_A20GATE <18>
JTAG_CLK B56 A55 PS_ID LAT_ON_SW# 1 2
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 PS_ID <53> LAT_ON_SW_BTN# <31>
+3.3V_ALW JTAG_TMS A53 A57 BAT1_LED# Bat2 = Amber LED 1 @ R877 10K_0402_5%~D
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1 BAT1_LED# <44>
JTAG_RST# B57 B61 BAT2_LED# Bat1 = Blue LED
JTAG_RST# GPIO157/LED2 BAT2_LED# <44>
B65 FWP# @ C740
nFWP
1
10K_0402_5%~D

A46 PROCHOT#_EC 20mA drive pins 1U_0402_6.3V6K~D

PROCHOT#/PWM4 2
R824

1 2 C736 High active

JTAG_RST# citcuit 0.1U_0402_16V4Z~D FAN PWM & TACH
close to U51.B57 DOCK_POR_RST# B22 GENERAL PURPOSE I/O 2 1 VOL_MUTE
<39> DOCK_POR_RST# GPIO050/FAN_TACH1 VOL_MUTE <46> +3.3V_RUN
SUS_ON A21 B2 R884 1K_0402_5%~D
<43> SUS_ON
2

AUX_ON GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1 DOCK_SMB_ALERT#

<32> AUX_ON B23 GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2 A2 DOCK_SMB_ALERT# <39,53,63>
JTAG_RST# BREATH_LED# B24 B8 R886 1 2 1K_0402_5%~D VOL_UP
<39,44> BREATH_LED# GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP <46>

1
C PCH_ALW_ON A23 B18 R887 1 2 1K_0402_5%~D VOL_DOWN C
<43> PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN <46>
<24> BIA_PWM_EC BIA_PWM_EC B25 A8 ME_SUS_PWR_ACK R799
GPIO055/PWM2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <16>
1

1 HDDC_EN A24 B9 1.5V_SUS_PWRGD 10K_0402_5%~D

<28> HDDC_EN GPIO056/PWM3 GPIO016/GPTP-IN8 1.5V_SUS_PWRGD <55>
100_0402_5%~D

0.1U_0402_16V4Z~D

@ A9 PM_APWROK
1

GPIO017/GPTP-OUT8 PM_APWROK <16>

R836

C735

SSM3K7002FU_SC70-3~D
A14 1.05V_A_PWRGD
1.05V_A_PWRGD <57>

2
GPIO026/GPTP-IN1 ALW_PWRGD_3V_5V RUNPWROK
2
BC-LINK GPIO027/GPTP-OUT1 B15 ALW_PWRGD_3V_5V <54>
JTAG1 BC_CLK_ECE5048 A43 A17 DEVICE_DET#
DEVICE_DET# <29>
2

@SHORT PADS~D <40> BC_CLK_ECE5048 BC_DAT_ECE5048 GPIO123/BCM_A_CLK GPIO041 RESET_OUT#

<40> BC_DAT_ECE5048 B45 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT B39 RESET_OUT# <16>

1
CONN@ BC_INT#_ECE5048 A_ON D
<40> BC_INT#_ECE5048 A42 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 A44 A_ON <43,57>

Q45
BC_CLK_EMC4022 A12 B47 PCH_RSMRST# 2
<22> BC_CLK_EMC4022 GPIO022/BCM_B_CLK GPIO126 <43> RUN_ON_ENABLE#
2

<22> BC_DAT_EMC4022 BC_DAT_EMC4022 B13 A54 AC_PRESENT G

GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 AC_PRESENT <16>
BC_INT#_EMC4022 A13 B58 SIO_PWRBTN# S
<22> BC_INT#_EMC4022 SIO_PWRBTN# <16>
2

3
GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4
B20 GPIO044/BCM_C_CLK
A18 GPIO043/BCM_C_DAT
B19 GPIO042/BCM_C_INT# SMBUS INTERFACE
BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT
<42> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <39>
<42> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK +3.3V_ALW_PCH
GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK DOCK_SMB_CLK <39>
BC_INT#_ECE1117 A19 A4 LCD_SMBDAT
+3.3V_ALW <42> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA
BEEP A16 B5 LCD_SMBCLK
<30> BEEP GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK
SIO_SLP_S5# B16 B7 BAY_SMBDAT AC_PRESENT 1 2
<16> SIO_SLP_S5# GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA BAY_SMBDAT <29,53>
ACAV_IN_NB A15 A7 BAY_SMBCLK R835 10K_0402_5%~D
<40,61,63> ACAV_IN_NB GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK BAY_SMBCLK <29,53>
B48 GPU_SMBDAT
GPIO130/I2C2A_DATA GPU_SMBDAT <47>
1

1
10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

100K_0402_5%~D
@ R850

B49 GPU_SMBCLK +3.3V_ALW

GPIO131/I2C2A_CLK GPU_SMBCLK <47>
R847

R848

R849

HOST INTERFACE A47 CHARGER_SMBDAT

GPIO132/I2C1G_DATA CHARGER_SMBDAT <61>
SIO_EXT_SMI# A6 B50 CHARGER_SMBCLK LCD_SMBCLK 2 1
<14,17> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <61>
SIO_RCIN# A27 B52 CARD_SMBDAT R418 2.2K_0402_5%~D
<18> SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <38>
CONN@ LPC_LDRQ#_MEC B29 A49 CARD_SMBCLK LCD_SMBDAT 2 1
CARD_SMBCLK <38>
2

JDEG1 IRQ_SERIRQ LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK USH_SMBDAT R420 2.2K_0402_5%~D

A28 SER_IRQ GPIO143/I2C1E_DATA B53 USH_SMBDAT <34>
<14,34,35,40> IRQ_SERIRQ PCH_PLTRST#_EC USH_SMBCLK DOCK_SMB_DAT
1 1 <14,17,35,37,38,40> PCH_PLTRST#_EC B30 LRESET# GPIO144/I2C1E_CLK A50 USH_SMBCLK <34> 2 1
2 MSCLK CLK_PCI_MEC A29 R838 2.2K_0402_5%~D
2 <17> CLK_PCI_MEC PCI_CLK
7 3 MSDATA LPC_LFRAME# B31 DOCK_SMB_CLK 2 1
G1 3 <14,34,35,40> LPC_LFRAME# LFRAME#
8 4 1 2 HOST_DEBUG_TX LPC_LAD0 A30 DELL PWR SW INF R841 2.2K_0402_5%~D
G2 4 <14,34,35,40> LPC_LAD0 LAD0
5 @ R8531 2 0_0402_5%~D HOST_DEBUG_RX LPC_LAD1 B32 A59 VOL_MUTE 2 1
5 <14,34,35,40> LPC_LAD1 LAD1 BGPO0
6 @ R855 0_0402_5%~D LPC_LAD2 A31 B63 LAT_ON_SW# R1169 100K_0402_5%~D
6 <14,34,35,40> LPC_LAD2 LAD2 VCI_IN2#
LPC_LAD3 B33 A60 ALWON VOL_UP 2 1
<14,34,35,40> LPC_LAD3 LAD3 VCI_OUT ALWON <54>
ACES_85204-06001~D CLKRUN# A32 A63 VCI_INT1# R1170 100K_0402_5%~D
<16,35,40> CLKRUN# CLKRUN# VCI_IN1#
SIO_EXT_SCI# A33 B67 POWER_SW_IN# VOL_DOWN 2 1
+3.3V_ALW <18> SIO_EXT_SCI# GPIO100/nEC_SCI VCI_IN0#
B1 ACAV_IN R1197 100K_0402_5%~D
VCI_OVRD_IN ACAV_IN <22,61,63> +1.05V_RUN_VTT
A1 DOCK_PWR_SW# BAY_SMBDAT 2 1
VCI_IN3# trace width 20 mils R854 2.2K_0402_5%~D
B
MASTER CLOCK B
MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2 BAY_SMBCLK 2 1
XTAL1 PECI_VREF
49.9_0402_1%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

MEC_XTAL2 2 1 MEC_XTAL2_R A62 A48 PECI_EC_R 1 2 @ R862 0_0402_5%~D R856 2.2K_0402_5%~D

XTAL2 PECI PECI_EC <7>
1

@ R1068 0_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D 1 DYN_TUR_CURRNT_SET# 2 1

GPIO160/32KHZ_OUT
R857

R858

R859

R860

R861

I2S B17 R863 close to R1171 100K_0402_5%~D

I2S_DAT U51& least 250mils C737
I2S_CLK B27 1 2
VSS_RO
VR_CAP

B34 B28 @ R864 1 2 100K_0402_5%~D 0.1U_0402_16V4Z~D XFR_ID_BIT# 2 1

VSS[1]
VSS[4]

NC1 I2S_WS 2
AGND

CONN@ A64 @ R865 100K_0402_5%~D R943 10K_0402_5%~D

2

JTAG2 NC2
EP

<40> EC_32KHZ_ECE5048 1 2 B68 NC3

1 @ R867 0_0402_5%~D
1 JTAG_TDI Depopulated R867 for ECE5028 use MEC5055-LZY_DQFN132_11X11~D R864 & R865
2
B66

B11
B60

B12

B54

C1

2 JTAG_TMS
7 G1 3 3 for MEC5045 need to used 0 ohm
8 4 JTAG_CLK for MEC5055 need to used 100K ohm.
G2 4 JTAG_TDO +RTC_CELL
5 5
6 +3.3V_ALW
6 least VCI_INT1# 2 1
ACES_85204-06001~D R875 C744 REV 15mil 15mil R1156 100K_0402_5%~D
2

+5V_RUN
R875 2 1 MSDATA
240K 4700p X00 1
C739

Place closely pin A29 33K_0402_5%~D R869 10K_0402_5%~D CLK_KBD

4.7U_0603_6.3V6K~D

2 1
2 1 A_ON R845 4.7K_0402_5%~D
CLK_PCI_MEC 130K 4700p X01 +3.3V_ALW +3.3V_ALW R873 100K_0402_5%~D DAT_KBD 2 1
1

2 1 2 AUX_ON R846 4.7K_0402_5%~D

62K 4700p X02
1

BOARD_ID R874 2.7K_0402_5%~D CLK_MSE 2 1

@ R885 1 2 DDR_ON R851 4.7K_0402_5%~D
* 33K 4700p A00

2
10_0402_5%~D R876 100K_0402_5%~D DAT_MSE 2 1
R871 R872 1 2 SUS_ON R852 4.7K_0402_5%~D
1 8.2K 4700p 1K_0402_5%~D 10K_0402_5%~D R878 100K_0402_5%~D
2

C744 1 2 PCH_ALW_ON
1
4700P_0402_25V7K~D 4.3K 4700p 1 2 R880 100K_0402_5%~D

1
@ C747 +3.3V_ALW_PCH R1588 0_0402_5%~D 1 2 DOCK_POR_RST#
4.7P_0402_50V8C~D
2
2 2K 4700p SYSTEM_ID FWP# R881 100K_0402_5%~D +3.3V_RUN
@ Q126 1 2 EN_INVPWR
1K 4700p MMBT3906WT1G_SC70-3~D R882 100K_0402_5%~D
2

2
PCH_RSMRST# 1 3 PCH_RSMRST#_Q 1 1 2 1.05V_0.8V_PWROK
C

PCH_RSMRST#_Q <14,16>
@ R1587 C742 @ R879 R883 10K_0402_5%~D DEVICE_DET# 2 1
E

4.7K_0402_5%~D 4700P_0402_25V7K~D 10K_0402_5%~D 1 2 RESET_OUT# R1118 100K_0402_5%~D

@ R843 8.2K_0402_5%~D
BOARD_IDrisetimeismeasuredfrom5%~68%.
B
2

2 1 2 CPU1.5V_S3_GATE
1

1
R889 100K_0402_5%~D
A
32 KHz Clock +3.3V_M @ D76A
1
A

6
1

C741 2
1 2 R893
100K_0402_5%~D BAV99DW-7-F_SOT363-6~D 1=JTAG interface Reset disabled
39P_0402_50V8J~D CHIPSET_ID for BID 0=Reset JTAG interface
Y6 @ D76B
2

MEC_XTAL2 PCH_PWRGD# 4
function
4 G 3 PCH_PWRGD# <22>
3 DELL CONFIDENTIAL/PROPRIETARY
5
1

D
MEC_XTAL1 1 G 2
RESET_OUT# 2 Q48 BAV99DW-7-F_SOT363-6~D
Compal Electronics, Inc.
32.768KHZ_12.5PF_Q13MC1461000~D G SSM3K7002FU_SC70-3~D @ R1589 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
C743 2.2K_0402_5%~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
S
SCHEMATICS,MB A6561
3

1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

2

INTEL RSMRST# circuit NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
39P_0402_50V8J~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 41 of 77
5 4 3 2 1
 5 4 3 2 1

BlueTooth +3.3V_BT

+3.3V_RUN 1 2 1 2
@ R1129 0_0603_5%
+3.3V_ALW 1 2 C748
@ R1130 0_0402_5%~D 0.1U_0402_16V4Z~D
Touch Pad Pitch: 1.0
+3.3V_TP CONN@
JBT1
D D
1 1
<17> BT_DET# 2 2

4.7K_0402_5%~D

4.7K_0402_5%~D
<37> COEX1_BT_ACTIVE 3 3

1
<34> BT_COEX_STATUS2 4 4
R903

R902
<34> BT_PRI_STATUS 5 5
Pitch: 0.5 <44> BT_ACTIVE 6 6
<40> BT_RADIO_DIS# 7 7
<37> COEX2_WLAN_ACTIVE 8
2

2
JTP1 CONN@ 8
9 9
2 1 TP_DATA 1 10
<41> DAT_TP_SIO 1 10
L54 BK1608HM601-T_0603~D TP_CLK 2 11
2 <17> USBP11- 11
2 1 TP_CLK TP_DATA 3 12
<41> CLK_TP_SIO 3 <17> USBP11+ 12
L55 BK1608HM601-T_0603~D 4 13
4 G1

10P_0402_50V8J~D

10P_0402_50V8J~D
+3.3V_TP 5 5 14 G2
10P_0402_50V8J~D

10P_0402_50V8J~D

1 1 1 1 PS2_DAT_TS 6 9
PS2_CLK_TS 6 G1 @R1133
@ R1133 LOTES_YBA-WTB-010-K01~D
7 7 G2 10
C752

C751

C750

C749
8 1K_0402_5%~D
8

100P_0402_50V8J~D
+3.3V_BT 1 2 BT_COEX_STATUS2
2 2 2 2

33P_0402_50V8J~D

10K_0402_5%~D
TYCO_2041070-8

@ C754
@R1134
@ R1134 1 1

C753

R904
1K_0402_5%~D
1 2 BT_PRI_STATUS
2 2

2
C C
+3.3V_TP
TP_CLK +3.3V_TP
TP_DATA
SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D
1 +3.3V_RUN 1 2
1

1
@ R1161 0_0603_5%
C755 +3.3V_ALW 1 2
@D36
@

@D37
@
0.1U_0402_16V4Z~D @ R1162 0_0603_5%~D
2
D36

D37
2

Place close to
JTP1.7 Place close to JTP1 connector

Keyboard
B B

Pitch: 1.0
JKB1 CONN@
+3.3V_ALW +5V_RUN 1
<18> KB_DET# PS2_CLK_TS 1
2 2
PS2_DAT_TS 3 3
1 1 +3.3V_ALW 4 4
+5V_RUN 5 5
C756 C758 6
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D <41> BC_INT#_ECE1117 6
<41> BC_DAT_ECE1117 7 7
2 2
8 8
<41> BC_CLK_ECE1117 9 9
10 10
11 GND
Place close to JKB1 12 GND
FCI_10089709-010010LF~D

Power Switch for debug

<31,41> POWER_SW#_MB 1 1 2 2
A A
1
@ C759
100P_0402_50V8J~D @ PWRSW1
2 @SHORT PADS~D
Place on Bottom DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 42 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW +3.3V_ALW_PCH
DC/DCInterface +5V_RUNSource
+3.3V_ALW_PCHSource 1 2 +3.3V_ALW2 +15V_ALW +5V_ALW Q50
+15V_ALW PJP67 PAD-OPEN 43X118 SI4164DY-T1-GE3_SO8~D +5V_RUN
+3.3V_ALW2 8 1

1
@ Q49 7 2

10U_0805_10V4Z~D
6 SI3456DDV-T1-GE3_TSOP6~D R906 6 3

S
1

1
5 4 100K_0402_5%~D 5 1

10U_0805_6.3V6M~D
@ @ 2 R909 R910

1
20K_0402_5%~D

C761
R907 R905 1 1 @ @ 100K_0402_5%~D 20K_0402_5%~D

4
100K_0402_5%~D 100K_0402_5%~D 5V_RUN_ENABLE

G
2

C760

R908
2

2
3
ALW_ENABLE

2
<20> ALW_ENABLE 2

2200P_0402_50V7K~D
2
3
D Q52B D

3300P_0402_50V7K~D
RUN_ON_ENABLE# 5 DMN66D0LDW-7_SOT363-6~D 1
<41> RUN_ON_ENABLE#
Q51B @ 1 @

C763
ALW_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D

4
C762
6

6
2

4
@ Q51A 2 Q52A
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
<41> PCH_ALW_ON 2 <11,38,40,56,64> RUN_ON 2

1
+3.3V_RUNSource
+3.3V_ALW Q55 +3.3V_RUN
+15V_ALW NTMS4920NR2G_SO8~D
+3.3V_SUSSource +15V_ALW 8 1

10U_0805_6.3V6M~D
+3.3V_ALW Q54 7 2

1
20K_0402_5%~D
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS 6 3 1

1
R912 5

C764

R913
R911 6 100K_0402_5%~D

S
+3.3V_ALW2 100K_0402_5%~D 5 4

4
2

10U_0805_6.3V6M~D
2

2
1
20K_0402_5%~D
1 1

2
3.3V_RUN_ENABLE

G
1

C765

R914
3

470P_0402_50V7K~D
R915 SUS_ENABLE

1
100K_0402_5%~D 2 D
1

2
3

C766
G Q56
2

Q53B S SSM3K7002FU_SC70-3~D

3
2

4700P_0402_25V7K~D
SUS_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D 1
C C
6

C767
4

Q53A
DMN66D0LDW-7_SOT363-6~D 2
<41> SUS_ON 2
1

DischargCircuit +1.5V_RUNSource
Q59
+3.3V_M +1.5V_MEM NTGS4141NT1G_TSOP6~D
+3.3V_MSource +15V_ALW +1.5V_RUN

D
+3.3V_ALW Q58 6

S
1
+15V_ALW SI3456DDV-T1-GE3_TSOP6~D +3.3V_M 5 4

10U_0805_6.3V6M~D
+3.3V_ALW2 R916 2

1
D

20K_0402_5%~D
6 39_0603_5%~D R920 1 1
S
1

5 4 100K_0402_5%~D

G
10U_0805_6.3V6M~D

C769

R921
R917 2

3
@
1

1
20K_0402_5%~D
100K_0402_5%~D

+3.3V_M_CHG
1 1

2
2

R919
R918
G

2
C768

100K_0402_5%~D 1.5V_RUN_ENABLE
2

A_ENABLE
2

4700P_0402_25V7K~D
2

2
3

SSM3K7002FU_SC70-3~D
1

1
D
4700P_0402_25V7K~D

C771
Q57B 2 Q62

1
A_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D D G SSM3K7002FU_SC70-3~D
1 2

Q60
A_ON_3.3V# 2 S

3
6

C770

G
4

Q57A S

3
B DMN66D0LDW-7_SOT363-6~D 2 B

<41,57> A_ON 2
1

+1.05V_RUNSource
+15V_ALW +1.05V_M Q63
DischargCircuit SI4164DY-T1-GE3_SO8~D
8 1
+1.05V_RUN

1
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT 7 2

10U_0805_6.3V6M~D
R930 6 3

1
20K_0402_5%~D
100K_0402_5%~D 5 1
1

C772

R931
@ R922 @R928
@ R928 @ R923 @ R924 R929 @ R925 R926

4
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 39_0603_5%~D 39_0402_5%~D 220_0402_5%~D R927 1.05V_RUN_ENABLE
22_0603_5%~D 2

2
2

1
D

2200P_0402_50V7K~D
+3.3V_ALWPCH_CHG

+5V_RUN_CHG

+1.5V_RUN_CHG

+3.3V_RUN_CHG

+1.05V_RUN_CHG

+1.5V_CPU_VDDQ_CHG
Q64
+3.3V_SUS_CHG

+DDR_CHG
G SSM3K7002FU_SC70-3~D 1
S

C773
2
<7,11> RUN_ON_CPU1.5VS3#
1

1
D D D D D
SSM3K7002FU_SC70-3~D
@ Q67

SSM3K7002FU_SC70-3~D
@ Q68

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D
@ Q70

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D
1

D D
SSM3K7002FU_SC70-3~D
@ Q65

SSM3K7002FU_SC70-3~D
@ Q66

Q69

Q72
RUN_ON_ENABLE# 2 2 2 2 2
1

SUS_ON_3.3V# ALW_ON_3.3V# G G G G D G
2 2
Q71

G G S S S S 2 S
3

3
A S S G A
3

S
3

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 43 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW HDDLEDsolutionforWhiteLED

1
+5V_ALW +5V_ALW
R932 R938

3
10K_0402_5%~D 100K_0402_5%~D Q83A
+5V_ALW 1 2

3
+3.3V_ALW DMN66D0LDW-7_SOT363-6~D

2
Q74B Q74A 1 6 2
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D Q82A

6
4 3 1 2 1 6 2 DMN66D0LDW-7_SOT363-6~D Q81
<14> SATA_ACT#
D59 SDM10U45-7_SOD523-2~D PDTA114EU_SC70-3~D BatteryLED

2
1
Q75 MASK_BASE_LEDS#
PDTA114EU_SC70-3~D R940 1 2 2

1
47K_0402_5%~D +5V_ALW 1 2 BATT_WHITE <46>
MASK_SATA_LED# 1 2 C774 R941 4.7K_0402_5%~D
<40> MASK_SATA_LED#

1
5

1
D D
D62 SDM10U45-7_SOD523-2~D 0.1U_0402_16V4Z~D

1
+5V_ALW BATT_YELLOW <46>

NC
1 2 SATA_LED SATA_LED <46> 2 4 BAT2_LED R942
<41> BAT2_LED# A Y
R934 4.7K_0402_5%~D 100K_0402_5%~D

3
U54
<40> LED_SATA_DIAG_OUT# Q83B
NC7SZ04P5X_NL_SC70-5~D

2
DMN66D0LDW-7_SOT363-6~D
5 4 3 2
MASK_BASE_LEDS#
Q82B Q84

4
DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D

5
SYS_LED_MASK#

1
+3.3V_ALW
R945

3
100K_0402_5%~D
+3.3V_ALW WIRELESSLEDsolutionforWhiteLED +3.3V_ALW 1 2
Q92A
DMN66D0LDW-7_SOT363-6~D
1 6 2

1
+5V_ALW
R937 Q88
100K_0402_5%~D +3.3V_ALW PDTA114EU_SC70-3~D

2
Q89A MASK_BASE_LEDS#

6
2 DMN66D0LDW-7_SOT363-6~D

1
Q78A

1
DMN66D0LDW-7_SOT363-6~D
1 6 2 R947 1 2 2 +3.3V_ALW
<37,40> WIRELESS_LED#
47K_0402_5%~D 1 2
Q79 C775 R946 150_0402_5%~D

1
5

1
PDTA114EU_SC70-3~D 0.1U_0402_16V4Z~D

2
R948 +3.3V_ALW

NC
3

MASK_BASE_LEDS# 2 4 BAT1_LED 100K_0402_5%~D

<41> BAT1_LED#

1
A Y

3
U55

2
DMN66D0LDW-7_SOT363-6~D NC7SZ04P5X_NL_SC70-5~D Q92B R949
<42> BT_ACTIVE 5

3
Q78B DMN66D0LDW-7_SOT363-6~D 4.7K_0402_5%~D
5 4 3 2 1 2 BATT_WHITE_LED <24>
4
1

C R944 Q89B Q93 C

4
100K_0402_5%~D 1 2 WIRELESS_LED DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D
WIRELESS_LED <46>

5
R939 4.7K_0402_5%~D R951
150_0402_5%~D
2

1
SYS_LED_MASK# 1 2 BATT_YELLOW_LED <24>

+5V_ALW

1
+5V_ALW
R953
100K_0402_5%~D

3
Q95B

DMN66D0LDW-7_SOT363-6~D

2
DMN66D0LDW-7_SOT363-6~D
4 3 2
+3.3V_ALW

6
Q94
PDTA114EU_SC70-3~D

5
Q95A
C777
0.1U_0402_16V4Z~D 2 +5V_ALW

1
1
1 2 <40> SYS_LED_MASK# 1 2 BREATH_WHITE_LED <24>
R954 R955 4.7K_0402_5%~D

1
47K_0402_5%~D +5V_ALW
R956
100K_0402_5%~D

3
Q101B

DMN66D0LDW-7_SOT363-6~D
P

NC
<39,41> BREATH_LED#

2
2 4 BREATH_LED#_R DMN66D0LDW-7_SOT363-6~D
A Y
4 3 2

G
U57

6
NC7SZ04P5X_NL_SC70-5~D Q96

3
PDTA114EU_SC70-3~D
SPKStatusLED

5
Q101A
2

1
MASK_BASE_LEDS# LED1
B B
1 2 BREATH_WHITE_LED_PWR 2 1

1
R957 1K_0402_5%~D
LTW-C193TS5_WHITE~D
PlaceLED1closetoSW1
+3.3V_RUN
1

@
R1109 +3.3V_RUN
10K_0402_5%~D
+3.3V_ALW
2

@ Q119
3

C778
SSM3K7002FU_SC70-3~D 0.1U_0402_16V4Z~D
1 2
S

<40> VOL_MUTE_LED# 3 1 2

5
U58
Q102 @ SYS_LED_MASK#
G

P
<40> SYS_LED_MASK#
2

PDTA114EU_SC70-3~D B MASK_BASE_LEDS#
O 4
MASK_BASE_LEDS# LID_CL# 2
<40,46> LID_CL#
1

G
1 2
@ R1059 1K_0402_5%~D R_SPK_LED# <46> TC7SH08FU_SSOP5~D EMI CLIP

3
CLIP1
EMI_CLIP

GND 1

LED Circuit Control Table

Fiducial Mark SYS_LED_MASK# LID_CL#
@ FD1
1
A
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function) 0 X A

@ FD2 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H26 @ H27

Mask Base MB LEDs (Lid Closed) 1 0
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P2 H_2P3 H_2P3
1 Do not Mask LEDs (Lid Opened) 1 1
FIDUCIAL MARK~D
1

@ FD3
1

FIDUCIAL MARK~D
@ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 @ H24
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
@ FD4 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_6P1 H_2P5 H_8P0X2P5 H_2P8 H_8P0X2P5N H_2P8 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
FIDUCIAL MARK~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B

401931
Date: Thursday, January 13, 2011 Sheet 44 of 77
5 4 3 2 1
 5 4 3 2 1

+5V_USB_PWR1

150U_B2_6.3V-M~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

0.1U_0402_16V4Z~D
+3.3V_RUN 1
ESATA Repeater +
1 @ 1 @ 1

C667

C1151

C1152

C668
0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

2
2 2 2 2

0_0402_5%~D

0_0402_5%~D
+3.3V_RUN 1 1 @ JESA1 CONN@

R742

R743
1 VBUS

C662
D D
1 2 ESATA_PWRSAVE USBP1_D- 2 D-

C661
R741 0_0402_5%~D USBP1_D+ 3 USB
2 2 D+
4

1
GND
U44
7 6 ESATA_PTX_DRX_P4_RP 1 2 SATA_PTX_DRX_P4 5
EN VCC C671 0.01U_0402_16V7K~D GND
18 CAD VCC 10 6 A+
<14> ESATA_PTX_DRX_P4_C ESATA_PTX_DRX_P4_C 2 1 ESATA_PTX_DRX_P4 16 ESATA_PTX_DRX_N4_RP 1 2 SATA_PTX_DRX_N4 7 ESATA
C664 0.01U_0402_16V7K~D VCC C672 0.01U_0402_16V7K~D A-
1 AINP VCC 20 8 GND
<14> ESATA_PTX_DRX_N4_C ESATA_PTX_DRX_N4_C 2 1 ESATA_PTX_DRX_N4 2 ESATA_PRX_DTX_N4_RP 1 2 SATA_PRX_DTX_N4 9
C663 0.01U_0402_16V7K~D AINM C673 0.01U_0402_16V7K~D B-
PA 9 10 B+
ESATA_PRX_DTX_N4_C 2 1 ESATA_PRX_DTX_N4 4 8 ESATA_PRX_DTX_P4_RP 1 2 SATA_PRX_DTX_P4 11
<14> ESATA_PRX_DTX_N4_C C666 0.01U_0402_16V7K~D BOUTM PB C674 0.01U_0402_16V7K~D GND
5 BOUTP
ESATA_PRX_DTX_P4_C 2 1 ESATA_PRX_DTX_P4 15 ESATA_PTX_DRX_P4_RP
<14> ESATA_PRX_DTX_P4_C C665 0.01U_0402_16V7K~D AOUTP ESATA_PTX_DRX_N4_RP
3 GND AOUTM 14 12 GND
13 GND 13 GND
17 11 ESATA_PRX_DTX_P4_RP 14
GND BINP ESATA_PRX_DTX_N4_RP L51 GND
19 GND BINM 12 15 GND
21 4 3 USBP1_D+
EP <17> USBP1+ 4 3

1
MAX4951BECTP+TGH7_TQFN20_4X4~D FOX_3Q38111-RA5C5-8H
1 2 USBP1_D-
<17> USBP1- 1 2
R745 @ R746
0_0402_5%~D 0_0402_5%~D DLW21SN900SQ2_0805~D
1 2

2
@ R736 0_0402_5%~D

1 2
@ R737 0_0402_5%~D

C C

D73
USBP1_D- 2
1
USBP1_D+ 3

PESD5V0U2BT_SOT23-3~D

+5V_USB_PWR2 CONN@
L50 JUSB1
4 3 USBP0_D+ 1 8
<17> USBP0+ 4 3 VBUS G

150U_B2_6.3V-M~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
USBP0_D- 2 7
+5V_USB_PWR2 +5V_USB_PWR1 D- G

0.1U_0402_16V4Z~D
1 USBP0_D+ 3 6
USBP0_D- @ @ D+ G
<17> USBP0- 1 1 2 2 1 1 1 4 GND G 5
+

C651

C1153

C1154

C654
+5V_ALW @ U45 DLW21SN900SQ2_0805~D
PJP7
1 10 USB_OC0# <17> 1 2 SUYIN_020173GR004M57HZL
+5V_ALW_FUSE GND FAULT1# @R734
@ R734 0_0402_5%~D 2 2 2 2
2 2 1 1 2 IN OUT1 9
10U_0805_10V4Z~D

3 IN OUT2 8
0.1U_0402_16V4Z~D

JUMP_43X79 4 EN1# ILIM 7 1 2

1 1 5 6 @R735
@ R735 0_0402_5%~D
<40> ESATA_USB_PWR_EN# EN2# FAULT#2
1

T-PAD 11
C669

C670

R747
B TPS2560DRCR-PG1.1_SON10_3X3~D 24.9K_0402_1%~D B
2 2 D72
USBP0_D- 2
2

1
USBP0_D+ 3

PESD5V0U2BT_SOT23-3~D

CONN@

MDC CONN. H=5.5, Pitch=0.8 JMDC1

+3.3V_ALW_PCH
1 2
<14> PCH_AZ_MDC_SDOUT PCH_AZ_MDC_SDOUT 3
GND1
IAC_SDATA_OUT
RES0
RES1 4 W=20 mil
5 GND2 3.3V 6
PCH_AZ_MDC_RST1#
D

<14> PCH_AZ_MDC_RST# 1 3 <14> PCH_AZ_MDC_SYNC 7 IAC_SYNC GND3 8

1 2 MDC_SDIN 9 10
<14> PCH_AZ_MDC_SDIN1 IAC_SDATA_IN GND4

4.7U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
+5V_ALW RH37 33_0402_5%~D PCH_AZ_MDC_RST1# 11 12 PCH_AZ_MDC_BITCLK <14> 1 1
Q44 IAC_RESET# IAC_BITCLK
G
2

C676
SSM3K7002FU_SC70-3~D

C675
R751

GND
GND
GND
GND
GND
GND
1

100K_0402_5%~D 2 2
R752
10K_0402_5%~D TYCO_1-1775149-2~D
2

13
14
15
16
17
18
2

<40> MDC_RST_DIS# C677 Connector for MDC Rev1.5

10P_0402_50V8J~D
PCH_AZ_MDC_BITCLK 2 1 BITCLK_TERM 1 2
R753 10_0402_5%~D
A PCH_AZ_MDC_SDOUT 2 A
1 SDOUT_TERM 1 2
R754 10_0402_5%~D
C678
10P_0402_50V8J~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 45 of 77
5 4 3 2 1
 5 4 3 2 1

D D

power 20mil

JSF1 CONN@
<18> IO1_LOOP# 1 1
<40,44> LID_CL# 2 2
+3.3V_ALW 3 3
<40> WIRELESS_ON#/OFF 4 4
5 5 G1 7
6 6 G2 8

TYCO_2041084-6~D
normal trace 50ohm

SNIFFER /Hall SENSOR IO BOARD

C C

USBx2 /CRT/ AUDIO JACK IO BOARD

TYCO_2041300-2

MEDIA BOARD
65 GND GND 66
63 GND GND 64
61 GND GND 62

59 59 60 60
<17> USBP2+ 57 57 58 58 1 +5V_ALW
<17> USBP2- 55 55 56 56
CONN@ 53 54 C1183
B JLED1 53 54 0.1U_0402_16V4Z~D B
<17> USBP3+ 51 51 52 52
MEDIA_DET# 2
<18> MEDIA_DET# 1 1 <17> USBP3- 49 49 50 50
2 2 47 47 48 48
RED_CRT
Defult on, 3
4
3 <25> RED_CRT 45
43
45 46 46
44
4 43 44
WIRELESS_ON/OFF#: 5 5 <25> GREEN_CRT GREEN_CRT 41 41 42 42 +5V_RUN
6 39 40
LOW: ON <44> R_SPK_LED# 7
6
7 <25> BLUE_CRT
BLUE_CRT 37
39
37
40
38 38 +3.3V_RUN
BATT_YELLOW 8 35 36
HIGH: OFF <44> BATT_YELLOW
BATT_WHITE 9
8 DAT_DDC2_CRT 33
35 36
34
<44> BATT_WHITE 9 <25> DAT_DDC2_CRT 33 34
SATA_LED 10 CLK_DDC2_CRT 31 32
<44> SATA_LED 10 <25> CLK_DDC2_CRT 31 32
WIRELESS_LED 11 29 30
<44> WIRELESS_LED 11 29 30
MIC_MUTE# 12 <25> HSYNC_BUF HSYNC_BUF 27 28
<40> MIC_MUTE# VOL_MUTE 12 VSYNC_BUF 27 28 MIC_IN_R
<41> VOL_MUTE 13 13 <25> VSYNC_BUF 25 25 26 26 MIC_IN_R <30>
VOL_DOWN 14 23 24
<41> VOL_DOWN VOL_UP 14 23 24 AUD_HP_OUT_R
<41> VOL_UP 15 15 <40> USB_SIDE_EN# 21 21 22 22 AUD_HP_OUT_R <30>
16 16 <17> USB_OC1# 19 19 20 20
17 17 18 18
17 AUD_HP_NB_SENSE 15 16
GND <30,40> AUD_HP_NB_SENSE 15 16 AUD_HP_OUT_L
18 GND 13 13 14 14 AUD_HP_OUT_L <30>
IO_LOOP# 11 12
TYCO_1-2041084-6 <18> IO_LOOP# AUD_MIC_SWITCH 11 12
<30> AUD_MIC_SWITCH 9 9 10 10
7 7 8 8
5 5 6 6
3 3 4 4
1 1 2 2
JBTB1 CONN@

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 46 of 77
5 4 3 2 1
 5 4 3 2 1

UV1A
Part 1 of 5
PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_P0 AE12 N1
<6> PEG_CTX_GRX_P[0..15] PEX_RX0 GPIO0
PEG_CTX_GRX_N0 AF12 G1 DPC_GPU_HPD BIA_PWM_GPU 1 2
PEG_CTX_GRX_N[0..15] PEX_RX0_N GPIO1 DPC_GPU_HPD <39>
PEG_CTX_GRX_P1 AG12 C1 BIA_PWM_GPU BIA_PWM_GPU <24> @ RV2 10K_0402_5%~D
<6> PEG_CTX_GRX_N[0..15] PEX_RX1 GPIO2
PEG_CTX_GRX_N1 AG13 M2 ENVDD_GPU ENVDD_GPU <24>
PEG_CRX_GTX_P[0..15] PEG_CTX_GRX_P2 PEX_RX1_N GPIO3 PANEL_BKEN_DGPU ENVDD_GPU
<6> PEG_CRX_GTX_P[0..15] AF13 PEX_RX2 GPIO4 M3 PANEL_BKEN_DGPU <24> 1 2
PEG_CTX_GRX_N2 AE13 K3 GPU_VID_0 GPU_VID_0 <64> RV1 10K_0402_5%~D
PEG_CRX_GTX_N[0..15] PEG_CTX_GRX_P3 PEX_RX2_N GPIO5 GPU_VID_1
<6> PEG_CRX_GTX_N[0..15] AE15 PEX_RX3 GPIO6 K2 GPU_VID_1 <64>
PEG_CTX_GRX_N3 AF15 J2 PANEL_BKEN_DGPU 1 2
D PEG_CTX_GRX_P4 PEX_RX3_N GPIO7 THERMTRIP_VGA# @ RV14 10K_0402_5%~D D
AG15 PEX_RX4 GPIO8 C2 THERMTRIP_VGA# <22>

GPIO
PEG_CTX_GRX_N4 AG16 M1 GPU_GPIO9
PEG_CTX_GRX_P5 PEX_RX4_N GPIO9
AF16 PEX_RX5 GPIO10 D2
PEG_CTX_GRX_N5 AE16 D1
PEG_CRX_GTX_P0 0.22U_0402_16V7K~D CV1 PEG_CRX_GTX_C_P0 PEG_CTX_GRX_P6 PEX_RX5_N GPIO11 GPU_CLKDWN_R
2 1 AE18 PEX_RX6 GPIO12 J3 1 2 GPU_CLKDWN <40> Close to GPU
PEG_CRX_GTX_N0 0.22U_0402_16V7K~D 2 1 CV2 PEG_CRX_GTX_C_N0 PEG_CTX_GRX_N6 AF18 J1 @ RV20 0_0402_5%~D
PEG_CTX_GRX_P7 PEX_RX6_N GPIO13
AG18 PEX_RX7 GPIO14 K1
PEG_CRX_GTX_P1 0.22U_0402_16V7K~D 2 1 CV4 PEG_CRX_GTX_C_P1 PEG_CTX_GRX_N7 AG19 F3 DPE_GPU_HPD GPU_CRT_RED 1 2
PEX_RX7_N GPIO15 DPE_GPU_HPD <26>
PEG_CRX_GTX_N1 0.22U_0402_16V7K~D 2 1 CV3 PEG_CRX_GTX_C_N1 PEG_CTX_GRX_P8 AF19 G3 GPU_DEEP_CLKDWN_R 1 2 RV3 150_0402_1%~D
PEX_RX8 GPIO16 GPU_DEEP_CLKDWN <40>
PEG_CTX_GRX_N8 AE19 G2 @ RV25 0_0402_5%~D GPU_CRT_GRN 1 2
PEG_CRX_GTX_P2 0.22U_0402_16V7K~D CV5 PEG_CRX_GTX_C_P2 PEG_CTX_GRX_P9 PEX_RX8_N GPIO17 DGPU_DI_INT#_R RV4 150_0402_1%~D
2 1 AE21 PEX_RX9 GPIO18 F1 1 2 DGPU_DI_INT# <40>
PEG_CRX_GTX_N2 0.22U_0402_16V7K~D 2 1 CV6 PEG_CRX_GTX_C_N2 PEG_CTX_GRX_N9 AF21 F2 DPD_GPU_HPD @ RV26 0_0402_5%~D GPU_CRT_BLU 1 2
PEX_RX9_N GPIO19 DPD_GPU_HPD <39>
PEG_CTX_GRX_P10 AG21 RV5 150_0402_1%~D
PEG_CRX_GTX_P3 0.22U_0402_16V7K~D CV7 PEG_CRX_GTX_C_P3 PEG_CTX_GRX_N10 PEX_RX10 GPU_CRT_HSYNC
2 1 AG22 PEX_RX10_N DACA_HSYNC AD2 GPU_CRT_HSYNC <25>
PEG_CRX_GTX_N3 0.22U_0402_16V7K~D 2 1 CV8 PEG_CRX_GTX_C_N3 PEG_CTX_GRX_P11 AF22 AD1 GPU_CRT_VSYNC
PEX_RX11 DACA_VSYNC GPU_CRT_VSYNC <25>
PEG_CTX_GRX_N11

DACA
AE22 PEX_RX11_N
PEG_CRX_GTX_P4 0.22U_0402_16V7K~D 2 1 CV9 PEG_CRX_GTX_C_P4 PEG_CTX_GRX_P12 AE24 AE2 GPU_CRT_RED
PEX_RX12 DACA_RED GPU_CRT_RED <25>
PEG_CRX_GTX_N4 0.22U_0402_16V7K~D 2 1 CV10 PEG_CRX_GTX_C_N4 PEG_CTX_GRX_N12 AF24 AD3 GPU_CRT_BLU
PEX_RX12_N DACA_BLUE GPU_CRT_BLU <25>
PEG_CTX_GRX_P13 AG24 AE3 GPU_CRT_GRN DPC_GPU_HPD 2 1
PEX_RX13 DACA_GREEN GPU_CRT_GRN <25> DP_HDMI_HPD <40>
PEG_CRX_GTX_P5 0.22U_0402_16V7K~D 2 1 CV11 PEG_CRX_GTX_C_P5 PEG_CTX_GRX_N13 AF25 DV2 RB751V-40GTE-17_SOD323-2~D
PEG_CRX_GTX_N5 0.22U_0402_16V7K~D CV12 PEG_CRX_GTX_C_N5 PEG_CTX_GRX_P14 PEX_RX13_N DACA_VREF CV13 1
2 1 AG25 PEX_RX14 DACA_VREF AF1 2 0.1U_0402_10V7K~D
PEG_CTX_GRX_N14 AG26 AE1 DACA_RSET 1 2 DPD_GPU_HPD 2 1

PCI EXPRESS
PEG_CRX_GTX_P6 0.22U_0402_16V7K~D CV14 PEG_CRX_GTX_C_P6 PEG_CTX_GRX_P15 PEX_RX14_N DACA_RSET RV6 124_0402_1%~D DV3 RB751V-40GTE-17_SOD323-2~D
2 1 AF27 PEX_RX15
PEG_CRX_GTX_N6 0.22U_0402_16V7K~D 2 1 CV15 PEG_CRX_GTX_C_N6 PEG_CTX_GRX_N15 AE27 U6
PEX_RX15_N DACB_HSYNC DPE_GPU_HPD
DACB_VSYNC U4 2 1
PEG_CRX_GTX_P7 0.22U_0402_16V7K~D 2 1 CV16 PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_P0 AD10 DV4 RB751V-40GTE-17_SOD323-2~D

DACB
PEG_CRX_GTX_N7 0.22U_0402_16V7K~D CV17 PEG_CRX_GTX_C_N7 PEG_CRX_GTX_C_N0 PEX_TX0
2 1 AD11 PEX_TX0_N DACB_RED T5
PEG_CRX_GTX_C_P1 AD12 R4
PEG_CRX_GTX_P8 0.22U_0402_16V7K~D CV18 PEG_CRX_GTX_C_P8 PEG_CRX_GTX_C_N1 PEX_TX1 DACB_BLUE
2 1 AC12 PEX_TX1_N DACB_GREEN T4
PEG_CRX_GTX_N8 0.22U_0402_16V7K~D 2 1 CV19 PEG_CRX_GTX_C_N8 PEG_CRX_GTX_C_P2 AB11
PEG_CRX_GTX_C_N2 PEX_TX2
AB12 PEX_TX2_N DACB_VREF R6
PEG_CRX_GTX_P9 0.22U_0402_16V7K~D 2 1 CV20 PEG_CRX_GTX_C_P9 PEG_CRX_GTX_C_P3 AD13 V6 +3.3V_RUN_GFX
C PEG_CRX_GTX_N9 0.22U_0402_16V7K~D CV21 PEG_CRX_GTX_C_N9 PEG_CRX_GTX_C_N3 PEX_TX3 DACB_RSET C
2 1 AD14 PEX_TX3_N
PEG_CRX_GTX_C_P4 AD15
PEG_CRX_GTX_P10 0.22U_0402_16V7K~D CV22 PEG_CRX_GTX_C_P10 PEG_CRX_GTX_C_N4 PEX_TX4
2 1 AC15 PEX_TX4_N
PEG_CRX_GTX_N10 0.22U_0402_16V7K~D 2 1 CV23 PEG_CRX_GTX_C_N10 PEG_CRX_GTX_C_P5 AB14 AF3 GPU_JTAG_TCK @ TV1
PEX_TX5 JTAG_TCK

1
PEG_CRX_GTX_C_N5 AB15 AG4 GPU_JTAG_TDI @ TV2
PEG_CRX_GTX_P11 0.22U_0402_16V7K~D CV24 PEG_CRX_GTX_C_P11 PEG_CRX_GTX_C_P6 PEX_TX5_N JTAG_TDI GPU_JTAG_TDO @ TV3 @ RV7
2 1 AC16 AE4

TEST
PEG_CRX_GTX_N11 0.22U_0402_16V7K~D CV25 PEG_CRX_GTX_C_N11 PEG_CRX_GTX_C_N6 PEX_TX6 JTAG_TDO GPU_JTAG_TMS @ TV4 10K_0402_5%~D
2 1 AD16 PEX_TX6_N JTAG_TMS AF4
PEG_CRX_GTX_C_P7 AD17 AG3 GPU_JTAG_TRST# 1 2
PEG_CRX_GTX_P12 0.22U_0402_16V7K~D CV26 PEG_CRX_GTX_C_P12 PEG_CRX_GTX_C_N7 PEX_TX7 JTAG_TRST_N RV9 1K_0402_1%~D
2 1 AD18

2
PEG_CRX_GTX_N12 0.22U_0402_16V7K~D CV27 PEG_CRX_GTX_C_N12 PEG_CRX_GTX_C_P8 PEX_TX7_N GPU_TESTMODE GPU_TESTMODE
2 1 AC18 PEX_TX8 TESTMODE AD25
PEG_CRX_GTX_C_N8 AB18
PEG_CRX_GTX_P13 0.22U_0402_16V7K~D CV28 PEG_CRX_GTX_C_P13 PEG_CRX_GTX_C_P9 PEX_TX8_N
2 1 AB19 PEX_TX9

1
PEG_CRX_GTX_N13 0.22U_0402_16V7K~D 2 1 CV29 PEG_CRX_GTX_C_N13 PEG_CRX_GTX_C_N9 AB20
PEG_CRX_GTX_C_P10 PEX_TX9_N GPU_CRT_CLK_DDC_R RV8
AD19 PEX_TX10 I2CA_SCL R1 1 2 GPU_CRT_CLK_DDC <25>
PEG_CRX_GTX_P14 0.22U_0402_16V7K~D 2 1 CV30 PEG_CRX_GTX_C_P14 PEG_CRX_GTX_C_N10 AD20 T3 GPU_CRT_DAT_DDC_R RV10 1 2 33_0402_5%~D 10K_0402_5%~D
PEX_TX10_N I2CA_SDA GPU_CRT_DAT_DDC <25>
PEG_CRX_GTX_N14 0.22U_0402_16V7K~D 2 1 CV31 PEG_CRX_GTX_C_N14 PEG_CRX_GTX_C_P11 AD21 RV11 33_0402_5%~D
PEG_CRX_GTX_C_N11 PEX_TX11 I2CB_SCL
AC21 R2

2
PEG_CRX_GTX_P15 0.22U_0402_16V7K~D CV32 PEG_CRX_GTX_C_P15 PEG_CRX_GTX_C_P12 PEX_TX11_N I2CB_SCL I2CB_SDA
2 1 AB21 PEX_TX12 I2CB_SDA R3
PEG_CRX_GTX_N15 0.22U_0402_16V7K~D 2 1 CV33 PEG_CRX_GTX_C_N15 PEG_CRX_GTX_C_N12 AB22
PEG_CRX_GTX_C_P13 PEX_TX12_N LDDC_CLK_GPU
AC22 PEX_TX13 I2CC_SCL A2 LDDC_CLK_GPU <23>

I2C
PEG_CRX_GTX_C_N13 AD22 B1 LDDC_DATA_GPU LDDC_DATA_GPU <23>
PEG_CRX_GTX_C_P14 PEX_TX13_N I2CC_SDA
AD23 PEX_TX14
PEG_CRX_GTX_C_N14 AD24 A3 I2CH_SCL
PEG_CRX_GTX_C_P15 PEX_TX14_N GPIO20 I2CH_SDA
AE25 PEX_TX15 GPIO21 A4 FERMI Changed
PEG_CRX_GTX_C_N15 AE26 PEX_TX15_N GPU_SMBCLK
I2CS_SCL T1 GPU_SMBCLK <41>
AB10 T2 GPU_SMBDAT
<15> CLK_PCIE_VGA PEX_REFCLK I2CS_SDA GPU_SMBDAT <41>
<15> CLK_PCIE_VGA# AC10 PEX_REFCLK_N
1 2 PEX_TSTCLK_OUT AF10
Differential signal @ RV13 200_0402_1%~D PEX_TSTCLK_OUT# AE10
PEX_TSTCLK_OUT
D11 XTALSSIN 1 2
PEX_TSTCLK_OUT_N XTAL_SSIN RV12 10K_0402_5%~D
B XTALOUTBUFF B
2 1 AG10 PEX_TERMP XTAL_OUTBUFF E9 1 2
RV15 2.49K_0402_1%~D RV16 10K_0402_5%~D
DGPU_PEX_RST 1 2 DGPU_PEX_RST_R AD9 E10 1 2 NV_CLK_27M_OUT

CLK
@RV18
@ RV18 0_0402_5%~D PEX_RST_N XTAL_OUT @RV19
@ RV19 0_0402_5%~D
+3.3V_RUN_GFX 1 2 CLK_REQ# AE9 D10 CLK_27M_IN
RV21 10K_0402_5%~D PEX_CLKREQ_N XTAL_IN

N12P-NS-S-A1_BGA533~D

YV1 27MHZ_10PF_X3S027000BA1H-U~D
CLK_27M_IN 1 3 NV_CLK_27M_OUT
2 G1 +3.3V_RUN_GFX
G2 4

18P_0402_50V8J~D

18P_0402_50V8J~D
+3.3V_RUN
1 1

CV34

CV35
+3.3V_RUN +3.3V_RUN_GFX 1 2 GPU_CRT_CLK_DDC
2

@ RV30 RV23 @ 4.7K_0402_5%~D

1

2 2 GPU_CRT_DAT_DDC
1 2 1 2
100K_0402_5%~D @ CV188 0.1U_0402_16V4Z~D RV29 RV24 @ 4.7K_0402_5%~D
2.2K_0402_5%~D 1 2 I2CH_SCL
5

RV100 @ 10K_0402_5%~D
1

1 1 2 I2CH_SDA FERMI Changed

P

<17> PLTRST_GPU#
2

B DGPU_PEX_RST RV101 @ 10K_0402_5%~D

O 4
<18> DGPU_HOLD_RST# 2 2 1 I2CB_SCL
A
G

RV27 2.2K_0402_5%~D
74AHC1G09GW_TSSOP5~D 2 1 I2CB_SDA
3
2

RV22 UV14 RV28 2.2K_0402_5%~D

1 2 GPU_GPIO9
100K_0402_5%~D RV102 10K_0402_5%~D
1 2 GPU_CLKDWN_R
RV104 10K_0402_5%~D
1

A A
1 2
@ DV1
RB751V-40GTE-17_SOD323-2~D

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 47 of 77
5 4 3 2 1
 5 4 3 2 1

UV1C
Part 3 of 5
AC4 C15 GB1B-64 : PGOOD
<23> LCD_ACLK+_GPU IFPA_TXC NC
<23> LCD_ACLK-_GPU AD4 IFPA_TXC_N NC D15

NC
V5 J5 1 2 UV1E
<23> LCD_A0+_GPU IFPA_TXD0 PGOOD RV105 Part 5 of 5
<23> LCD_A0-_GPU V4 IFPA_TXD0_N B2 GND GND U2
AA5 10K_0402_5%~D B5 U5
<23> LCD_A1+_GPU IFPA_TXD1 GND GND
<23> LCD_A1-_GPU AA4 IFPA_TXD1_N B8 GND GND U11
<23> LCD_A2+_GPU W4 IFPA_TXD2 B11 GND GND U12
<23> LCD_A2-_GPU Y4 IFPA_TXD2_N MULTI_STRAP_REF2_GND T6 1 2 B14 GND GND U13
AB4 W6 RV106 B17 U14

DBG
D IFPA_TXD3 DBG_DATA1 40.2K_0402_1%~D GND GND D
AB5 IFPA_TXD3_N DBG_DATA2 Y6 B20 GND GND U15
DBG_DATA3 AA6 B23 GND GND U16
DBG_DATA4 N3 B26 GND GND U17
AB3 GB1B-64 : MULTI_STRAP_REF2_GND E2 U23
<23> LCD_BCLK+_GPU IFPB_TXC GND GND
<23> LCD_BCLK-_GPU AB2 IFPB_TXC_N E5 GND GND U26
<23> LCD_B0+_GPU W1 IFPB_TXD4 E8 GND GND V9
V1 C7 STRAP0 E11 V19
<23> LCD_B0-_GPU IFPB_TXD4_N STRAP0 GND GND
W3 E17 W11

STRAP
LVDS / TMDS
<23> LCD_B1+_GPU IFPB_TXD5 STRAP1 GND GND
<23> LCD_B1-_GPU W2 IFPB_TXD5_N STRAP1 B9 E20 GND GND W14
<23> LCD_B2+_GPU AA2 IFPB_TXD6 E23 GND GND W17
AA3 A9 STRAP2 E26 Y2
<23> LCD_B2-_GPU IFPB_TXD6_N STRAP2 GND GND
AB1 IFPB_TXD7 H2 GND GND Y5

GND
AA1 IFPB_TXD7_N H5 GND GND Y23
J11 GND GND Y26
J14 GND GND AC2
DPC_GPU_AUX/DDC G4 N5 J17 AC5
<27> DPC_GPU_AUX/DDC IFPC_AUX_I2CW_SCL BUFRST_N GND GND
DPC_GPU_AUX#/DDC G5 K9 AC6
<27> DPC_GPU_AUX#/DDC IFPC_AUX_I2CW_SDA_N GND GND
<39> DPC_GPU_LANE_P0 P4 IFPC_L0 VGA_THERMDN <22> K19 GND GND AC8
TO DOCKING <39> DPC_GPU_LANE_N0 N4 IFPC_L0_N 1 L2 GND GND AC11

GENERAL
M5 D8 @ L5 AC14
<39> DPC_GPU_LANE_P1 IFPC_L1 THERMDN CV37 GND GND
<39> DPC_GPU_LANE_N1 M4 IFPC_L1_N L11 GND GND AC17
L4 D9 100P_0402_50V8K~D L12 AC20
<39> DPC_GPU_LANE_P2 IFPC_L2 THERMDP 2 GND GND
<39> DPC_GPU_LANE_N2 K4 IFPC_L2_N VGA_THERMDP <22> L13 GND GND AC23
<39> DPC_GPU_LANE_P3 H4 IFPC_L3 L14 GND GND AC26
<39> DPC_GPU_LANE_N3 J4 IFPC_L3_N L15 GND GND AF2
N2 STRAP4 L16 AF5
STRAP4 GND GND
DPD_GPU_AUX/DDC D3 F9 STRAP3
Fermi changed L17
M12
GND GND AF8
AF11
<27> DPD_GPU_AUX/DDC IFPD_AUX_I2CX_SCL STRAP3 GND GND
DPD_GPU_AUX#/DDC D4 M13 AF14
<27> DPD_GPU_AUX#/DDC IFPD_AUX_I2CX_SDA_N GND GND
<39> DPD_GPU_LANE_P0 F5 IFPD_L0 M14 GND GND AF17
<39> DPD_GPU_LANE_N0 F4 IFPD_L0_N M15 GND GND AF20
TO DOCKING <39> DPD_GPU_LANE_P1 E4 IFPD_L1 ROM_CS_N B10 M16 GND GND AF23
C C
<39> DPD_GPU_LANE_N1 D5 IFPD_L1_N P2 GND GND AF26

SERIAL
C3 C9 ROM_SCLK_GPU P5 T16
<39> DPD_GPU_LANE_P2 IFPD_L2 ROM_SCLK GND GND
<39> DPD_GPU_LANE_N2 C4 IFPD_L2_N P9 GND GND T15
B3 A10 ROM_SI_GPU P19 T14
<39> DPD_GPU_LANE_P3 IFPD_L3 ROM_SI GND GND
<39> DPD_GPU_LANE_N3 B4 IFPD_L3_N P23 GND GND F6
C10 ROM_SO_GPU P26
ROM_SO GND
T12 GND FB_CAL_PU_GND A15 1 2
TMDS_E_GPU_DDC F7 T13 RV42 40.2_0402_1%~D
<26> TMDS_E_GPU_DDC TMDS_E_GPU_DDC# IFPE_AUX_I2CY_SCL GND
<26> TMDS_E_GPU_DDC# G6 IFPE_AUX_I2CY_SDA_N FB_CAL_TERM_GND B16 1 2
D6 RV43 60.4_0402_1%~D
<26> TMDSE_GPU_P2 IFPE_L0
<26> TMDSE_GPU_N2 C6 IFPE_L0_N IFPAB_RSET AB6 1 2 W16 GND_SENSE MULTI_STRAP_REF0_GND F11 1 2
A6 @RV32
@ RV32 1K_0402_1%~D RV44 40.2K_0402_1%~D
TO MB HDMI <26> TMDSE_GPU_P1
A7
IFPE_L1
R5 1 2 E14 F10 1 2
<26> TMDSE_GPU_N1 IFPE_L1_N IFPC_RSET RV45 1K_0402_1%~D <64> GPU_GND_SENSE GND_SENSE MULTI_STRAP_REF1_GND RV46 40.2K_0402_1%~D
<26> TMDSE_GPU_P0 B6 IFPE_L2
<26> TMDSE_GPU_N0 B7 IFPE_L2_N IFPD_RSET M6 1 2
E6 RV47 1K_0402_1%~D N12P-NS-S-A1_BGA533~D
<26> TMDSE_GPU_CLK IFPE_L3
<26> TMDSE_GPU_CLK# E7 IFPE_L3_N IFPE_RSET F8 1 2
RV48 1K_0402_1%~D

N12P-NS-S-A1_BGA533~D

+3.3V_RUN_GFX
Decive ID change to 0x1056 for QS sample
34.8K_0402_1%~D
10K_0402_1%~D
4.99K_0402_1%~D

4.99K_0402_1%~D

10K_0402_1%~D
45.3K_0402_1%~D

34.8K_0402_1%~D

45.3K_0402_1%~D
2

set to multi-level straps

RV52

@ RV53

RV54
RV49

RV50

RV51

RV97

@ RV98

1 2 DPC_GPU_AUX/DDC
RV38 100K_0402_5%~D
@ @ 1 2 DPC_GPU_AUX#/DDC
1

B RV37 100K_0402_5%~D B

STRAP0 1 2 DPD_GPU_AUX/DDC
STRAP1 RV35 100K_0402_5%~D
STRAP2 1 2 DPD_GPU_AUX#/DDC
ROM_SCLK_GPU RV36 100K_0402_5%~D
ROM_SI_GPU
ROM_SO_GPU RV39
STRAP3 2.2K_0402_5%~D
STRAP4 1 2 TMDS_E_GPU_DDC
2

2
15K_0402_1%~D

15K_0402_1%~D

20K_0402_1%~D
34.8K_0402_1%~D

34.8K_0402_1%~D

4.99K_0402_1%~D
10K_0402_1%~D
4.99K_0402_1%~D

+3.3V_RUN_GFX 1 2 TMDS_E_GPU_DDC#
2

RV40
@ RV55

RV60
RV56

RV57

RV58

@X76 RV59

RV41

RV99

2.2K_0402_5%~D
1

@ @ @
1

Resistor Values Pull-up to +3V Pull-down to Gnd

5K 01111 11111
10K 01110 11110 ROM_SCLK PCIDEVID_EXT, SUB_VENDOR, SLOT_CLK, PEX_PLL_EN
15K 01011 11011
20K 01001 11001
ROM_SI RAM_CFG[3:0]
Hynix 64Mx16 DDR3 part stuff RV59=15K
** Samsung 64Mx16 DDR3 part stuff RV59=20K 25K 00111 10111 ROM_SO XCLK_417, FB_0_BAR_SIZE, ALT_ADOOR, VGA_DEVICE
A
30K 00110 10110 A
Hynix 128Mx16 DDR3 part stuff RV59=35K 35K 00011 10011
Samsung 128Mx16 DDR3 part stuff RV59=45.3K 45K 00000 100000

STRAP0 USER[3:0]
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
STRAP1 3GIO_PADCFG_LUT_ADR[3:0] TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
STRAP2 PCI_DEVID[3:0] PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 48 of 77
5 4 3 2 1
 5 4 3 2 1

UV1D
Part 4 of 5 ClosetoPin C1747tobeclosetotheGPU
add for GB1b-64 +GPU_CORE J9 A13
VDD FBVDDQ 2.97A
J10 VDD FBVDDQ B13 +1.5V_MEM_GFX
J12 VDD FBVDDQ C13
1 1 1 1 1 J13 VDD FBVDDQ D13 1 1 1 1 1 1
1 @ 1 @ L9 D14
VDD FBVDDQ
M9 E13

CV47
CV48
CV39
VDD FBVDDQ

CV164
CV163
CV162
CV161
CV160
M11 F13

CV44
CV38
CV45
CV46
2 2 2 2 2 VDD FBVDDQ 2 2 2 2 2 2

CV159
M17 VDD FBVDDQ F14 N10M SPEC FBVDDQ TYP. 1.8V.
2 2
N9 VDD FBVDDQ F15
N11 F16

1U_0402_6.3V6K~D
VDD FBVDDQ

10U_0805_6.3V6M~D

1U_0603_10V7K~D
1U_0603_10V7K~D
1U_0603_10V7K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
N12 F17

0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
VDD FBVDDQ

22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
N13 VDD FBVDDQ F19
N14 VDD FBVDDQ F22 +1.5V_MEM_GFX
D D
N15 VDD FBVDDQ H23
N16 VDD FBVDDQ H26 1 1 1 1 1 1

@
N17 VDD FBVDDQ J15
N19 J16

CV52
CV53
CV54
CV55
CV57
1 1 1 1 1 1 1 VDD FBVDDQ
P11 J18

@CV56
CV56
VDD FBVDDQ 2 2 2 2 2 2
P12 J19

CV49
CV40
CV50
CV41
CV51
CV42
CV43
VDD FBVDDQ
P13 VDD FBVDDQ L19
2 2 2 2 2 2 2
P14 L23

1U_0402_6.3V6K~D
VDD FBVDDQ

10U_0805_6.3V6M~D

4.7U_0603_6.3V6K~D
P15 VDD FBVDDQ L26

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
P16 VDD FBVDDQ M19
+1.05V_RUN_VTT_GFX

0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
P17 VDD FBVDDQ N22
R9 VDD FBVDDQ U22
R11 VDD FBVDDQ Y22
R12 VDD
R13 VDD PEX_IOVDDQ AG6
R14 VDD PEX_IOVDDQ AF6 1 1 1 1 1 1 1
1 1 1 R15 VDD PEX_IOVDDQ AE6
R16 AD6

CV61
CV62
CV63
CV64
CV65
CV66
CV67
under GPU VDD PEX_IOVDDQ

POWER
R17 AC13

CV58
CV59
CV60
VDD PEX_IOVDDQ 2 2 2 2 2 2 2
T9 VDD PEX_IOVDDQ AC7
2 2 2
T11 AB17

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_4VAM~D
VDD 2A PEX_IOVDDQ

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
22U_0805_6.3VAM~D
NV DG for VDD Cap: T17 VDD PEX_IOVDDQ AB16

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.01uF 10% X7R x6 U9 VDD PEX_IOVDDQ AB13
U19 AB9 +1.05V_RUN_VTT_GFX
0.047uF 10% X7R x3 +3.3V_RUN_GFX LV1 220R 100MHZ VDD PEX_IOVDDQ PLACECLOSETOBALL PLACENEARGPU
W9 VDD PEX_IOVDDQ AB8
0.1uF 10% X7R x1 BLM18PG221SN1D_2P~D W10 AB7
+3.3V_RUN_VDD33 VDD PEX_IOVDDQ
4.7uF 10% X5R x1 1 2 W12 VDD
W13 VDD PEX_IOVDD AG7 1 1 1 1 1 1 1
For GB1b-64 add: W18 AF7
4.7u X5R x1 VDD PEX_IOVDD
W19 AE7

CV70
CV71
CV72
CV73
CV77
CV78
CV79

1 1 1 1 1 VDD PEX_IOVDD
PEX_IOVDD AD8
2A 2 2 2 2 2 2 2
PEX_IOVDD AD7
C 120mA C
A12 AC9

CV74
CV75
CV68
CV76
CV69
2 2 2 2 2 VDD33 PEX_IOVDD
B12

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_4VAM~D

VDD33

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
22U_0805_6.3VAM~D

C12 VDD33 PEX_PLLVDD AF9 +PEX_PLLVDD

D12

1U_0402_6.3V6K~D
VDD33

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
E12 VDD33 VID_PLLVDD K6
F12
45mA
+3.3V_RUN_GFX VDD33 45mA +PLLVDD 120mA
SP_PLLVDD L6

1 2 +3.3V_RUN_PEX_SVDD_3V3 120mA AG9 K5

60mA PLACENEARGPU
LV2
PEX_SVDD_3V3 PLLVDD
PJP70 +FB_AVDD
20 mil
1 1 FB_PLLAVDD R19 2 1 +1.05V_RUN_VTT_GFX
PAD-OPEN1x1m V3 100mA
IFPA_IOVDD BLM18PG300SN1D_2P~D
AC19

CV81
??mA FB_PLLAVDD 1 1
+IFPAB_IOVDD V2

CV80
2 2 IFPB_IOVDD 1
T19
CV83

285mA FB_DLLAVDD 100mA

J6
CV82

IFPCD_IOVDD 2 2
CV165

0.1U_0402_16V4Z~D
285mA +IFPCDE_IOVDD +DACA_VDD

4.7U_0603_6.3V6K~D
H6 IFPE_IOVDD DACA_VDD AG2
0.1U_0402_10V7K~D

1U_0603_10V6K~D

W5 1 2
10U_0805_4VAM~D

+IFPAB_PLLVDD DACB_VDD RV63 10K_0402_5%~D

AD5 IFPAB_PLLVDD
??mA add for GB1b-64
+IFPCD_PLLVDD P6 B15 +1.5V_MEM_VDDQ 2 1 +1.5V_MEM_GFX
220mA IFPC_PLLVDD FB_CAL_PD_VDDQ RV65 40.2_0402_1%~D
N6 IFPD_PLLVDD VDD_SENSE W15 GPU_VDD_SENSE <64>
220mA
+IFPE_PLLVDD D7 E15
+1.8V_RUN_GFX 220R 100MHZ 285mA 220mA IFPE_PLLVDD VDD_SENSE
route as 50ohm
LV11 BLM18PG221SN1D_2P~D
2 1 +IFPAB_IOVDD N12P-NS-S-A1_BGA533~D

B B
1 1 1 1 1 1

CV175
CV166
CV174
CV170
+1.05V_RUN_VTT_GFX 180R 100MHZ add for GB1b-64 LV4
2 2 2 2 2 2

CV173
CV172
120mA BLM18AG121SN1D_0603~D
LV3 150mA,10mil +PEX_PLLVDD 2 1 +1.05V_RUN_VTT_GFX
LV6 2 1 +PLLVDD

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+3.3V_RUN_GFX

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
MMZ1608D301BT_0603 220mA 1 BLM18PG221SN1D_2P~D 1 1 1 1
1 2 +IFPCD_PLLVDD 1 1 1 1 1

CV84
CV90
CV93
CV91

+1.05V_RUN_VTT_GFX 220R 100MHZ 285mA

CV87
CV88
CV92

2 2 2 2 2
CV179
CV180
CV181

LV9 BLM18PG221SN1D_2P~D 1 1 1 1 1 1
+IFPCDE_IOVDD 2 2 2 2 2
2 1
0.1U_0402_10V7K~D
1U_0603_10V6K~D

CV94
CV95
CV96
CV97
CV98
CV99
4.7U_0805_10V7K~D
4.7U_0603_6.3V6K~D

1U_0402_6.3V6K~D
2 2 2 2 2 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3VAM~D

1 1 1 1 1 1

1U_0603_10V6K~D

4.7U_0603_6.3V6K~D

CV119
CV121
CV122
CV123
4.7U_0805_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2 2 2 2 2 2
add for GB1b-64

CV118
CV120
300ohm 100MHz ESR0.25ohm
add for GB1b-64 120mA add for GB1b-64 +3.3V_RUN_GFX
+DACA_VDD 1 2

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
LV7

4.7U_0603_6.3V6K~D
MMZ1608D301BT_0603

1 1 1 1 1 1 1
+3.3V_RUN_GFXLV5 220mA
MMZ1608D301BT_0603
CV107
CV109
CV110
CV108
CV112
CV113
CV114

1 2 +IFPE_PLLVDD
+1.05V_RUN_VTT_GFX 285mA 2 2 2 2 2 2 2
LV10
1U_0402_6.3V6K~D

A A
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D

+IFPAB_PLLVDD
4.7U_0603_6.3V6K~D

2 1 1 1 1 1 1 1
4.7U_0805_10V7K~D

BLM18AG121SN1D_0603~D

CV101
CV102
CV103
CV104
CV105
CV106

1 1 1 1 2 2 2 2 2 2

CV171
CV168
CV167
1U_0603_10V6K~D
2 2 2 2

CV169
4.7U_0805_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
add for GB1b-64
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title

1U_0603_10V6K~D

1U_0402_6.3V6K~D
4.7U_0805_10V7K~D
0.1U_0402_10V7K~D
add for GB1b-64 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 49 of 77
5 4 3 2 1
 5 4 3 2 1

+1.8V_RUN_GFX Source
FBAD[0..63]
FBAD[0..63] <51,52> +1.8V_RUN +1.8V_RUN_GFX
FBA_CMD[0..30] QV7
FBA_CMD[0..30] <51,52> PMV45EN_SOT23-3~D
DQMA#[0..7]
DQMA#[0..7] <51,52>

S
1 3

10U_0805_6.3V6M~D
DQSA_RN[0..7]
DQSA_RN[0..7] <51,52>

1
20K_0402_5%~D
RV96
DQSA_WP[0..7] 1

G
DQSA_WP[0..7] <51,52>

2
1.05V_RUN_VTT_GFX#_EN 1 2 1.05V_RUN_VTT_GFX#_EN_R

CV187
RV95 0_0402_5%~D
D D

2
2
UV1B
Part 2 of 5 Mode E - Mirror Mode Mapping
FBAD0 D22 G24 FBA_CMD0
FBAD1 FBA_D0 FBA_CMD0 FBA_CMD1 PAD~D TV6@
E24 FBA_D1 FBA_CMD1 F27 DATA Bus
FBAD2 E22 F25 FBA_CMD2
FBA_CMD3 FBAD3 FBA_D2 FBA_CMD2 FBA_CMD3
D24 F26 Address 0..31 32..63
FBAD4 D26
FBA_D3
FBA_D4
FBA_CMD3
FBA_CMD4 G26 FBA_CMD4 +3.3V_RUN_GFX Source
1
10K_0402_5%~D

FBAD5 D27 G27 FBA_CMD5 CMD0 ODT_L

FBA_D5 FBA_CMD5
RV66

CKE_1 FBAD6 C27 G25 FBA_CMD6

FBAD7 FBA_D6 FBA_CMD6 FBA_CMD7 +15V_ALW +3.3V_ALW QV5 +3.3V_RUN_GFX
B27 FBA_D7 FBA_CMD7 J25 CMD1 CS1#_L
FBAD8 A21 J24 FBA_CMD8 +3.3V_ALW2 SI3456BDV-T1-E3_TSOP6~D
FBAD9 FBA_D8 FBA_CMD8 FBA_CMD9
B21 H24 CMD2 CS0#_L
2

FBA_D9 FBA_CMD9

D
FBAD10 C21 H22 FBA_CMD10 6

S
FBA_D10 FBA_CMD10

1
FBAD11 C19 J26 FBA_CMD11 CMD3 CKE_L 5 4
FBA_D11 FBA_CMD11

1
FBAD12 C18 G22 FBA_CMD12 2
FBA_D12 FBA_CMD12

1
10U_0805_6.3V6M~D

20K_0402_5%~D
FBAD13 D18 G23 FBA_CMD13 CMD4 A9 A11 RV92 RV91 1 1
FBAD14 FBA_D13 FBA_CMD13 FBA_CMD14 100K_0402_5%~D 100K_0402_5%~D
B18 J22

G
FBA_D14 FBA_CMD14

CV185

RV90
FBA_CMD19 FBAD15 C16 J27 FBA_CMD15 CMD5 A6 A7

3
FBAD16 FBA_D15 FBA_CMD15 FBA_CMD16 3.3V_RUN_GFX_EN
E21 M24

2
FBA_D16 FBA_CMD16
1

2
10K_0402_5%~D

FBAD17 F21 L24 FBA_CMD17 PAD~D TV5@ CMD6 A3 BA1

2
FBA_D17 FBA_CMD17

3
RV68

FBAD18 D20 J23 FBA_CMD18

FBA_D18 FBA_CMD18

3300P_0402_50V7K~D
ODT_2 FBAD19 F20 K23 FBA_CMD19 CMD7 A0 A12
FBAD20 FBA_D19 FBA_CMD19 FBA_CMD20 QV6B
D17 FBA_D20 FBA_CMD20 K22 1

CV186
FBAD21 F18 M23 FBA_CMD21 CMD8 A8 A8 3.3V_RUN_GFX_ON# 5 DMN66D0LDW-7_SOT363-6~D
2

FBAD22 FBA_D21 FBA_CMD21 FBA_CMD22

D16 FBA_D22 FBA_CMD22 K24

6
FBAD23 E16 M27 FBA_CMD23 CMD9 A12 A0

4
FBAD24 FBA_D23 FBA_CMD23 FBA_CMD24 QV6A 2
A22 FBA_D24 FBA_CMD24 N27
FBAD25 C24 M26 FBA_CMD25 CMD10 A1 A2 DMN66D0LDW-7_SOT363-6~D

MEMORY INTERFACE
FBAD26 FBA_D25 FBA_CMD25 FBA_CMD26
D21 FBA_D26 FBA_CMD26 K26 <15,40> 3.3V_RUN_GFX_ON 2
FBAD27 B22 K27 FBA_CMD27 CMD11 RAS# RAS#
C FBA_CMD0 FBAD28 FBA_D27 FBA_CMD27 FBA_CMD28 C
C22 K25

1
FBAD29 FBA_D28 FBA_CMD28 FBA_CMD29
A25 FBA_D29 FBA_CMD29 M25 CMD12 A13 A14
1
10K_0402_5%~D

FBAD30 B25 L22 FBA_CMD30

FBA_D30 FBA_CMD30
RV71

FBAD31 A26 CMD13 BA1 A3

FBAD32 FBA_D31 DQMA#0
ODT_1 U24 FBA_D32 FBA_DQM0 C26
FBAD33 V24 B19 DQMA#1 CMD14 A14 A13
FBAD34 V23
FBA_D33 FBA_DQM1
D19 DQMA#2 +1.5V_MEM_GFX Source
2

FBAD35 FBA_D34 FBA_DQM2 DQMA#3

R24 FBA_D35 FBA_DQM3 D23 CMD15 CAS# CAS#
FBAD36 T23 T24 DQMA#4 +3.3V_ALW2 +15V_ALW +1.5V_MEM QV1
FBA_D36 FBA_DQM4

100K_0402_5%~D
FBAD37 R23 AA23 DQMA#5 CMD16 CKE_H SI4164DY-T1-GE3_SO8~D +1.5V_MEM_GFX
FBAD38 FBA_D37 FBA_DQM5 DQMA#6
P24 FBA_D38 FBA_DQM6 AB27 8 1

1
FBAD39 P22 T26 DQMA#7 CMD17 CS1#_H 7 2
FBA_D39 FBA_DQM7

RV67
FBAD40 AC24 6 3
FBA_D40

1
100K_0402_5%~D

10U_0805_6.3V6M~D

20K_0402_5%~D
FBA_CMD16 FBAD41 AB23 D25 DQSA_RN0 CMD18 CS0#_H 5 1
FBA_D41 FBA_DQS_RN0

RV69

RV70
FBAD42 AB24 A18 DQSA_RN1
FBA_D42 FBA_DQS_RN1
1
10K_0402_5%~D

CV124
FBAD43 W24 E18 DQSA_RN2 CMD19 ODT_H

4
FBA_D43 FBA_DQS_RN2
RV72

FBAD44 AA22 B24 DQSA_RN3 GFX_MEM_VTT_EN

FBAD45 FBA_D44 FBA_DQS_RN3 DQSA_RN4 2
CKE_2 W23 R22 CMD20 RST RST

2
FBA_D45 FBA_DQS_RN4

3
DMN66D0LDW-7_SOT363-6~D
FBAD46 W22 Y24 DQSA_RN5
FBA_D46 FBA_DQS_RN5

2200P_0402_50V7K~D
FBAD47 V22 AA27 DQSA_RN6 CMD21 A7 A6
2

FBA_D47 FBA_DQS_RN6

QV2B
FBAD48 AA25 R27 DQSA_RN7
FBAD49 FBA_D48 FBA_DQS_RN7 GFX_MEM_VTT_ON# 5
W27 FBA_D49 CMD22 A4 A5 1
FBAD50 W26 C25 DQSA_WP0
FBA_D50 FBA_DQS_WP0

CV125
FBAD51 W25 A19 DQSA_WP1 CMD23 A11 A9

4
FBAD52 FBA_D51 FBA_DQS_WP1 DQSA_WP2
AB25 FBA_D52 FBA_DQS_WP2 E19

6
2

DMN66D0LDW-7_SOT363-6~D
FBAD53 AB26 A24 DQSA_WP3 CMD24 A2 A1
FBA_D53 FBA_DQS_WP3

QV2A
FBA_CMD20 FBAD54 AD26 T22 DQSA_WP4
FBAD55 FBA_D54 FBA_DQS_WP4 DQSA_WP5
AD27 FBA_D55 FBA_DQS_WP5 AA24 CMD25 A10 WE#
1
10K_0402_5%~D

FBAD56 V25 AA26 DQSA_WP6 2

FBA_D56 FBA_DQS_WP6 <40> GFX_MEM_VTT_ON
RV75

FBAD57 R25 T27 DQSA_WP7 CMD26 A5 A4

FBAD58 FBA_D57 FBA_DQS_WP7
RST V26

1
FBAD59 FBA_D58 +FB_VREF
B
V27 FBA_D59 FB_VREF A16 CMD27 BA2 A15 B
FBAD60 R26
2

FBAD61 FBA_D60
T25 FBA_D61 FBA_CLK0 F24 CLKA0 <51> CMD28 WE# A10
FBAD62 N25 F23
FBA_D62 FBA_CLK0_N CLKA0# <51>
FBAD63 N26 CMD29 BA0 BA0
FBA_D63
FBA_CLK1 N24 CLKA1 <52>
+1.05V_RUN_VTT_GFX Source
FBA_CLK1_N N23 CLKA1# <52> CMD30 A15 BA2
+15V_ALW +1.05V_M
M22 1 2 +1.5V_MEM_GFX QV3 +1.05V_RUN_VTT_GFX
FBA_DEBUG

100K_0402_5%~D
RV76 10K_0402_5%~D SI4164DY-T1-GE3_SO8~D

1
8 1

RV73

10U_0805_6.3V6M~D
N12P-NS-S-A1_BGA533~D 7 2

1
+1.5V_MEM_GFX

20K_0402_5%~D
6 3 1

RV74
5
1.1K_0402_1%~D 1.1K_0402_1%~D

CV126
2
1 @ RV77

4
2

2
1.05V_RUN_VTT_GFX#_EN
16mil

SSM3K7002FU_SC70-3~D

2200P_0402_50V7K~D
2

+FB_VREF

1
D
1
1 @RV78
@

0.01U_0402_25V7K~D

QV4

CV127
1 2
RV78

@ CV128

G
S

3
2
2
2

A A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 50 of 77
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits

FBA_CMD[0..30]
FBA_CMD[0..30] <50,52>
FBAD[0..63]
FBAD[0..63] <50,52>
DQMA#[0..7]
DQMA#[0..7] <50,52>
DQSA_RN[0..7]
DQSA_RN[0..7] <50,52>
D DQSA_WP[0..7] D
DQSA_WP[0..7] <50,52>

UV3
UV4
+1.5V_MEM_GFX 16mil E3 FBAD30
E3 FBAD1 16mil DQL0
F7 FBAD24
DQL0 FBAD6 DQL1 FBAD31
DQL1 F7 DQL2 F2
1
1.1K_0402_1%~D

F2 FBAD3 FBA_CMD7 N3 F8 FBAD28

DQL2 A0 DQL3 Mode E - Mirror Mode Mapping
RV80

FBA_CMD7 N3 F8 FBAD4 Group0 FBA_CMD10 P7 H3 FBAD29 Group3

FBA_CMD10 A0 DQL3 FBAD0 FBA_CMD24 A1 DQL4 FBAD26
P7 A1 DQL4 H3 P3 A2 DQL5 H8
FBA_CMD24 P3 H8 FBAD5 FBA_CMD6 N2 G2 FBAD25 DATA Bus
FBA_CMD6 A2 DQL5 FBAD2 FBA_CMD22 A3 DQL6 FBAD27
N2 G2 P8 H7
2

FBA_CMD22 A3 DQL6 FBAD7 FBA_CMD26 A4 DQL7 Address

P8 A4 DQL7 H7 P2 A5 0..31 32..63
FBA_CMD26 P2 FBA_CMD5 R8
+FBA_VREF0 FBA_CMD5 A5 FBA_CMD21 A6 FBAD14
R8 A6 R2 A7 DQU0 D7 CMD0 ODT_L
FBA_CMD21 R2 D7 FBAD17 FBA_CMD8 T8 C3 FBAD10
A7 DQU0 A8 DQU1
1.1K_0402_1%~D

0.01U_0402_16V7K~D

FBA_CMD8 T8 C3 FBAD21 FBA_CMD4 R3 C8 FBAD15 CMD1 CS1#_L

FBA_CMD4 A8 DQU1 FBAD19 FBA_CMD25 A9 DQU2 FBAD11
1 R3 A9 DQU2 C8 Group2 L7 A10/AP DQU3 C2
1

RV79

CV129

FBA_CMD25 L7 C2 FBAD20 FBA_CMD23 R7 A7 FBAD12 Group1 CMD2 CS0#_L

FBA_CMD23 A10/AP DQU3 FBAD18 FBA_CMD9 A11 DQU4 FBAD8
R7 A11 DQU4 A7 N7 A12/BC# DQU5 A2
FBA_CMD9 N7 A2 FBAD22 FBA_CMD12 T3 B8 FBAD13 CMD3 CKE_L
2 FBA_CMD12 A12/BC# DQU5 FBAD16 FBA_CMD30 A13 DQU6 FBAD9
T3 A13 DQU6 B8 M7 A15 DQU7 A3
FBA_CMD30 M7 A3 FBAD23 CMD4 A9 A11
2

A15 DQU7 +1.5V_MEM_GFX +1.5V_MEM_GFX

CMD5 A6 A7
FBA_CMD29 M2 B2
FBA_CMD29 FBA_CMD13 BA0 VDD
M2 BA0 VDD B2 N8 BA1 VDD D9 CMD6 A3 BA1
FBA_CMD13 N8 D9 FBA_CMD27 M3 G7
FBA_CMD27 BA1 VDD BA2 VDD
M3 BA2 VDD G7 VDD K2 CMD7 A0 A12
CLKA0 K2 K8
VDD VDD
C VDD K8 VDD N1 CMD8 A8 A8 C
N1 CLKA0 J7 N9
<50> CLKA0 VDD CK VDD
2

J7 N9 CLKA0# K7 R1 CMD9 A12 A0

<50> CLKA0# CK VDD CK# VDD
RV81 K7 R1 FBA_CMD3 K9 R9
160_0402_1% FBA_CMD3 CK# VDD CKE VDD
K9 CKE VDD R9 CMD10 A1 A2
FBA_CMD0 K1 A1 CMD11 RAS# RAS#
1

FBA_CMD0 FBA_CMD11 ODT VDDQ

K1 ODT VDDQ A1 J3 RAS# VDDQ A8
CLKA0# FBA_CMD11 J3 A8 FBA_CMD2 L2 C1 CMD12 A13 A14
FBA_CMD2 RAS# VDDQ FBA_CMD15 CS# VDDQ
L2 CS# VDDQ C1 K3 CAS# VDDQ C9
FBA_CMD15 K3 C9 FBA_CMD28 L3 D2 CMD13 BA1 A3
FBA_CMD28 CAS# VDDQ WE# VDDQ
L3 WE# VDDQ D2 VDDQ E9
VDDQ E9 VDDQ F1 CMD14 A14 A13
F1 DQSA_WP3 F3 H2
DQSA_WP0 VDDQ DQSA_WP1 DQSL VDDQ
F3 DQSL VDDQ H2 C7 DQSU VDDQ H9 CMD15 CAS# CAS#
DQSA_WP2 C7 H9
DQSU VDDQ
CMD16 CKE_H
DQMA#3 E7 A9
DQMA#0 DQMA#1 DML VSS
E7 DML VSS A9 D3 DMU VSS B3 CMD17 CS1#_H
DQMA#2 D3 B3 E1
DMU VSS VSS
VSS E1 VSS G8 CMD18 CS0#_H
G8 DQSA_RN3 G3 J2
DQSA_RN0 VSS DQSA_RN1 DQSL VSS
G3 DQSL VSS J2 B7 DQSU VSS J8 CMD19 ODT_H
DQSA_RN2 B7 J8 M1
DQSU VSS VSS
VSS M1 VSS M9 CMD20 RST RST
VSS M9 VSS P1
P1 FBA_CMD20 T2 P9 CMD21 A7 A6
FBA_CMD20 VSS RESET VSS
T2 RESET VSS P9 VSS T1
VSS T1 L8 ZQ VSS T9 CMD22 A4 A5
L8 ZQ VSS T9
CMD23 A11 A9
1

1
243_0402_1%~D

+FBA_VREF0 +FBA_VREF0 M8 B1
VREFCA VSSQ

243_0402_1%~D
M8 VREFCA VSSQ B1 H1 VREFDQ VSSQ B9 CMD24 A2 A1
RV82

RV83
B B
H1 VREFDQ VSSQ B9 VSSQ D1
VSSQ D1 VSSQ D8 CMD25 A10 WE#
D8 E2
2

2
VSSQ VSSQ
VSSQ E2 J1 NC VSSQ E8 CMD26 A5 A4
J1 NC VSSQ E8 J9 NC VSSQ F9
J9 NC VSSQ F9 L1 NC VSSQ G1 CMD27 BA2 A15
L1 NC VSSQ G1 L9 NC VSSQ G9
L9 NC VSSQ G9 T7 NC CMD28 WE# A10
T7 96-BALL
NC
96-BALL SDRAM DDR3 CMD29 BA0 BA0
SDRAM DDR3 H5TQ1G63DFR-11C_FBGA96~D
H5TQ1G63DFR-11C_FBGA96~D CMD30 A15 BA2
@X76
@X76 +1.5V_MEM_GFX
+1.5V_MEM_GFX
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CV139

CV140

CV141

CV142

CV143
CV190

CV189

CV130

CV131

CV132

CV133

CV134

CV135

CV136

CV192

CV191

CV137

CV138

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 51 of 77
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

FBAD[0..63]
FBAD[0..63] <50,51>
FBA_CMD[0..30]
FBA_CMD[0..30] <50,51>
D DQMA#[0..7] D
DQMA#[0..7] <50,51>
DQSA_RN[0..7]
DQSA_RN[0..7] <50,51>
DQSA_WP[0..7]
DQSA_WP[0..7] <50,51>
UV5 UV6
16mil
E3 FBAD35 E3 FBAD61
16mil DQL0
F7 FBAD32 DQL0
F7 FBAD57
DQL1 FBAD38 DQL1 FBAD58
DQL2 F2 DQL2 F2
FBA_CMD9 N3 F8 FBAD33 Group4 FBA_CMD9 N3 F8 FBAD60
+1.5V_MEM_GFX FBA_CMD24 A0 DQL3 FBAD37 FBA_CMD24 A0 DQL3 FBAD56
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group7
FBA_CMD10 P3 H8 FBAD34 FBA_CMD10 P3 H8 FBAD62
A2 DQL5 A2 DQL5
1.1K_0402_1%~D

FBA_CMD13 N2 G2 FBAD39 FBA_CMD13 N2 G2 FBAD59

FBA_CMD26 A3 DQL6 FBAD36 FBA_CMD26 A3 DQL6 FBAD63
P8 H7 P8 H7
A4 DQL7 A4 DQL7 Mode E - Mirror Mode Mapping
1

RV84

FBA_CMD22 P2 FBA_CMD22 P2
FBA_CMD21 A5 FBA_CMD21 A5
R8 A6 R8 A6
FBA_CMD5 R2 D7 FBAD42 FBA_CMD5 R2 D7 FBAD51 DATA Bus
FBA_CMD8 A7 DQU0 FBAD46 FBA_CMD8 A7 DQU0 FBAD52
T8 A8 DQU1 C3 T8 A8 DQU1 C3
FBA_CMD23 R3 C8 FBAD40 FBA_CMD23 R3 C8 FBAD49 Address 0..31 32..63
2

+FBA_VREF1 FBA_CMD28 A9 DQU2 FBAD45 FBA_CMD28 A9 DQU2 FBAD53

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBA_CMD4 R7 A7 FBAD44 Group5 FBA_CMD4 R7 A7 FBAD48 Group6 CMD0 ODT_L
A11 DQU4 A11 DQU4
1.1K_0402_1%~D

0.01U_0402_16V7K~D

FBA_CMD7 N7 A2 FBAD43 FBA_CMD7 N7 A2 FBAD54

A12/BC# DQU5 A12/BC# DQU5
1

1 FBA_CMD14 T3 B8 FBAD41 FBA_CMD14 T3 B8 FBAD50 CMD1 CS1#_L

A13 DQU6 A13 DQU6
RV85

CV144

FBA_CMD27 M7 A3 FBAD47 FBA_CMD27 M7 A3 FBAD55

A15 DQU7 A15 DQU7
+1.5V_MEM_GFX +1.5V_MEM_GFX
CMD2 CS0#_L
2
CMD3 CKE_L
2

FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 BA0 VDD FBA_CMD6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD4 A9 A11
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD BA2 VDD
C VDD K2 VDD K2 CMD5 A6 A7 C
VDD K8 VDD K8
VDD N1 VDD N1 CMD6 A3 BA1
J7 N9 CLKA1 J7 N9
<50> CLKA1 CK VDD CK VDD
K7 R1 CLKA1# K7 R1 CMD7 A0 A12
<50> CLKA1# CK# VDD CK# VDD
FBA_CMD16 K9 R9 FBA_CMD16 K9 R9
CLKA1 CKE VDD CKE VDD
CMD8 A8 A8
FBA_CMD19 K1 A1 FBA_CMD19 K1 A1 CMD9 A12 A0
ODT VDDQ ODT VDDQ
2

FBA_CMD11 J3 A8 FBA_CMD11 J3 A8
RV86 FBA_CMD18 RAS# VDDQ FBA_CMD18 RAS# VDDQ
L2 CS# VDDQ C1 L2 CS# VDDQ C1 CMD10 A1 A2
160_0402_1% FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
FBA_CMD25 CAS# VDDQ FBA_CMD25 CAS# VDDQ
L3 WE# VDDQ D2 L3 WE# VDDQ D2 CMD11 RAS# RAS#
E9 E9
1

VDDQ VDDQ
VDDQ F1 VDDQ F1 CMD12 A13 A14
CLKA1# DQSA_WP4 F3 H2 DQSA_WP7 F3 H2
DQSA_WP5 DQSL VDDQ DQSA_WP6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD13 BA1 A3
CMD14 A14 A13
DQMA#4 E7 A9 DQMA#7 E7 A9
DQMA#5 DML VSS DQMA#6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD15 CAS# CAS#
VSS E1 VSS E1
VSS G8 VSS G8 CMD16 CKE_H
DQSA_RN4 G3 J2 DQSA_RN7 G3 J2
DQSA_RN5 DQSL VSS DQSA_RN6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD18 CS0#_H
VSS P1 VSS P1
FBA_CMD20 T2 P9 FBA_CMD20 T2 P9 CMD19 ODT_H
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ VSS T9 L8 ZQ VSS T9 CMD20 RST RST

1
CMD21 A7 A6
1
243_0402_1%~D

243_0402_1%~D
B +FBA_VREF1 +FBA_VREF1 B
M8 VREFCA VSSQ B1 M8 VREFCA VSSQ B1
RV87

RV88
H1 VREFDQ VSSQ B9 H1 VREFDQ VSSQ B9 CMD22 A4 A5
VSSQ D1 VSSQ D1
D8 D8 CMD23 A11 A9

2
VSSQ VSSQ
E2 E2
2

VSSQ VSSQ
J1 NC VSSQ E8 J1 NC VSSQ E8 CMD24 A2 A1
J9 NC VSSQ F9 J9 NC VSSQ F9
L1 NC VSSQ G1 L1 NC VSSQ G1 CMD25 A10 WE#
L9 NC VSSQ G9 L9 NC VSSQ G9
T7 NC T7 NC CMD26 A5 A4
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD27 BA2 A15
H5TQ1G63DFR-11C_FBGA96~D H5TQ1G63DFR-11C_FBGA96~D
CMD28 WE# A10
@X76 @X76
+1.5V_MEM_GFX +1.5V_MEM_GFX CMD29 BA0 BA0
CMD30 A15 BA2
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1 1 1 1 1 1 1 1 1
CV148

CV149

CV150

CV151

1 1 1 1 1 1 1 1 1
CV194

CV193

CV145

CV146

CV147

CV154

CV155

CV156

CV157

CV158
CV196

CV195

CV152

CV153

2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2

A A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATICS,MB A6561
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
401931
Date: Thursday, January 13, 2011 Sheet 52 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW

ESD Diodes +COINCELL

COIN RTC Battery

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

1
PD33

PD34

PD32
PR1
PL21 +3.3V_ALW 1K_0402_5%~D
@ @ @ FBMJ4516HS720NT_1806~D
1 2 +3.3V_RTC_LDO

2
Media Bay Battery Connector

1
JRTC1

Z4012
1
100K_0402_1%~D
PJP36 +COINCELL 1 3
MBATT+_C 1 G
2 1 MPBATT+ 2 2 G 4

PR504
MBATT1 PR501

0.1U_0603_25V7K~D
1
D D
1 100_0402_5%~D PR502 PAD-OPEN 2x2m~D TYCO_2-1775293-2~D
1

3
PC302
2 Z5304 1 2 100_0402_5%~D PR503
BAY_SMBCLK <29,41>

2
2 Z5305 100_0402_5%~D +RTC_CELL
3 1 2 BAY_SMBDAT <29,41>

2
3 Z5306
2200P_0402_50V7K~D

4 4 1 2 MODULE_BATT_PRES# <40,63>
5 5
6 6
1
PC301

PD1

1
GND 7
8 RB715F_SOT323~D 1
2

GND PC1
1U_0603_10V4Z~D
SUYIN_150010GR006M500ZR
2
Move to power schematic

+3.3V_ALW
GND

ESD Diodes

PL22
FBMJ4516HS720NT_1806~D
DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

2
1 2
PD2

PD3

PD4
PL1 +3.3V_ALW
@ @ @ FBMJ4516HS720NT_1806~D
1 2 PBATT+
Primary Battery Connector
1

1
100K_0402_1%~D
PBATT+_C

PR2
0.1U_0603_25V7K~D
GND 11

1
GND 10

PC2
9 PR4

2
9 100_0402_5%~D PR3
8

2
8 Z4304 100_0402_5%~D PR5
2200P_0402_50V7K~D

7 7 1 2 PBAT_SMBCLK <41>
C 6 Z4305 1 2 100_0402_5%~D C
6 PBAT_SMBDAT <41>
5 Z4306 1 2
5 PBAT_PRES# <40,63>
1
PC3

4 4
3 @ PQ1
3
2
2

2 FDN338P_NL_SOT23-3~D
1 1
@ PD5

3
1 2 1 3 DOCK_SMB_ALERT# <39,41,63>
PBATT1
SUYIN_200275MR009G50PZR RB751V-40_SOD323-2~D

2
2
@ PR6
GND 1 2
<39,40,63> SLICE_BAT_PRES#
0_0402_5%~D

1
@ PC4
1500P_0402_7K~D

2
+5V_ALW
+3.3V_ALW

DA204U_SOT323~D
3

2
PD6
@ PR7 PU1

2.2K_0402_5%~D
2
1 2 GND <39> DOCK_PSID 1 6 GPIO_PSID_SELECT <40>
0_0402_5%~D NO IN

PR8
2 GND V+ 5 +5V_ALW
PL2 PR9

1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
D

2 1 1 3 1 2 3 NC COM 4 PS_ID <41>

100K_0402_1%~D

+5V_ALW PQ2 TS5A63157DCKR_SC70-6~D

2

FDV301N_NL_SOT23-3~D +5V_ALW
G
2

B B
PR10

+5V_ALW
DA204U_SOT323~D

DA204U_SOT323~D
3

2
PD9

10K_0402_1%~D
1

1
C

PR11

PD8
2 PQ3
@ B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D

@
3
2

GND @
1

1
PR12

PD7
PR14 SM24_SOT23 PR13
0_0402_5%~D 1 2
1 2 DCIN_CBL_DET# <40> PSID_DISABLE# <40>
1

@ 10K_0402_5%~D
150P_0402_50V8J~D

.47U_0402_6.3V6-K~D
2

2
PC400

PC5

DC_IN+ Source
1

@ +DC_IN +DC_IN_SS
PQ4
FDS6679AZ_SO8~D
1 S D 8
PL3 2 S
FBMA-L18-453215-900LMA90T_1812~D D 7
3 S D 6
1 2 +DC_IN 4 G D 5
1

1M_0402_5%~D
VZ0603M260APT_0603

0.022U_0805_50V7K~D
2

100K_0402_5%~D

10U_1206_25V6M~D
1
PR15
PC6

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
1

1
PD10

1
1

PR16

PC11
0.1U_0603_25V7K~D

2
1

PC7

PC8

PC9

PJPDC1 PR18
4.7K_0805_5%~D

2
1

@
0.1U_0603_25V7K~D

1 1 2 SOFT_START_GC <63>
2

1
1
PC10

2
2

2
@ PR17

1M_0402_5%~D

3 -DCIN_JACK 10K_0402_5%~D
3
1

2
PC12

4
2

4
PR19

A 5 +DCIN_JACK A
2

5
6 6
7 @
7
2

MOLEX_87438-0743 PL4
FBMA-L18-453215-900LMA90T_1812~D
1 2
DELL CONFIDENTIAL/PROPRIETARY
0.1U_0603_25V7K~D
1

Compal Electronics, Inc.

Title
PC13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D SCHEMATICS,MB A6561
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
401931
Date: Thursday, January 13, 2011 Sheet 53 of 77
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO

+DC1_PWR_SRC

PJP46
+PWR_SRC 1 2

PAD-OPEN 4x4m 3.3Volt+/Ͳ5%

Pop10OhmforMAX17020 ThermalDesignCurrent:4.708A

2
0_0805_5%~D

0_0805_5%~D
PJP47 +5V_VCC1
D D

2200P_0402_50V7K~D

0.1U_0805_50V7M~D
+5V_ALW2 1 2
Peakcurrent:6.725A

PR20

PR21
2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
0.1U_0805_50V7M~D
5Volt+/Ͳ5% @ PR22
OCP_MIN:8.07A

1
PAD-OPEN1x1m 10_0603_5%~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
ThermalDesignCurrent:7.784A

1
1

PC19

PC20

PC21

PC22

PC23
4.7U_0603_6.3V6K~D
2 1

PC14

PC15

PC16

PC17

PC18
PeakCurrent:11.12A

2
Fsw=300KHz

1
PC24
@
OCP_MIN:13.344A @
+3.3V_ALW2

2
0.1U_0603_25V7K~D
Fsw=400KHz

1
PC25

1U_0402_6.3V4Z~D
0_0402_5%~D
@ PR24

1U_0603_10V6K~D
1

1
PC26
0_0402_5%~D

1
PR23

PC27
1 2

2
@ PR25

2
0_0402_5%~D

2
1 2

+5V_ALW2P
+5V_3V_REF

EN_3V_5V
+3.3V_ALW2
+3.3V_RTC_LDO PC28
0.1U_0603_25V7K~D

1
GNDA_3V5V GNDA_3V5V PR27

VIN
1 2
0_0402_5%~D
LDOREFIN 1 2

0.1U_0402_10V7K~D
FDS8878 1N SO8

@ PR26

0.1U_0402_10V7K~D
PR28

2
3

PC30
0_0603_5%~D @

33

8
7
6
5
4
3
2
1

5
6
7
8
GNDA_3V5V PU2 1 2
D

1
+5V_ALWP

PC29
0_0402_5%~D

AO4466L_SO8~D
LDO

ONLDO

REF
PAD

LDOREFIN

IN
RTC

VCC
TON

D
D
D
D
REFIN2
PQ5

2
2

PQ6
2 @ PR29
G 249K_0402_1%~D
9 BYP REFIN2 32 4 G
+5V_ALWP PR30 10 31 1 2 GNDA_3V5V
OUT1 ILIM2
S

330K_0402_1%~D +5V_FB1 11 30 +3.3V_OUT2

FB1 OUT2

S
S
S
C GNDA_3V5V 1 2 12 29 2 PR31 10_0402_5%~D +3.3V_ALWP C
1

PL5 POK1 ILIM1 SKIP POK2

13 28

3
2
1
EN_3V_5V PGOOD1 PG00D2 EN_3V_5V PL6
14 ON1 ON2 27
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D +5V_ALW_UGATE 15 26 +3.3V_ALW_UGATE 4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D
+5V_ALWP +5V_ALW_PHASE DH1 DH2 +3.3V_ALW_PHASE +3.3V_ALWP
1 2 16 LX1 LX2 25 2 1
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
SECFB
1

1
AGND
PGND
0_0402_5%~D

0_0402_5%~D
GNDA_3V5V @

BST1

BST2
0.1U_0603_25V7K~D
FDMS7692 1N POWER56-8

VDD

5
6
7
8

1
DL1

DL2
PC31

PC32
330U_V_6.3VM~D

330U_V_6.3VM~D
D
PR32

PR33
0.1U_0603_25V7K~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
D
D
D
D
2

2
1

1
PC34

PC35
SN0608098_TQFN32_5X5~D

AO4406AL_SO8~D
1 1

17
18
19
20
21
22
23
24
PQ7

@
2
1

1
+ +
PC33

PC36

PC37

PC38
@ 2

2
G

SECFB

PQ8
4 G
2

2
PR34 PR35 @ PR37
2

2
2 2
S

@ 2.2_0603_5%~D 2.2_0603_5%~D 4.7_1206_5%~D @

S
S
S

0_0402_5%~D
1 2+5V_ALW_BOOT +3.3V_ALW_BOOT1 2
1
1

1
0_0402_5%~D

@
4.7_1206_5%~D

3
2
1
PR36

PR39
+3.3V_ALW_LGATE
1

1
PR38

@
2

2
+5V_ALW_LGATE
GNDA_3V5V

GNDA_3V5V
GNDA_3V5V PC39 PJP48

1U_0603_10V6K~D
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2
+3.3V_ALWP +3.3V_ALWP

PC40
1 1 2

+5V_ALW2
0.1U_0603_25V7K~D

2
PAD-OPEN1x1m
1

PD11 GNDA_3V5V

100K_0402_1%~D

100K_0402_1%~D
PC41

BAT54SW-7-F_SOT323-3~D

2
2

PR40

PR41
PC42
2 0.1U_0603_25V7K~D PD13
1

1 1 2 BAT54CW_SOT323~D
B B
3 @

1
PR42 PD12 POK2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D
<41> ALWON
3

0_0402_5%~D
1
200K_0402_5%~D
2

PR45
PR43
PR44

0_0402_5%~D
<22> THERM_STP# 2 1

2
1

POK1
PJP49 ALW_PWRGD_3V_5V <41>
1 2

PAD-OPEN 4x4m PR46

PJP50 PJP51 200K_0402_1%~D
+5V_ALWP 1 2 +15V_ALW 2 1 +15V_ALWP 2 1
+5V_ALW
PAD-OPEN 4x4m
0.1U_0603_25V7K~D

PAD-OPEN1x1m
2

(100mA,20mils ,Via NO.=1)

1

PR47
PC43

PJP52 39K_0402_5%~D
1 2 +3.3V_ALW
2

+3.3V_ALWP
1

PAD-OPEN 4x4m
PJP9
1 2

PAD-OPEN 4x4m
GNDA_3V5V

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
401931
Date: Thursday, January 13, 2011 Sheet 54 of 77
5 4 3 2 1
 5 4 3 2 1

+1.5V_SUS_P(RT8209B) 1.5 Volt +/-5%

D D
Thermal Design Current: 12.259A
Peak current: 17.513A
OCP_MIN:21.016A
@ PL28
FBMJ4516HS720NT_1806~D
1 2

PJP10
+1.5V_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m

2200P_0402_50V7K~D

0.1U_0805_50V7M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
1

1
PC44

PC45

PC46

PC47

PC48
PQ22

FDMS7692_POWER56-8-5~D
5

2
@ @

PR49
255K_0402_1%~D 4
1 2
PR50 PR48
GNDA_1.5V PC50
0_0402_5%~D 2.2_0603_5%~D
<41,56> DDR_ON 1 2 BST_1.5VP 1 2 1 2

3
2
1
2

0.1U_0603_25V7K~D
1

@ PC51 @ PR508 PL7

15

14
1
.1U_0402_16V7K 300K_0402_5%~D PU3 1UH_FDUE1040D-1R0M=P3_21.3A_20%~D
1 2

EN/DEM

BOOT
NC
+1.5V_SUS_P
2

DH_1.5VP

4.7_1206_5% 680P_0603_50V7K~D
2 TON UGATE 13

330U_SX_2VY~D

330U_SX_2VY~D
C C

PC53
LX_1.5VP

2200P_0402_50V7K~D
PR51

0.1U_0402_10V7K~D
3 VOUT PHASE 12

5
10_0402_5%~D 1 1

2
1 2 4 11 1 2 +5V_ALW PQ21

FDMS0310S_DFN8-5
+5V_ALW VDD CS

1
+ +

PC56

PC57
PR55 @

PC58

PC59
5 10 10K_0402_1%~D
FB VDDP

0_0402_5%~D

2
1

2 2

PR53
6 9 DL_1.5VP 4
PGOOD LGATE

1
PGND
PC49
GND
4.7U_0603_6.3V6K~D @
PC615
2

PR56

1
2 1 RT8209MGQW_WQFN14_3P5X3P5 PC52
7

3
2
1
4.7U_0805_10V6K~D

2
GNDA_1.5V +3.3V_ALW 39P_0402_50V8J~D @

PR52 GNDA_1.5V
100K_0402_1%~D

10K_0402_1%~D
1 2 GNDA_1.5V
1

1
PR59

PR54
10K_0402_1%~D
2

<41> 1.5V_SUS_PWRGD
GNDA_1.5V

B B

PJP11
1 2

PAD-OPEN 4x4m
PJP12
1 2 PJP13
+1.5V_SUS_P 1 2 +1.5V_MEM

PAD-OPEN1x1m PAD-OPEN 4x4m

GNDA_1.5V

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DELL CONFIDENTIAL/PROPRIETARY
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
401931
Date: Thursday, January 13, 2011 Sheet 55 of 77
5 4 3 2 1
 5 4 3 2 1

+1.8V_RUNP
1.8 Volt +/-5%
Thermal Design Current: 0.824 A
Peak current: 1.178 A
+3.3V_ALW
@
PJP14
OCP_MIN: 1.414 A
2 1 +1.8V_PWR_SRC
D D
PAD-OPEN 2x2m~D

10U_0805_6.3V6M~D

22U_0805_6.3V4Z~D

0.1U_0603_25V7K~D
PC68
2

1
PC66

PC67

1
PR60

2
@ 0_0603_5%~D

2
+1.8V_VDD

13

14

15

16

17
PU4

VIN

VIN

PGND

PGND

TPAD
PR61
PC69
1 2 12 1 +1.8V_EN 2 1 RUN_ON <11,38,40,43,64>
VDD EN

GNDA_1.8V 0.1U_0402_10V7K~D 24k_0402_1%~D

11 AGND RES 2

TPS51311RGTR_QFN16_3X3~D
PR64
PC70 PR63
1 2 2 1 +1.8V_FB 10 3 2 1 +3.3V_RUN
FB PGOOD
0.012U_0402_16V7K~D 10_0402_1%~D
+1.8V_RUNP

PR65 PR66 PC71 10K_0402_5%~D

2 1 2 1 2 1 +1.8V_COMP 9 4 +1.8V_VBST
COMP VBST
2K_0402_1%~D 1.43K_0402_1%~D 0.018U_0402_16V7K~D 1.8V_RUN_PWRGD <40>

MODE
1K_0402_1%~D PC72

3.3_0603_1%~D
2
SW

SW

SW
2 1
1

PR67
PR68

C 100P_0402_50V8J~D C

1
PC73

+1.8V_MODE
2

2 1

GNDA_1.8V PR69 0.22U_0603_10V7K~D

@ PJP15 1 2 PL8
1 2 2UH_#A915AY-H-2R0M=P3_3.3A_20%~D
57.6K_0402_1%~D +1.8V_SW 2 1 +1.8V_RUNP
PAD-OPEN1x1m

680P_0603_50V8J~D

47P_0402_50V8J~D
22U_0805_6.3V4Z~D

22U_0805_6.3V4Z~D
PC74
GNDA_1.8V GNDA_1.8V

1
PC75

PC76

PC77
@

2
1

PR70
4.7_0805_5%~D
2
@

+0.75V_DDR_VTT
B B

DDR3 Termination

@
+5V_ALW PJP16
+1.8V_RUNP 2 1 +1.8V_RUN
PAD-OPEN 2x2m~D
0.75Volt +/-5%
Thermal Design Current: 0.525A
4.7U_0805_10V4Z~D

PU5
Peak current: 0.75A
2

RT9026GFP_MSOP10~D
PC78

PJP17 +V_DDR_REF
VOUT=1.8V
+1.5V_MEM 2 1 DC_1+0.75V_VTT_PWR_SRC 1 10
1

VDDQSNS VIN L=3.3uF

PAD-OPEN 2x2m~D 2 VLDOIN Fsw=290KHz
+0.75V_P PC81 D=0.092
GND 8 Input Ripple Current=TDC*(D*(1-D))^0.5=0.884A
VTTREF 6 2 1 Output Ripple Current=1.707A
3 PJP18
VTT PR72 +0.75V_P Output Ripple Voltage=1.707*15m=20.5mV
10U_0805_6.3V6M~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D 2 1 +0.75V_DDR_VTT
2

+0.75V_S5
10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

5 VTTSNS S5 9 2 1
PC82

PC83

0_0402_5%~D PAD-OPEN 2x2m~D

PGND

7 +0.75V_S3 2 1
GND
1

S3
2

2
PC79

PC80

PR71
0_0402_5%~D
1

11

A A

DDR_ON <41,55>

0.75V_DDR_VTT_ON <40>

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 56 of 77
5 4 3 2 1
 5 4 3 2 1

+1.05V_M

D D

PC84
PJP19
1U_0402_6.3V6K~D +1.05V_PWR_SRC 1 2 +5V_ALW
2 1 PAD-OPEN 4x4m
1.05Volt+/Ͳ5%

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PC88

PC89
ThermalDesignCurrent:4.391A

1
+1.05VM_VX

@ PC85

PC86

PC87
Peakcurrent:6.273A

2
GNDA_1.05VM

17

16
OCP_MIN:7.527A

2
PU6
PC90
VIN

VIN
+3.3V_ALW 0.22U_0603_10V7K~D

1
PR74 PR75 @
PC91 100P_0402_50V8J~D 3.3_0603_1%~D 0_0402_5%~D
2 1 1 VCCA VBST 15 +1.05VM_BST 1 2 2 1 SIO_SLP_A# <16,40>
C 2 GND PGOOD 14 +1.05VM_PWRGD PR78 C
PR76 5.6K_0402_5%~D PC92 680P_0402_50V7K~D 0_0402_5%~D
2 1 2 1 +1.05VM_COMP 3 13 +1.05VM_EN 2 1 A_ON <41,43>
COMP EN 22.1K_0402_1%~D
+1.05VM_VFB 4 12 +1.05VM_FSET 2 1
PR80 2K_0402_1%~D VFB FSET @ PR79
2 1 +1.05V_MP 5 11 +1.05VM_MODE
VOUT MODE

2
+1.05VM_SS 10 +1.05VM_IMON

22K_0402_1%~D
2 1 1 2 6 SS IMON

PR83
+1.05V_MP

GNDA_1.05VM
0.01U_0402_16V7K
1

0_0402_5%~D
2.67K_0402_1%~D

PGND

PGND
PC94

1800P_0402_50V7K~D
+1.05V_MP
SW

PR81 PC93
2

1
PR82

SN1003055RUWR_QFN17_3P5X3P5~D
2

GNDA_1.05VM PL9
0.42UH_ETQP4LR42AFM_17A_20%~D
+1.05VM_VX

GNDA_1.05VM +1.05VM_VX 2 1
GNDA_1.05VM
1

1
@
1.33K_0402_1%~D
@ PR84

PC106

PC107
PC95

6800P_0402_25V7K~D
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0603_25V7K~D
1

1
0.1U_0603_25V7K~D

PC96

PC97

PC98

PC99

PC100

PC101

PC102

PC103

PC104

PC105
@ PR85 0_0402_5%~D
2

2 1

2
2
@ PR86
7.68K_0805_1%~D
GNDA_1.05VM

1
B B

+3.3V_ALW
100K_0402_1%~D
1
PR87

PJP21
PJP20 1 2
1 2
2

PAD-OPEN 4x4m
PR88 0_0402_5%~D
+1.05VM_PWRGD 2 1 1.05V_A_PWRGD <41> PAD-OPEN1x1m PJP22
+1.05V_MP 1 2 +1.05V_M
GNDA_1.05VM
PAD-OPEN 4x4m

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 57 of 77
5 4 3 2 1
 5 4 3 2 1

PC108
PJP23
1U_0402_6.3V6K~D +1.05VTT_PWR_SRC 1 2 +5V_ALW
D D
2 1 PAD-OPEN 4x4m

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
10U_0805_10V4Z~D

10U_0805_10V4Z~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PC112

PC113
1

1
+1.05VTT_VX

@ PC147

@ PC181

PC109

PC110

PC111
2

2
GNDA_1.05VTT

17

16

2
PU7
PC114

VIN

VIN
+3.3V_ALW 0.22U_0603_10V7K~D

1
PR89
PC115 100P_0402_50V8J~D 2.2_0603_5%~D
2 1 1 VCCA VBST 15 +1.05VTT_BST 1 2 1.05Volt+/Ͳ5%
2 GND PGOOD 14 +1.05VTT_PWRGD PR91 ThermalDesignCurrent:5.98A
PR90 5.6K_0402_5%~D PC116 680P_0402_50V7K~D 0_0402_5%~D CPU_VTT_ON <40,62>
2 1 2 1 +1.05VTT_COMP 3 COMP EN 13 +1.05VTT_EN 1 2 Peackcurrent:8.543A
22.1K_0402_1%~D
+1.05VTT_VFB 4 VFB FSET 12 +1.05VTT_FSET 2 1 OCP_MIN:10.251A
PR93 2K_0402_0.5%~D @ PR92
2 1 +1.05VTT_SENSE 5 11 +1.05VTT_MODE
+1.05VTT_SENSE

VOUT MODE

0_0402_5%~D
2 1 1 2 +1.05VTT_SS 6 10 +1.05VTT_IMON
SS IMON

PR95
GNDA_1.05VTT

0.01U_0402_16V7K
0_0402_5%~D 1

PGND

PGND
PC118

1800P_0402_50V7K~D

SW
PR94 PC117
2

1
SN1003055RUWR_QFN17_3P5X3P5~D

9
1

1
20K_0402_0.5%~D

3.09K_0402_0.5%~D

GNDA_1.05VTT PL10 +1.05VTTP

0.42UH_ETQP4LR42AFM_17A_20%~D

+1.05VTT_VX
PR96
PR505

+1.05VTT_VX 2 1
GNDA_1.05VTT
2

1
@

1.33K_0402_1%~D
@ PR97

PC128

PC131
47U_0805_4V6M~D

47U_0805_4V6M~D
PC119

6800P_0402_25V7K~D
22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0603_25V7K~D
1

1
C 0.1U_0603_25V7K~D C

PC120

PC129

PC121

PC122

PC130

PC123

PC124

PC125

PC126

PC127
@ PR98 0_0402_5%~D

2
GNDA_1.05VTT 2 1

2
2

1
PR100
10_0402_5%~D
GNDA_1.05VTT @ PR99
7.68K_0805_1%~D
GNDA_1.05VTT

2
PR101
2 1 +5V_RUN PR102
+1.05VTT_SENSE 1 2 VTT_SENSE <10>
9.31K_0402_1%~D
PR103 0_0402_5%~D
+1.05VTT_PWRGD 1 2 1.05V_VTTPWRGD <41,62>
0_0402_5%~D PR105
PR104 GNDA_1.05VTT 1 2 VTT_GND <10>
2 1
0_0402_5%~D
13.3K_0402_1%~D

B B

PJP25
PJP24
1 2 2 1

PAD-OPEN 43X118
PAD-OPEN1x1m
PJP26
+1.05VTTP 1 2 +1.05V_RUN_VTT
GNDA_1.05VTT
A PAD-OPEN 43X118 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401931
Date: Thursday, January 13, 2011 Sheet 58 of 77
5 4 3 2 1
 5 4 3 2 1

+VCC_PWR_SRC

2200P_0402_50V7K~D

10U_1206_25VAK~D

10U_1206_25VAK~D
0.1U_0603_25V7K~D
5

5
PQ10
PQ9

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN

1
PC132
PC401

PC133

PC134

PC135

PC351
0.033U_0402_16V7K~D @

2
1 2 UGATE3 4 4

PC136 +5V_ALW
PR118 PR107 PC137
1 2 1 2 2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1

3
2
1
PC138 BOST3 2 1 BT3_1 1 2
0.33U_0603_10V7K~D 1_0603_1%~D 1U_0603_10V6K~D PU8 PL11
2 1 5 1 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
PR109 VDD BST
2 1 6 8 PHASE3 4 1 +VCC_CORE
D
40.2K_0402_1%~D P1_SW SKIP DH D
2 1

1
P3_SW 3 2P3_Vo

470P_0603_50V8J~D
2 PWM LX 7

PQ12

PC139
PH1 PR111 PR110 4.32K_0402_1%~D PQ11

AON6704L_DFN8-5

AON6704L_DFN8-5

1
Layout Note: 1 2 2 1 2 1 P2_SW 3 4

2
GND DL 2.1K_0402_1%~D PR114
PC142 close to PIN19 10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D PR112 4.32K_0402_1%~D 9 @ PR113 1_0402_5%~D
P3_SW EP LGATE3
2 1 4 4

1
MAX17491GTA+T_TQFN8_3X3~D

2
PR115 4.32K_0402_1%~D

2.2_1206_1%~D
+Vcore_VCC

PR117
1
PC140 PR120

3
2
1

3
2
1
PR121 0_0402_5%~D PR122 10_0402_5%~D 4700P_0402_25V7K~D 2 1

2
+5V_ALW 1 2 +Vcore_VDD 1 2 @ 22.1K_0402_1%~D

1
1K_0402_1%~D

165K_0402_1%~D

165K_0402_1%~D
5.62K_0402_1%~D

5.62K_0402_1%~D
2.2U_0603_10V7K~D
1

2
PC143 PR128 @ PC144
1

PC142

PR123

PR124

PR125

PR126

PR127
2.2U_0603_10V7K~D
1U_0603_10V6K~D

0_0402_5%~D 1 2
PC141

GNDA_VCC 1 2 +Vcore_CSPA3
2

@ PC145 1000P_0402_50V7K~D
2

2
<14,41> 1.05V_0.8V_PWROK 1 2 GNDA_VCC 1 2 PC146

1
@ PR129 0_0402_5%~D 0.22U_0603_10V7K~D
1000P_0402_50V7K~D 2 1
<40> IMVP_VR_ON 1 2 +Vcore_IMAXA
@ PR131 0_0402_5%~D

100K_0402_1%_TSM0B104F4251RZ~D

100K_0402_1%_TSM0B104F4251RZ~D
+GFX_IMAXB +Vcore_CSNA

+Vcore_CSPAAVE

+VGFX_THERMB

+Vcore_THERMA

10K_0402_1%~D

105K_0402_1%~D

105K_0402_1%~D
+VCC_PWR_SRC 1 2

+Vcore_CSPA3

+Vcore_CSPA2

+Vcore_CSPA1

+Vcore_PWMA

2
+Vcore_CSNA
PR132 200K_0402_1%~D

+Vcore_TONA

+Vcore_VCC

PR133

PR134

PR135
+Vcore_EN

+Vcore_SR
GNDA_VCC +VCC_PWR_SRC PJP27

PH2

PH3
1 2 +PWR_SRC
+VGFX_PWR_SRC 1 2 +VGFX_TONB @

1
PR136 200K_0402_1%~D PAD-OPEN 4x4m

2200P_0402_50V7K~D

10U_1206_25VAK~D

10U_1206_25VAK~D
0.1U_0603_25V7K~D
1

5
PQ13

PQ14

100U_25V_M~D

100U_25V_M~D

100U_25V_M~D
10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN
LocalsenseresisterputHWside 1 1 1

1
PC148

PC154

PC155

PC156
49

48

47

46

45

44

43

42

41

40

39

38

37
+ + +

PC151

PC152

PC153

PC352
PR138 PU9 @
10_0402_1%~D GNDA_VCC

TONA

CSNA

CSPAAVE

THERMB

THERMA

DRVPWMA
CSPA3

CSPA2

CSPA1
TPAD

EN

VCC

SR

2
<10> VSSSENSE 1 2 +Vcore_GNDSA 4 4
C @ PR506 2 2 2 C
1

0_0402_5%~D PC149
2 1 1000P_0402_50V7K~D
1

@ PC150 1 36 +GFX_IMAXB
2

3
2
1

3
2
1
1000P_0402_50V7K~D GNDA_VCC TONB IMAXB
2 35 +Vcore_IMAXA PR141 PC157 PL12
2

PR139 10_0402_1%~D PR140 12.4K_0402_1%~D GNDSA IMAXA 2.2_0603_5%~D 0.22U_0603_10V7K~D 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D

<10> VCCSENSE 1 2 2 1 +Vcore_FBA 3 34 BOST2 2 1 BT2_1 1 2
@ PR507 FBA BSTA2
4 1 +VCC_CORE
1

0_0402_5%~D PC158 +Vcore_VRHOT# 4 33 PHASE2

VRHOT# LXA2

1
1000P_0402_50V7K~D GNDA_VCC P2_SW 3 2P2_Vo

470P_0603_50V8J~D
2 1

PQ16

PC159
5 32 UGATE2 PQ15

AON6704L_DFN8-5

AON6704L_DFN8-5
2

AGND DHA2

1
@ PR143 GNDA_VCC

2
+1.05V_RUN_VTT 1 2 +VGFX_FBB 6 MAX17411GTM+_TQFN48_6X6~D 31 LGAT2 2.1K_0402_1%~D PR145
75_0402_5%~D FBB DLA2 @ PR144 1_0402_5%~D
PR146 +VGFX_GNDSB 7 30 4 4
GNDSB PGNDA

1
1 2

2
<7,41> H_PROCHOT# 0_0402_5%~D +Vcore_VDD

2.2_1206_1%~D
8 CSPBAVE VDDA 29
1

PR148
PC168

2.2U_0603_10V7K~D
1

1
43P_0402_50V8J +GFX_CSPB1 9 28 PC161 PR152

3
2
1

3
2
1
CSPB1 DLA1

PC160
4700P_0402_25V7K~D 2 1
2

2
10 27 @ 22.1K_0402_1%~D

2
CSNB DHA1

1
GNDA_VCC <60> +GFX_CSNB
11 26 PR154 @ PC162
<60> +GFX_CSPBAVE CSPB2 LXA1
0_0402_5%~D 1 2
2

+GFX_POKB 12 25 +Vcore_CSPA2
PR147 POKB BSTA1 @ PC164 1000P_0402_50V7K~D

2
DRVPWMB
2

GNDA_VCC 1 2 PC166
ALERT#

0_0402_5%~D PR150 0.22U_0603_10V7K~D

PGNDB

AGND
VDDB

POKA
BSTB

1000P_0402_50V7K~D
VDIO

0_0402_5%~D 2 1
DHB
1

DLB

CLK
LXB

PR149
10_0402_5%~D
+Vcore_VCC
1

1 2 @ PC205 +Vcore_CSNA
13

14

15

16

17

18

19

20

+Vcore_VDIO 21

+Vcore_ALERT# 22

23

+Vcore_POKA 24

GNDA_VCC 1 2
+Vcore_VDD

+Vcore_CLK

PR153 1000P_0402_50V7K~D
10_0402_1%~D
<11> VSS_AXG_SENSE 1 2 +VGFX_GNDSB
B <60> +GFX_BSTB +VCC_PWR_SRC B
1

PC163

2200P_0402_50V7K~D

10U_1206_25VAK~D

10U_1206_25VAK~D
0.1U_0603_25V7K~D
GNDA_VCC

<60> +GFX_LXB

5
PQ17

PQ18
1000P_0402_50V7K~D

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN
1

@ PC165
2

<60> +GFX_DHB

1
PC169
1000P_0402_50V7K~D GNDA_VCC

PC170

PC171

PC172

PC353
@
2

PR156 PR157 8.06K_0402_1%~D <60> +GFX_DLB

2
<11> VCC_AXG_SENSE 1 2 2 1+VGFX_FBB PC173 0.1U_0402_25V6K~D UGATE1 4 4
1 2
1

10_0402_1%~D PC167
1000P_0402_50V7K~D 2 1 PR161 PC174
+VCC_GFXCORE 1 2 PR159 130_0402_1%~D 2.2_0603_5%~D 0.22U_0603_10V7K~D
2

3
2
1

3
2
1
GNDA_VCC +1.05V_RUN_VTT 2 1 BOST1 2 1 BT1_1 1 2
PR158 @ PR160 130_0402_1%~D PL13
10_0402_5%~D +3.3V_RUN 2 1 0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
+GFX_POKB PR162 54.9_0402_1%~D
PHASE1 4 1 +VCC_CORE
<10> VIDSOUT
10K_0402_1%~D

1 2
2

1
0_0402_5%~D

PR164 0_0402_5%~D P1_SW 3 2P1_Vo

470P_0603_50V8J~D
<10> VIDALERT_N

PQ20
PR165

PR166

PC175
1 2 PQ19

AON6704L_DFN8-5

AON6704L_DFN8-5

1
PR167 0_0402_5%~D

2
<10> VIDSCLK 1 2 2.1K_0402_1%~D PR170
@ PR168 0_0402_5%~D @ PR169 1_0402_5%~D
1

PR171 LGATE1 4 4

1
<40> IMVP_PWRGD 2 1 +Vcore_POKA

2
2.2_1206_1%~D
PR173
0_0402_5%~D
1

PC176 PR176

3
2
1

3
2
1
4700P_0402_25V7K~D 2 1

2
@ 22.1K_0402_1%~D
2

1
PR177 @ PC177
0_0402_5%~D 1 2
+Vcore_CSPA1
@ PC178 1000P_0402_50V7K~D

2
GNDA_VCC 1 2 PC179
0.22U_0603_10V7K~D
A 1000P_0402_50V7K~D 2 1 A

PJP28
1 2 +Vcore_CSNA
@ PC180
GNDA_VCC 1 2
PAD-OPEN1x1m
GNDA_VCC 1000P_0402_50V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401931
Date: Thursday, January 13, 2011 Sheet 59 of 77
5 4 3 2 1
 5 4 3 2 1

D D

C C

+VGFX_PWR_SRC
PJP29
1 2 +PWR_SRC
PAD-OPEN 4x4m

2200P_0402_50V7K~D

10U_1206_25VAK~D

10U_1206_25VAK~D
0.1U_0603_25V7K~D
5

5
PQ24

PQ38

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN

1
PC193

PC194

PC195

PC196

PC354
2

2
4 4
<59> +GFX_DHB

PR189 PC197
2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1

3
2
1
2 1 GBT1_1 1 2
<59> +GFX_BSTB
PL15
0.36UH_FDUE1040J-H-R36M=P3_33A_20%~D
4 1 +VCC_GFXCORE
<59> +GFX_LXB 5

1
GP1_SW3 2GP1_Vo

2200P_0402_50V7K~D
470P_0603_50V8J~D

0.1U_0402_10V7K~D

470U_D2_2VM_R4.5M~D
PQ26

PC198
PQ25

AON6704L_DFN8-5

AON6704L_DFN8-5
1

1
+

PC201
PC200

PC199
@
4 4

2
1
<59> +GFX_DLB 2

2.2_1206_1%~D

1
PR193
1

1_0402_5%~D
PC203
3
2
1

3
2
1

PR191
4700P_0402_25V7K~D

2
@
2

PC402

2
B B
0.033U_0402_16V7K~D
1 2

PC208 PR119 0_0603_5%~D

1 2 1 2

0.33U_0603_10V7K~D
PR201
2 1
40.2K_0402_1%~D

PH4 PR203
1 2 2 1 2 1

10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D PR202 1.43K_0402_1%~D

<59> +GFX_CSNB
@ PC207
GNDA_VCC 1 2

1000P_0402_50V7K~D

<59> +GFX_CSPBAVE

A A

Compal Electronics, Inc.

Title
SCHEMATICS,MB A6561
Size Document Number Rev
B
401931
Date: Thursday, January 13, 2011 Sheet 60 of 77
5 4 3 2 1
 5 4 3 2 1

@ PD14
2 1 @ PL16
FBMJ4516HS720NT_1806~D
ES2AA-13-F 2 1
PQ27 PR205
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
8 1 PJP33
+DC_IN_SS 7 2 4 1 1 2

0.1U_0603_25V7K~D
6 3
PAD-OPEN 4x4m

0.1U_0603_25V7K~D
5 3 2
@

47P_0402_50V8J~D
1

1
D D

PC210

PC211
AdapterProtectionEvent

PC209
PR206

2
1
1 2 PR207 D @
DC_BLOCK_GC <63>
1 2 2 PQ28
0_0402_5%~D
<63> CSS_GC
G NTR4502PT1G_SOT23-3~D PR521 PR522 PR510

1
0_0402_5%~D D S

3
2 PQ30A
G NTGD4161PT1G_TSOP6~D
PQ29 S SW 0Ohm @ 100k

S
NTR4502PT1G_SOT23-3~D

D
5 6 DOCK_DCIN_IS+ <39>
E2 AC_OK=17.7 Volt
HW @ 0Ohm @

CSSN_1
CSSP_1

G
1
PR218 PQ30B
PR208 NTGD4161PT1G_TSOP6~D
TI bq24745 = 316K

0_0402_5%~D
10K_0402_5%~D
Intersil ISL88731 = 226K

S
0_0402_5%~D

100K_0402_1%~D

D
2 1 2 4 DOCK_DCIN_IS- <39>
Maxim = 383K

1
PR522

PR209

PR210

100K_0402_1%~D
1

1
PR211
0_0402_5%~D

G
3
+SDC_IN 1 2 H_PROCHOT#

PR212
MAX8731A_LDO MAX8731_REF PC212 PC213
PR216
10K_0402_1%~D

10K_0402_5%~D PR213 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D @ PC292

2
<63> +CHGR_DC_IN 1 2 1 2 1 2 1 2 0_0402_5%~D

2
1

1
@ PR521
316K_0402_1%~D

1 2 DK_CSS_GC <63>
PR214

PR215

1_0805_5%~D ICREF 0.1U_0603_25V7K~D 0_0402_5%~D

2

@ PR509
PR217

DYN_TUR_PWR_VO 1 2 DYN_TURB_PWR_ALRT#
GNDA_CHG 0_0402_5%~D

28

27
1
@ PC215 GNDA_CHG PU11 ICOUT 1 2 1 2 GNDA_CHG
2

0.1U_0805_50V7M~D @ PR220

1U_0603_10V6K~D
CSSP
ICREF

CSSN
PR219 2 1 DCIN 22 26 33_0603_1%~D @ PC214
1

DCIN ICOUT

2
PC405
49.9K_0402_1%~D PR218 1U_0603_10V6K~D

1
2.2_0603_1%~D @ PR510

BAT54HT1G_SOD323-2~D
2 1 2 ACIN
PR221 BOOT
25 1 2 BOOT_D 100K_0402_5%~D
BOOT @
15.8K_0402_1%~D

PC216 1 2 13

2
<22,41,63> ACAV_IN ACOK

1
PC217
0_0402_5%~D

2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
1

1
1

1
C 2 1 11 VDDSMB +3.3V_ALW C

5
6
7
8

5
6
7
8
PD15
PR222

1
PC218

PC219

PC220

PC221
0.01U_0402_25V7K~D 10 GNDA_CHG

SI4800BDY-T1-E3_SO8~D

SI4800BDY-T1-E3_SO8~D
D
D
D
D

D
D
D
D
2
SCL

PQ31

PQ32
GNDA_CHG +5V_ALW @ 9 21 MAX8731A_LDO 1 2
2

2
SDA VDDP

GNDA_CHG 14 PC222 1U_0603_10V6K~D 4 4

NC CHG_UGATE G G
UGATE 24
MAX8731_IINP 8 VICM
1

S
S
S

S
S
S
23 2 PR223 1 +VCHGR_B
PHASE

3300P_0402_50V7K~D
PC223 6

3
2
1

3
2
1
FBO

1
0.1U_0402_10V7K~D 1_0603_1%~D
2

1 2 5 @ PC224 PL17
EAI 220P_0402_50V7K~D 5.6UH_HMU1356B-5R6-F_8A_20%~D

1
GNDA_CHG PR224 CHG_LGATE
4.7K_0402_5%~D

1 2 1 2 4 EAO LGATE 20
+VCHGR

PC226
56P_0402_50V8~D

<41> CHARGER_SMBCLK 200K_0402_5%~D PC225 PR225 PR227

1

3
2200P_0402_50V7K~D 7.5K_0402_5%~D 0.01_1206_1%~D

2
PR226

<41> CHARGER_SMBDAT
2
PC227

MAX8731_REF 3 19 @ 2 1+VCHGR_L
4 1
VREF PGND
CSOP 18
PC228 PR228

1.8K_1206_5%~D
3 2
2

<22> MAX8731_IINP

1
120P_0402_50VNPO~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
0.1U_0603_25V7K~D
1 2 7 CE CSON 17

5
6
7
8

PR229
0_0402_5%~D

0_0402_5%~D
10K_0402_5%~D
8.45K_0402_1%~D

220P_0402_50V8J~D

1 2
1

1
15 VFB 1 PR230 PC234
0.1U_0402_10V7K~D
2

SI4812BDY-T1-E3_SO8~D
+VCHGR

2
VFB
1

1
PR232

PC229

1000P_0603_50V7K~D
1U_0603_10V6K~D
0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

12 GND
1

PR231

PR233

PC236

PC237

PC238

PC239
16 100_0402_5%~D @

2
NC
1

PQ33
PC230

PC231

PC232

PC233

PC235

29
2

2
TP

2
@ 4 PR234
2

2
4.7_1206_5%~D
2

@ @ @ @ BQ24747RHDR_QFN28_5X5~D
PJP34

1
PC240 D
1 2

3
2
1

1
0.1U_0603_25V7K~D PC241 @ PC293 2
1 2 1 2 1 2 G
PAD-OPEN1x1m S

3
GNDA_CHG 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
GNDA_CHG
Maximum charging current is 7.2A GNDA_CHG ACAV_IN @
B B
GNDA_CHG PQ34
MAX8731_REF RHU002N06_SOT323-3~D
+5V_ALW +3.3V_ALW
+DC_IN MAX8731_REF
100P_0402_50V8J~D

0.01U_0402_25V7K~D

10K_0402_1%~D
DYN_TUR_CURRENT_SET# PR236

47K_0402_1%~D
232K_0402_1%~D
1M_0402_1%~D
1

1
PC244

PC245

221K_0402_1%~D

DYN_TUR_PWR_VO

100K_0402_1%~D
1 2
2

1
PR519

PR235

PR237

PR239
+5V_ALW
90W High
2

PR238
0_0402_5%~D

+3.3V_ALW2 @ @
2

+5V_ALW PR518

2
PR520

1.8M_0402_1%
1

2
8
1 2 PU12A @
130W Low
1

3 PR240

P
PR513 +
1 1 2
1

150K_0402_1%~D PR516 PR517 O 0_0402_5%~D ACAV_IN_NB <40,41,63>

22.6K_0402_1%~D

42.2K_0402_1%~D

41.2K_0402_1%~D
100P_0402_50V8J~D
2 -
8

G
20K_0402_1%~D 0_0402_5%~D PU12B

100P_0402_50V8J~D
1

1
@ PR511 MAX8731_IINP D LM393DR_SO8~D
1 2 1 2 5
P
2

4
+

1
PC242

PR241

PR242

PC243

PR243
649K_0402_1%~D 7 2 PQ43
ICOUT 1 ICREF O G RHU002N06_SOT323-3~D
2 1 2 6 -
G
220P_0402_50V8J~D

S
3

2
PR515 LM393DR_SO8~D @
4

2
1

PC407
174K_0402_1%~D

113K_0402_1%~D

0_0402_5%~D
100P_0402_50V8J~D
1

2
1
PR512

PR514

PC406

@
2
2

2
1

DYN_TUR_CURRNT_SET# 2 PQ59
G RHU002N06_SOT323-3~D
S
3

A A

Adapter Protection Circuit fot Turbo Mode

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401931
Date: Thursday, January 13, 2011 Sheet 61 of 77
5 4 3 2 1
 5 4 3 2 1

D D

PJP35
VCC_SA
VCCSA_PWR_SRC 2 1 +PWR_SRC
ThermalDesignCurrent:4.2A
Peakcurrent:6A

10U_1206_25V6M~D

10U_1206_25V6M~D

2200P_0402_50V7K~D
0.1U_0603_25V7K~D
+5V_RUN PAD-OPEN1x1m
1 1 2
OCPmin:7.2A

1
PC246

PC247

PC249
PC248
2
PC250 2 2 1

1
1U_0603_10V6K~D
1 2 PR244
2.2_0805_5%~D

VCCSA_LGATE

5
6
7
8
VCCSA_VCC

1U_0603_10V6K~D
0.1U_0402_10V7K~D
1

1
PC251

PC252
PQ35

4 AO4466L_SO8~D

2
2

20
1
PU13

LGATE

PVCC

3
2
1
GNDA_VCCSA GNDA_VCCSA
PL18
2 19 1UH_FDVE0630-H-1R0M=P3_11.9A_20%~D
PGND VCC PR245
C 2 1 +0.8V_VCC C

2200P_0402_50V7K~D
2.2_0603_1%~D PC253

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D
330U_D2_2VY_R7M~D
VCCSA_BOOT

0.1U_0402_10V7K~D
GNDA_VCCSA 3 GND BOOT 18 1 2 1 2
1

5
6
7
8

1
0.22U_0603_10V7K~D @ PC254

1
+

PC255

PC256

PC257

PC260
10_0402_5%~D
VCCSA_UGATE 1000P_0603_50V7K~D

AO4406AL_SO8~D
4 RTN UGATE 17

PR246

PC258
1 2

2
2
PQ36

2
VCCSA_VID1 VCCSA_PHASE PR247 2
5 VID1 PHASE 16
4 @PR248
@PR248 12.7K_0402_1%~D

2
2.2_1206_1%~D
VCCSA_VID0 6 15 VCCSA_EN VCCSA_LGATE
PC261

1
+1.05V_RUN VID0 EN

2
2 1

3
2
1
VCCSA_SREF 7 14 VCCSA_PWRGD
SREF PGOOD PR251 .015U_0603_25V7K~D
.068U_0603_16V7~D

0_0402_5%~D
PR253
2

PR250 VCCSA_SET0 8 13 1 2 1.05V_VTTPWRGD <41,58>

SET0 FSEL

1
PC262

@ PR249 113K_0402_1%~D 2 1
0_0402_5%~D VCCSA_SENSE <11>
PR252
1

VCCSA_SET1 9 12 0_0402_5%~D @ PR254

2

SET1 VO CPU_VTT_ON <40,58> 0_0402_5%~D

1 2
OCSET
1

1
10_0402_5%~D
0_0402_5%~D 2 1
FB

<11> VCCSA_VID_1 +3.3V_RUN

1

PR257
GNDA_VCCSA PR255
PR256
10

11

10K_0402_5%~D
2

140K_0402_1%~D GNDA_VCCSA
PR410 1 2 0.8V_VCCPWROK <41>

2
1K_0402_5%~D ISL95870AHRUZ_UTQFN20_1P8X3P2
VCCSA_FB
2

PR258
@ PR260 0_0402_5%~D
PR259
1

4.12K_0402_1%~D VCCSA_OCSET
1 2 1 2
PR262
0_0402_5%~D

47.5K_0402_1%~D
1

VCCSA_VO 2 1
+1.05V_RUN
PR261

GNDA_VCCSA
B 12.7K_0402_1%~D B
2
2

@ PR263
10K_0402_5%~D
1

PR265
2

2 1 +GND_VCC_SA <11>
PR266
1K_0402_5%~D
0_0402_5%~D
1
1

@ PR267
4.12K_0402_1%~D
2

GNDA_VCCSA

A A
PJP37
2 1
0.9V 0.8V
PAD-OPEN1x1m
VCCSA_VID_1 0 1
PJP38
+0.8V_VCC 1 2 +VCC_SA
GNDA_VCCSA
DELL CONFIDENTIAL/PROPRIETARY
PAD-OPEN 43X118
Compal Electronics, Inc.
Title
output voltage adjustable network
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401931
Date: Thursday, January 13, 2011 Sheet 62 of 77
5 4 3 2 1
 5 4 3 2 1

PQ39 PD17
SI4835DDY-T1-GE3_SO8~D 2
1 8 MPBATT+ PR283 1
2 7 1 8 330K_0402_5%~D 3
+VCHGR S D
3 6 2 S D 7
PDS5100H-13_POWERDI5-3~D

0.1U_0603_25V7K~D
5 3 S D 6 1 2

100K_0402_5%~D
4 5 PQ41 PD16
G D

1
390K_0402_5%~D

620K_0402_5%~D
8 S 1 2 1

4
D

1
PR270

PC264

PR271

PR272
FDS6679AZ_SO8~D

0.47U_0805_25V7K~D
7 D S 2
PQ40 MPBATT_IN_SS 6 ES2AA-13-F
D S 3 PQ37
5 G 4

2
D
8 D 1

2
PR274 FDS6679AZ_SO8~D S
7 D S 2
33_0603_5%~D +DOCK_PWR_BAR 6 D 3
S

PC263
1 2 PD18 5 D 4
G

2N7002DW-T/R7_SOT363-6~D
RB751V-40_SOD323~D

1
10K_0402_5%~D

0.22U_0603_25V7K~D
2 1

2
3
PR273 FDS6679AZ_SO8~D

2
D D
PD19

1
2N7002DW-T/R7_SOT363-6~D

PQ42B

PC265
390K_0402_5%~D
RB751V-40_SOD323~D PR268

PR276
2 5 2 1 330K_0402_5%~D

2
2

1
499K_0402_1%~D
PR269

1
6

PR275
0_0402_5%~D

2
PQ42A

0> CHARGE_MODULE_BATT

1
1 2 2

2
PR277 0_0402_5%~D PR278

STSTART_DCBLOCK_GC
330K_0402_5%~D
1

PQ45 1 2 PD20
FDS6679AZ_SO8~D 2
PQ44 PBATT+ 1 S
SI4835DDY-T1-GE3_SO8~D D 8 1
2 S D 7 3
1 8 3 S PBATT_IN_SS
D 6

390K_0402_5%~D
2 7 4 G PDS5100H-13_POWERDI5-3~D
+VCHGR D 5

1
620K_0402_5%~D
3 6 PQ46

PR282
0.1U_0603_25V7K~D

5 8 D S 1

PR281
100K_0402_5%~D

7 D S 2
2

6 S 3 +PWR_SRC
4

D
1
PR279

PC266

2200P_0402_50V7K~D

0.1U_0603_25V7K~D
5 G 4

2
PR284 D

2
2
33_0603_5%~D FDS6679AZ_SO8~D
2

1
PC267

PC268
PR297 1 2
1

20K_0402_1%~D

3
2N7002DW-T/R7_SOT363-6~D
PD21

2
RB751V-40_SOD323~D

0.22U_0603_25V7K~D
1
2 1
5
1

1
PQ49B

PC270
10K_0402_5%~D

390K_0402_5%~D
1
PR286

PD23

4
2
2N7002DW-T/R7_SOT363-6~D

PR291
RB751V-40_SOD323~D

2
6
2N7002DW-T/R7_SOT363-6~D

PR280 2 1
20K_0402_1%~D
2

PQ47A

1
2N7002DW-T/R7_SOT363-6~D

499K_0402_1%~D
C 2 C
1
6

2N7002DW-T/R7_SOT363-6~D

PR292
PQ49A

6
PQ47B

2N7002DW-T/R7_SOT363-6~D
0> CHARGE_PBATT
1 2 2 5

2
3
PQ48A

2N7002DW-T/R7_SOT363-6~D
PR293 0_0402_5%~D

6
2
1

PQ48B
PR287

PQ50A
0_0402_5%~D

PR323
RB751V-40_SOD323~D

1 5 2 MODULE_ON <40>
1
2

RB751V-40_SOD323~D

RB751V-40_SOD323~D

PD30 2 1 2 DEFAULT_OVRDE <40>

PR285

499K_0402_1%~D
0_0402_5%~D
RB751V-40_SOD323~D

1
2 1 0_0402_5%~D

1
2

PR289
PD22

RB751V-40_SOD323~D
1

RB751V-40_SOD323~D
PD24

PD25

PD26

2
@
PD31

2
PR355
1

PBATT+ MPBATT+
PD27
0> CHARGE_EN 1 2 2 1
0_0402_5%~D
200K_0402_1%~D

510K_0402_5%~D
1

1
2N7002DW-T/R7_SOT363-6~D
1

RB751V-40_SOD323~D
2N7002DW-T/R7_SOT363-6~D
PR290

PR471
0_0402_5%~D
3

<40> SLICE_BAT_ON
PR296

3
PQ54B
2

5
2N7002DW-T/R7_SOT363-6~D

PQ50B

@ PR473 100K_0402_5%~D
2
6

5 1 2
2 4
PQ54A

0_0402_5%~D

PR295
4
PR298

1 2 2 <39,40,53> SLICE_BAT_PRES# 0_0402_5%~D

<40> DEFAULT_OVRDE PR294 0_0402_5%~D 1 2 MODULE_BATT_PRES# <40,53>
1
1
499K_0402_1%~D

PBATT+
1
PR288

<40,53> PBAT_PRES# +DOCK_PWR_BAR 1 2

@ PR299 0_0402_5%~D PR301
2

2
B +DC_IN_SS 1 2 0_0402_5%~D B
PR302 0_0402_5%~D @ PR306
0_0402_5%~D
1

<61> +CHGR_DC_IN 1 2
PR305 0_0402_5%~D

1
CHGVR_DCIN

DK_PWRBAR

1 2 CD3301_DCIN
DC_IN_SS

+DC_IN
PR307 47_0805_5%~D
1

PC271

0.1U_0603_50V4Z~D
2

+5V_ALW
P50ALW
36
35
34
33
32
31
30
29
28

1 2
PU14 PR309 0_0402_5%~D
<53> SOFT_START_GC
1 2
DC_IN_SS

PBatt+
NC
CHARGERVR_DCIN

DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC

+3.3V_ALW2
CD_PBATT_OFF 1 2 SLICE_BAT_ON <40>
PR310 100K_0402_5%~D PR311 0_0402_5%~D
<39> ACAV_DOCK_SRC# 1 2ACAVDK_SRC
1 2 DOCK_AC_OFF <39,40>
PR312 0_0402_5%~D 1 27 PR313 0_0402_5%~D
DC_IN P50ALW
2 SS_GC PBATT_OFF 26
+SDC_IN 1 2 ERC1 3 25 DK_AC_OFF 1 2
ERC1 DK_AC_OFF_EN
PR314 0_0402_5%~D 4 ACAVDK_SRC ACAV_IN_NB 24 1 2 3301_ACAV_IN_NB ACAV_IN_NB <40,41,61>
5 23 PR3160_0402_5%~D 1M_0402_5%~D
CD3301_SDC_IN GND GND DK_AC_OFF_EN PR315
6 SDC_IN DK_AC_OFF_EN 22 1 2 DOCK_AC_OFF_EC <40>
7 21 SL_BAT_PRES# PR317 0_0402_5%~D
<61> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC
8 ACAV_IN BLKNG_MOSFET_GC 20
P33ALW2 9 19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR

<22,41,61> ACAV_IN 1 2
SS_DCBLK_GC

PR318 0_0402_5%~D
DK_CSS_GC
RB751V-40_SOD323~D

1 2 SLICE_BAT_PRES# <39,40,53>
PWR_SRC

PR320 0_0402_5%~D
RB751V-40_SOD323~D

CSS_GC

P33ALW

37 TP
1

ERC3
ERC2

1 2 1 2
GND

+3.3V_ALW2 +NBDOCK_DC_IN_SS
PD29

PD28

PR319 0_0402_5%~D PR322 0_0402_5%~D

CD3301RHHR_QFN36_6X6~D
10
11
12
13
14
15
16
17
18

A PQ51 A
2

0.1U_0603_25V7K~D

FDN338P_NL_SOT23-3~D <61> CSS_GC P33ALW 1 2

ERC2

<61> DK_CSS_GC +3.3V_ALW

PR324 0_0402_5%~D
1
PC273

ERC3
1

1 3 DOCK_SMB_ALERT# <39,41,53>
EN_DK_PWRBAR
0.047U_0603_25V7K~D

1 2 EN_DOCK_PWR_BAR <40>
2

PR325 0_0402_5%~D
0.1U_0402_25V4Z~D

DELL CONFIDENTIAL/PROPRIETARY
2
2

PR321 1 2
PC274

40,53> SLICE_BAT_PRES# 1 2
1

1M_0402_5%~D
PC275

0_0402_5%~D STSTART_DCBLOCK_GC
@ PR326
Compal Electronics, Inc.
1

Title
2

PC272 @ 3301_PWRSRC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1500P_0402_7K~D
1
PR327
2
0_0402_5%~D
+PWR_SRC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
2

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 63 of 77
5 4 3 2 1
 5 4 3 2 1

D D

GPU_CORE
PJP39
+GPU_PWR_SRC 1 2 +PWR_SRC
ThermalDesignCurrent:15.615A
Peakcurrent:20.2A

10U_1206_25V6M~D

10U_1206_25V6M~D

2200P_0402_50V7K~D
PAD-OPEN 43X118

0.1U_0603_25V7K~D
+5V_RUN
1 1 2
OCPmin:24.2A

1
PC276

PC277

PC279
PC278
2
PC280 2 2 1

1
1U_0603_10V6K~D
1 2 PR328
2.2_0805_5%~D

5
PQ52
GPU_CORE_VCC

GPU_LGATE

AON6414AL 1N DFN
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1

1
PC281

PC282
4

2
2

20
1
PU15

LGATE

PVCC

3
2
1
GNDA_GPU_CORE GNDA_GPU_CORE PL19
0.56UH +-20% MPC1040LR56C 23A
2 PGND VCC 19
C PR329 4 1 +VCC_GPU_CORE C

2200P_0402_50V7K~D
2.2_0603_1%~D PC283

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D
GPU_BOOT1

0.1U_0402_10V7K~D
GNDA_GPU_CORE 3 GND BOOT 18 2 1 2 3 2
1 1

1
0.22U_0603_10V7K~D @ PC284

1
+ +

PC286

PC287

PC288
10_0402_5%~D
4 17 GPU_UGATE PQ53 1000P_0603_50V7K~D

AON6704L_DFN8-5
RTN UGATE

PR330

PC285
1 2

2
2

2
GPU_VID1 GPU_PHASE PR332 2 2
5 VID1 PHASE 16
4 @PR331
@PR331 5.9K_0402_1%~D

2
2.2_1206_1%~D
GPU_VID0 6 15 GPU_EN GPU_LGATE
PC289

1
+3.3V_RUN VID0 EN

2
2 1

3
2
1
SREF 7 14 GPU_PWRGD
SREF PGOOD 0.15U_0603_16V7K
.056U_0603_16V7~D

1
2

PR334 SET0 8 13 1 PR335 2 GNDA_GPU_CORE PR336

SET0 FSEL
PC290

@ PR333 30.1K_0402_1%~D GPU_OCSET 1 2 GPU_VDD_SENSE <49>

10K_0402_5%~D 0_0402_5%~D
1

SET1 9 12 0_0402_5%~D
2

SET1 VO
OCSET
1

PR337
PR339
2 1
FB

<47> GPU_VID_1
1

GNDA_GPU_CORE GPU_VO 2 1
0_0402_5%~D PR338
10

11
2

71.5K_0402_1%~D ISL95870AHRUZ_UTQFN20_1P8X3P2
PR340 5.9K_0402_1%~D
10K_0402_5%~D
2

PR403
2 1
1

412K_0402_1%~D
1

38.3K_0402_1%~D
PR341

10_0402_5%~D
PR344

1
GPU_FB 2 1

PR402
+3.3V_RUN 3.09K_0402_1%~D
2

B B

2
PR346
2

GNDA_GPU_CORE 5.11K_0402_1%
PR343
10K_0402_5%~D
2
1

PR345
<47> GPU_VID_0 2 1
GNDA_GPU_CORE
2

0_0402_5%~D
@ PR347

10K_0402_5%~D
PR404
1

0_0402_5%~D
PR400
2 1 2 1 GPU_GND_SENSE <48>
3.09K_0402_1%~D
1

PR401
5.11K_0402_1%
2

+3.3V_RUN
2

GNDA_GPU_CORE
PR348
10K_0402_5%~D
PJP41
PJP40
1 2 2 1
1

1 2 GPU_PWRGD
<18,40> DGPU_PWROK
PAD-OPEN 43X118
PR349 PAD-OPEN1x1m
A A
0_0402_5%~D PJP42
+VCC_GPU_CORE 1 2 +GPU_CORE
GNDA_GPU_CORE
1.025V 1V 0.85V 0.8V PAD-OPEN 43X118

GPU_VID_0 0 1 0 1
2 1 GPU_EN
<11,38,40,43,56> RUN_ON
@ PR350 0_0402_5%~D GPU_VID_1 0 0 1 1 DELL CONFIDENTIAL/PROPRIETARY
2 1
Compal Electronics, Inc.
<40> DGPU_PWR_EN
PR351 0_0402_5%~D Title
output voltage adjustable network
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATICS,MB A6561
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401931
Date: Thursday, January 13, 2011 Sheet 64 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 7 HW 6/15/2010 COMPAL Boot issue Change QC1 control from SUS_ON to RUN_ON_CPU1.5VS3# X01

2 11 HW 6/15/2010 COMPAL Modify net name Change +0.8V_VCC_SA to +VCC_SA X01

Change capacitors from 10uF_0805_10V Y5V to 10uF_0805_6.3V_X5R:

22,28,32,40
C305,C387,C462,C705,C728,C760,C764,C765,C768,C769,
41,43,11,20
C772,CC135,CH58,CH73,CH80,CV124,CV126,CV185,CV187
50,38 Follow PPM recommendation to change X01
3 6/15/2010 COMPAL Change capacitors from 10uF_0805_6.3V to 10uF_0603_6.3V:
HW material
C475,C638,C641,C643
Change resistors to 0402 size: RC134, RH201,RH253,RH208,RH213
Delete RH192 and add PJP66

4 14 HW 6/15/2010 COMPAL De-pop PCH XDP De-pop RH1,RH3~RH10,RH12~RH21,RH24,RH283~RH285,CH1 X01

5 14 HW 6/15/2010 COMPAL Change HDA_SYNC topology Add QH7 and RH37 X01
C C
1. Change ODD connector to 31 pin,
6 29 HW 6/15/2010 COMPAL Change ODD connector from 13 pin to 31 pin X01
2. Remove T157~T167,T169, U87~U89,C1168~C1170,R1181,R508.
3. Add Q123, Q76,R516,R514.
4. Change R510,R1177 power rail to +3.3V_ALW. X01

8 18 HW 6/17/2010 INTEL Follow Intel Design Guide Rev1.0 Change RH149 to 1k and RH150 to 4.7k X01

9 22 HW 6/17/2010 COMPAL Change EMC4002 to EMC4022 Change U9 to EMC4022, remove R392,R394 R866,R404,C279,R866, Reserve C277 X01

10 25 HW 6/17/2010 COMPAL Change CRT SW to MAX14885 Change CRT SW to MAX14885 and add C1181,C1182,R1581,remove C325~C336 X01

11 26 HW 6/17/2010 COMPAL Safety request Add no stuff D4 and co-lay with F2, change F2 to 2A_8V X01

Chagne U44 to MAX4591BE and Reserve R1189~R1196 for bypass repeater

12 45 HW 6/17/2010 COMPAL Change E-SATA repeater to MAX4951BE X01

B B
Change Codec to ZB version. Change U72 to ZB version as 92HD90B2X5NLGXZBX8 and stuff C962 X01
13 30 HW 6/17/2010 COMPAL
X01
14 41 HW 6/17/2010 COMPAL Board ID Change R875 to 130K
X01
15 34 HW 6/17/2010 COMPAL Change SI2301BDS to C version Change Q36 to SI2301CDS

16 34 HW 6/17/2010 BRCOM Change RFID capacitors for more popular Change C502,C505 from 1uF to 0.1uF X01

17 18 HW 6/17/2010 COMPAL Remove touch screen PAID pull down circuit Remove RH241 X01

18 47 HW 6/17/2010 BIOS request Reserve RV29, De-pop DV1, RV29 and pop U14 X01
COMPAL

19 46 HW 6/17/2010 COMPAL ME request Change the JBTB1 to TYCO_2041300-2 connector X01

20 23 HW 6/17/2010 COMPAL LVDS SW change to PI3LVD400ZFEX 1.Change U84, U85 to PI3LVD400ZFEX X01
A A
2.Remove Q209,Q210, U91,U90
21 41 HW 6/17/2010 COMPAL Change BAY_SMBDAT and BAY_SMBCLK pull-up X01
Change R854, R856 pull up power rail to +3.3V_ALW
resistors to +3.3V_ALW DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 65 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
22 11,14,41 HW 6/18/2010 COMPAL EOL concern Change CC176 to SGA00005H0L, change YH1, Y6 to SJ132P7KW1L X01
Change JKB1 to same as JSC1
23 42 HW 6/18/2010 COMPAL Change connector X01
Change JLED1 to TYCO_1-2041084-6
24 42 HW 6/18/2010 COMPAL Change TP pin definition Reverse TP pin definition for PT X01

Add series resistor and pull up resistors

25 40,41 HW 6/18/2010 COMPAL Add R773,R806,R884,R886,R887,R1169,R1170,R1197 X01
on MIC_MUTE#, VOL_MUTE,VOL_UP,VOL_DOWN

Modify signal name BREATH_BLUE_LED to BREATH_WHITE_LED and

26 24,44 HW 6/18/2010 COMPAL Correct net name for LED signal X01
BREATH_BLUE_LED_SNIFF to BREATH_WHITE_LED_SNIFF

Add HPD circuit to inform system for NV Add DV2,DV3,DV4,R1154 and use ECE5028 GPIOE7/DCD# as HPD signal to
27 40,47 HW 6/21/2010 NVIDIA X01
request inform system

28 32 HW 6/21/2010 INTEL Remove useless resistors Remove R556, R558, R559, R560 and short the pin1 and pin2 together X01
C C

24,28,30,
29 HW 6/22/2010 COMPAL Change part for Halogen free Change Q18,Q27,Q30,Q34,Q38,Q40,Q42,Q49,Q54,Q58,QV5 to HF part X01
32,38,43,50
30 10 HW 6/22/2010 COMPAL To have better return path De-pop CC130 and pop CC134 X01

31 43 6/23/2010 COMPAL Solution +1.5V_RUN voltage drop issue Change Q59 from SI3456BDV to NTGS4141NT1G X01
HW
Add serial damping resistor R935 47 ohm on SPI_CS0#, R936 22ohm on
32 14 HW 6/23/2010 COMPAL Add serial damping on SPI_CS0#,SPI_CS1# to X01
SPI_CS1#
avoid SPI EA fail issue
33 24 HW 6/25/2010 COMPAL PT panel change touch screen pin definition Change JTS1 pin definition for new TS pin define X01

34 43 HW 6/25/2010 COMPAL NTMS4107NR2G EOL Change Q55 to NTMS4920NR2G X01

35 14 HW 6/25/2010 COMPAL Follow Intel XDP design Change RH43,RH44,RH45 to 200 ohm X01

36 24 HW 6/25/2010 COMPAL Change LVDS connector to 40 pin Change JLVDS1 to 40 pin as ACES_59003-0400C-001 X01
B B

37 14,41,29 HW 7/1/2010 COMPAL Modify Module Bay circuit 1.Remove R1181,R1182,R1189. 2.Change BAY_SMBUS, DEVICE_DET# pull up X01
power rail from +3.3V_RUN to +3.3V_ALW. 3.Change net name ODD_DET# to
PCH_SATA_MOD_EN#. 4.Add Q123,Q76,R513,R514,R515 for USB_SMI# circuit.
5.De-pop C627,R712

38 24 HW 7/1/2010 COMPAL Stuff PWM pull down resistor for PT solution Pop R1137 X01

39
7 HW 7/1/2010 COMPAL For support XDP device De-pop RC9 X01
15,18, HW 7/1/2010 COMPAL Base on GPIO map to modify 1. Move SLP_ME_CSW_DEV# from GPIO45 to GPIO28, add MCARD_PCIE_SATA# on X01
40
40,41 5028 GPIOE3. 2. Remove RH238, change RH80 from 1k to 10k. 3. Change
SLICE_BAT_PRES# pull up power rail from +3.3V_ALW2 to +3.3V_ALW. 4. Add
R889
X01
41 24 HW 7/1/2010 COMPAL PWM function Remove R1139,R1140 and add D68,D69
A A

42 11 HW 7/1/2010 COMPAL VCCSA VID circuit Change VCCSA_VID_0 to VCCSA_VID_1 and pop RC138 X01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 66 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D Remove C268,C269, use DP1/DN1 for CPU,DP2/DN2 for GPU, DP3/DN3 for D
43 22 HW 7/2/2010 COMPAL Modify thermal diode for thermal request X01
DIMM, DN5/DP5 for WWAM
1. CH18, CH19 change to 10P_0402_50V8J~D
44 15,14,47 HW 7/8/2010 COMPAL Meet Crystal EA chnage caps value. X01
2. CH2, CH3 change to 15P_0402_50V8J~D
3. CV34, CV35 change to 12P_0402_50V8J~D
X01
45 47 HW 7/8/2010 COMPAL U14 power pin add 0.1uF bypass cap. Add CV188 0.1uF CAP at U14.5 pin X01
O2 suggest
1. Add R1198~R1206 33 ohm
1. add the damping resistors 33ohm on the
2. RE7 change to 33 ohm
46 36 HW 7/12/2010 COMPAL (SD/MMCDAT0-7 and SD/MMCCMD)
3. R680 chnage to 191 ohm X01
2. change the resistor RE7 on the SD/MMC_CLK
to 33ohm.
3. OZ600RJ1N rev.B PE_REXT change resistor
X01
EMC request
1. L51,L50 change to POP, R734~R737 change to De POP.
1.Add 90 ohm common mode choke L50,L51
C 2. Reserve CH7 150P C
at USBP0+/- and USBP1+/- for USB R/W noise X01
47 45,29 HW 7/12/2010 COMPAL 3. add LE2 220 ohm bead instead of R1106.
2. Reserve 150pF bypass capacitor at ODD
4. add RE9 0 ohm at BIA_PWM_LVDS
DEVICE_DET#
3.Add 220ohm Bead at DMIC_CLK for DMIC noise
4.Add 0 ohm at BIA_PWM_LVDS check UMA mode
whether have PCI noise

48 24,45 7/13/2010 COMPAL PPM recommendation to change material 1.C300, C669 from 10U 16V Y5V 1206 change to 10U 10V Z Y5V 0805 X01
HW
49 41 HW 7/13/2010 COMPAL SMSC request R864 and R865 can be depopulated
X01
1.I2S_CLK, I2S_WS pull down resistors
depopulated

50 33 HW 7/15/2010 COMPAL Hi-Pot EA Fail JLOM1.14 change to NC, JLOM1.15 change to GND net,Remove C1165,C1166 X01

51 37,44 HW 7/15/2010 COMPAL Modify LED circuit Remove R1578,R1579,R1580,D42,D60,D61, add Q77,Q124,R705,R718,R719 X01
B B

52 26 HW 7/15/2010 COMPAL Meet HDMI EA, EMI 1.L19,L20,L21,L22 change to Populated X01
2.R470,R471,R468,R469,R462,R466,R451,R459 change to Depopulated
53 37 HW 7/15/2010 COMPAL MINI card CONN from H9.9 change to H9 JMINI1,JMINI2,JMINI3 change to LOTES_AAA-PCI-047-P10-A X01

54 44 HW 7/15/2010 DELL 1.Remove MIC MUTE LED circuit, 1.Remove the R1108,Q119,R1061,Q105 parts as MIC mute circuit X01
2.Reserve SPK MUTE LED circuit 2.Reserve the R1109,Q119,Q102,R1059 parts as SPK mute circuit,
Change Q119 to SSM3K7002FU

55 14,17,18 HW 7/16/2010 COMPAL Follow GPIO MAP 1.Remove R1567~R1577. X01

40,41 2.U46.B64,A9,A18,A44,B39,B51 connect to GND direct.
3.R796 Net rename to DYN_TURB_PWR_ALRT# then change to 10K value and
pull up to +3.3V_ALW power rail.
4.Add GPIO DYN_TUR_CURRNT_SET# TO U51.A35 and add R1171 10k pull up.
5.SIO_EXT_SMI# GPIO form PCH.GPIO1 change to PCH.GPIO14 and add RH51
A
10kohm Pull up A
6.RH164 change to PCH_GPIO1 net. and remove RH254
X01
56 33 HW 7/19/2010 COMPAL ME change reuqest JLOM1 change to TYCO_2010019-3 DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 67 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
57 36 HW 7/19/2010 COMPAL OZ600RJ1 from A change to B version U39 change to OZ600RJ1LN-B_QFN48 X01

58 20,43 HW 7/19/2010 COMPAL Cost reduction as +3.3V_ALW_PCH and 1.Add PJP68 bypass JUMP for +5V_ALW to +5V_ALW_PCH
X01
+5V_ALW_PCH power control circuit 2.QH4,CH98,RH278 change to NON-POP
3.Add PJP67 bypass JUMP for +3.3V_ALW to +3.3V_ALW_PCH
4.Q51,R907,R905,C762,C760,R908,Q49 change to NON-POP
59 24 HW 7/20/2010 COMPAL Add BIA_PWM_GPU to control BIA_PWM_LVDS D63 change to POP X01

60 24 HW 7/20/2010 COMPAL Meet LCD power sequence spec R413 change to 470 ohm X01

61 24 HW 7/20/2010 COMPAL Corrent Touch screen pin define Modify JTS1 pin define X01

62 29 HW 7/20/2010 COMPAL Q107 change to one channel Q107 change to SSM3K7002FU_SC70-3~D X01

63 47 HW 7/20/2010 NV Follow NV request Add @RV103,RV104, @RV20,@RV25,@RV26 X01

C C

64 17,30,39 HW 7/20/2010 COMPAL EMC team request 1.I2S_12MHZ add @RE13

X01
2.I2S_BCLK add @RE10.
3.CLK_PCI_DOCK, RH103 change to 33ohm, R756 change to 33 ohm,
C704 change to 12pf
4.DAI_BCLK# add@RE12,@CE9
5.DAI_12MHZ# add @RE11,@CE8

65 26 HW 7/21/2010 COMPAL Safety team request Modify HDMI power circuit about D4,F2,R5 X01
parts

66 37 HW 7/21/2010 COMPAL DF398754 Debug reserve Reserve R725 0 ohm both PCIE_MCARD2_DET#R to PCIE_MCARD2_DET# X01

67 36 HW 7/21/2010 COMPAL Meet 1394 EA SPEC R683,R684,R685,R686 from 56.2 change to 53.6 ohm X01

68 36 HW 7/21/2010 COMPAL Add MS card function Modify U39 and JSD1 circuit X01
B B

69 30 HW 7/22/2010 COMPAL EMI snubber and change Audio net name 1.Change net name from I2S_12MHZ to I2S_MCLK X01
2.Reserve R1587~R1590 part at INT_SPK bus
70 41 HW 7/22/2010 COMPAL New GPIO MAP 1.Pull up R943 to +3.3V_ALW on XFR_ID_BIT# of ECE5055-GPIO105 X01
2.R712,R711,C627 change to de-pop

71 40 HW 7/23/2010 COMPAL TEMP_ALERT# Add 0 ohm jump between EC to PCH Add R738 ohm at TEMP_ALERT# X01
Follow GPIO map to add touch screen power Add TOUCH_SCREEN_PD#, Q125,Q32,R430,R431,C304,C306, and change JTCH1
72 24,42 HW 7/24/2010 COMPAL X01
down control circuit pin 1,pin2 from +5V_RUN to +5V_TSP

73 24 HW 7/26/2010 COMPAL Reserve a 0 ohm option between +5V_RUN and Reserve R1001 0 ohm 0603 between +5V_RUN and +5V_TSP X01
+5V_TSP

74 44 HW 7/26/2010 COMPAL Due to BT_ACTIVE was folating pin, Add R944 100K ohm for BT_ACTIVE pull down X01
so, add 100 Kohm pull down
A A

De-pop CV184, and change CV183 to 1uF,CV182 to 4.7uF, CV109 to

75 49 HW 7/28/2010 NV Follow NV suggestion to modify BOM X01
470pF,CV110 to 4700pF, LV8 to 100nH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 68 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
76 24 HW 9/06/2010 COMPAL In order to use the HF part. Q21 change SB000009K0L to SB000009K1L X02

77 14,18 HW 9/06/2010 Intel Follow Intel request Add RH52 and RH53. X02

78 38,45 HW 9/15/2010 COMPAL For the part consist issue. L49,L50,L51 change SM01002080L to SM070001E0L X02

79 45 HW 9/17/2010 COMPAL Remove Bypass ESATA Repeater schematic, Remove R1189~R1196. X02
because Gen1 EA fail when Bypass ESATA
Repeater.

80 15,36 HW 9/17/2010 H.ELE. YH2's CL value can't match cd & cg value. CH18 & CH19 change from 10P to 22P, X02
Y5's value too low that frequency shift of C591 & C592 change from 10P to 6.8P.
PCB board.

81 47,48,49 HW 9/21/2010 DELL Macallan DIS performance request. UV change from N12M to N12P. X02
50,51,52
C C

82 30 HW 9/23/2010 IDT MIC detect issue. U72 change version from SA00003ZZ1L(ZB) to SA00003ZZ2L(YA). X02

83 47 HW 9/23/2010 COMPAL De-pop pull up resistors De-pop RV23,RV24 X02

84 18 HW 9/23/2010 Intel Follow Intel design guide Rev1.2 Change RH149 to 2.2k and RH150 to 0 ohm X02

85 32 HW 9/23/2011 Intel Intel request U31 change version from WG82579LM QMWM A2 to WG82579LM QNGP C0. X02

86 15,32 HW 9/24/2011 H.ELE. modify item 80 CH18 & CH19 change from 22P to 10P and YH2 change from CL=18pF to CL=12pF. X02
YH2's CL value can't match cd & cg value. C470 & C471 change from 33P to 18P and Y3 change from CL=18pF to CL=12pF.

87 34 HW 9/24/2011 Broadcom Broadcom request Add decouping cap C556 for U35 on layout. X02

88 24 HW 9/24/2011 COMPAL The PWM can not function correct. R1137 change from 100K to 10K. X02
B B
89 41 HW 9/24/2011 EPSON The frequency skew of Y6 is too big in C741 & C743 change from 33P to 39P, X02
Normal temperature.

90 36 HW 9/25/2011 COMPAL Correct the 53.6 ohm into L end part number. Change the R683,R684,R685,R686 to SD00000HE8L X02

91 46 HW 9/25/2011 COMPAL Add bypass cap at IO board connector Add bypass cap C1183 at +5V_ALW. X02
of MB side.

92 38 HW 9/25/2011 COMPAL Correct the Express Card PWR S/W into Change the U41 to SA00001SL2L. X02
L end part number.

X03

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 69 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D 93 47,48,49 HW 9/27/2010 NVIDIA NVIDIA request. 1. CV160~CV162 change to 1uF X02 D

,51,52 2. Change CV41/42/43/50/51 to 0.022u

3. Change CV40/58/59/60 to 0.1u
4. No stuff CV58/44 on DSC
5. Change CV181 to 22uF_0805
6. Change +SP_PLLVDD to +PLLVDD and remove CV182,CV183,CV184,CV115,LV8
7. Change LV3 to SM01000BE0L
8. Change CV34/35 to 18pF
9. Reserve 1x1mm jumper and contact to PEX_SVDD_3V3.
10. CV90 placement under GPU
11. Change CV80 to 4.7u.
12. Add 2pcs of 1uF per VRAM
13. Change RV81,RV86 to 160_1%
14. Add 10K pull-down to UV1.J5
15. Add 40.2K_1% pull down on UV1.T6

C 94 36 HW 9/28/2010 O2Micro O2Micro request. 1. Move C582 to +MMI_1394_VCCH and close to either one pin 28 or pin 33. X02 C

2. Move C581 to +MMI_PE_VDDH and close to pin1.

3. Add a 0.01uF capacitor on +MMI_PE_VDDH and close to pin1.

95 30,31 HW 9/30/2010 IDT To solve pop noise and detect issue Add U6,Q33,Q46,D70,D71,R425,R33,R38,R424,R161,R352,R1088,C967,C307,C308 X02
Q107 change from SB00000960L(3pin) to SB00000DH0L(6pin)

96 30 HW 9/30/2010 COMPAL EMC request Add bypass cap C1185~C1188 X02

97 14,09 HW 10/04/2010 Intel Following Intel DG ver1.5 1. Add RH31 pull down resister. X02
2. RC96,RC97 no stuff

98 34 HW 10/04/2010 Broadcom Broadcom request(enhancement current amount) L39 & L40 change from SHI00005Y0L(0603 size) to SHI0000CH0L(0805 size X02
rate current is 400mA).

99 11 HW 10/04/2010 COMPAL Change QC5 VGS MAX rating from 12V to 20V Change QC5 from SB52302028L to SB00000HK0L X02
B B

100 24,26,47 HW 10/04/2010 COMPAL Change RB751V to HF part Change D53,D63~D69,DV1~DV4 to SCS00004L0L X02

101 7,18,41 HW 10/04/2010 COMPAL For cost saving Remove RH159,RH261 X02

102 30 HW 10/06/2010 COMPAL 1. Sync-up with Macallan 14" 1. Remove R1587~R1590, C1185~C1188, change R1183~R1186 to L91~L94 X03
2. EMC request 2. Change Audio signal's diode from 4 of 2pins(SD05.TCT) to 2 of 3pins
(PESD5V0U2BT SCA00000T0L)

103 38 HW 10/06/2010 COMPAL In order to enable Express Card PWR S/W Add connection of pin4,pin5,pin13 and pin14 to power net. X03
2nd source vendor "GMT" to act.

104 26 HW 10/06/2010 COMPAL Follow safety request Pop F2 and de-pop R5 X03

105 53,14 HW 10/06/2010 COMPAL Remove PAID function of RTC 1. JRTC1 change from 3pin to 2pin(SP02000CA0L) and remove detect pin X03
2. UH4.C36 & RH355.2 rename from RTC_DET# to PCH_GPIO33
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 70 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D 106 29 HW 10/06/2010 COMPAL For power saving Increase JSATA2 detect pin R1177 from 1k to 100kohm X03 D

107 46 HW 10/07/2010 COMPAL For NB board space consider. Remove page46 two block MIC detect schematic to IO/B. X03

108 28 HW 10/07/2010 COMPAL For cost saving De-pop the R505,Q28,R500,R499,C393,C394,R504 parts. X03

109 32 HW 10/07/2010 COMPAL Based on IEEE Return Loss EA fail L30~L37 change from SHI00004O0L(22NH) to SHI00005I0L(12NH) X03

110 28 HW 10/07/2010 COMPAL Based on support SSD HDD Add +3.3V_RUN on JSATA1 pin8,pin9,pin10 X03

111 47 HW 10/07/2010 COMPAL solve systen can't boot in UMA only mode. correct from U14 to UV14 and change the PN to SA00003Y00L. pop RV29. X03

112 30,32,40 HW 10/07/2010 COMPAL GPIO MAP update at 1-Oct-10 1. Add U15, C478 that defect RJ45 cable insert or not if plug in then X03
42 close WLAN power.
2. 5048 GPIOB7 rename from AUD_NB_MUTE to AUD_NB_MUTE#

C 113 18,30 HW 10/08/2010 COMPAL Remove PAID function of speaker 1. JSPK1 change from 6pin to 4pin(LTCX002V50L) that remove detect pin X03 C

2. UH4.D40 & RH269.2 rename from SPEAKER_DET# to GPIO17

114 48,49 HW 10/08/2010 nVIDIA Follow nVIDIA suggest 1.Move CV74 to contact +3.3V_RUN_VDD33 not +3.3V_RUN_GFX X03
2.RV41 change to 4.99K 1% and RV99 change to 20K 1%.

115 44 HW 10/11/2010 COMPAL LED brightness test result change R957 to 1K, R955, R941, R949, R939, R934 to 4.7K X03

116 41 HW 10/11/2010 COMPAL BORAD_ID change R875 to 62K. X03

117 17 HW 10/11/2010 Intel Follow Intel check list Rev1.2 Add @RH332 X03

118 31,41 HW 10/12/2010 DELL DELL DM Dennis has confirmed. No stuff “Latitude On” button of SW2,R877,C740 X03

119 24,45 HW 10/13/2010 COMPAL EMC request(for cost saving) 1.UE1,UE2,U13,U86 change from PRTR5V0U2X(SOT143-4)(4pin)to X03
PESD5V0U2BT(SOT23-3)(3pin) SCA00000T0L.
B
2.Diode for UE1,UE2 shall be added, not reserved. B

3.Rename UE1 to D73,UE2 to D72,U86 to D74,U13 to D75

120 28 HW 10/13/2010 COMPAL Follow 14" PJP71 size change to 1X1 X03

121 7 HW 10/14/2010 COMPAL UC1.4 is OD pin,so remove pull down R. Remove RC11 X03

122 22,47,48 HW 10/14/2010 nVIDIA Follow nVIDIA suggest 1.Change R1111 to 10K for power saving. X03
49 2.No stuff of CV188,RV50,CV159 and stuff of RV56,RV41,RV99,CV58
3.Change RV51 to 45.3K, CV109 & CV110 to 0.1uF

123 30 HW 10/14/2010 COMPAL Audio team Paul’s agree the EMI solution. Stuff of C973~C976 X03

124 28 HW 10/15/2010 COMPAL MikeCC suggest Stuff of R505,C394,R504 X03

125 14,18 HW 10/19/2010 COMPAL Follow Intel debug port DG Connect PCH_GPIO15 to PCH XDP_FN16 X03
A A
126 30 HW 10/19/2010 COMPAL Change Mic detect to external detect Remove R161 and add C1165 X03
127 51,52 HW 10/25/2010 DELL DELL request Change VRAM from 128Mx16 to 64Mx16 X03

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 71 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D 128 30 HW 11/10/2010 COMPAL Modify Mic detect circuit 1.Move C1180 to +VREFOUT_R X04 D

2.No stuff C967,R352,R1088

129 14~21 HW 11/10/2010 COMPAL Change PCH stepping Change UH4 to B2 stepping X04

130 18 HW 11/16/2010 COMPAL Follow check list Rev1.0 Change RH177 from 1k to 10k X04

131 15 HW 11/16/2010 COMPAL To fix ME issue De-pop RH296,RH297; pop QH5,RH302,RH303 X04
(transition fail S3/Moff->S3/M3)

132 47 HW 11/19/2010 NV Solve HDMI audio issue De-pop RV41, change RV97 to 34.8K and stuff it X04

133 47 HW 11/19/2010 NV Chagne Device ID to 0x1056 De-pop RV51,change RV57 to 34.8k and stuff X04
De-pop RV60, change RV54 to 10k and stuff it, change RV52 to 4.99k

134 47,48, HW 11/19/2010 NV Change GPU to QS sample Change UV1 to N12P-NS-S-A1 X04
C 49,50 C

135 28 HW 11/19/2010 Intel Follow Intel CRB design Change R501,R502 to 10k X04

136 38 HW 11/19/2010 COMPAL To fix soldering issue Change express card connector JEXP1 to TAISOL 5-421005002000-9 X04

137 45 HW 11/19/2010 COMPAL To fix pericom ESATA Repeater Stuff R745 that channel A from preemphasis to standard SATA of Pericom. X04
that PA internal pull high.

138 47 HW 11/26/2010 COMPAL Correct the DGPU_HOLD_RST# behavior. Reserve Pull-up resistor RV30 to DGPU_HOLD_RST#,but de-pop RV30. X05

Remove Resistor between +3.3V_ALW_PCH_JTAG

139 14 HW 11/26/2010 COMPAL Remove RH288. X05
and +3.3V_ALW_PCH.

140 41 HW 12/06/2010 COMPAL Follow INTEL DG1.5 RSMRST# timing cicuit Just add RSMRST# circuit for backup. but de-pop. X05
B B

GPIO17 for interior MIC and exterior MIC Reserve pull-down resistor RH273 to GPIO17,but De-pop RH273.
141 18 HW 12/07/2010 COMPAL X05
detect function.
142 41 HW 01/07/2011 COMPAL BOARD ID. Change R875 from 62k to 33k. A00

143 35 HW 01/07/2011 COMPAL PWM and backlight timing issue. Reserve 74AHC125 circuit for BIA_PWM_GPU, but de-pop. A00

144 35 HW 01/07/2011 COMPAL Modify TPM/TCM configuration table. Update USH BCM5882 and China TCM Z8H172T Option table. A00

Change 119pcs 0402 0 ohm resistors and 3pcs 0603 0 ohm footprint to new
145 ALL HW 01/11/2011 COMPAL For cost saving A00
footprint which is short pin1 and pin2 .

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 72 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 73 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 74 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Change PQ6 from SI4128 to AO4466L.
1 54 +3V/+5V 7/5 Compal +3.3V phase node over Mosfet Vds rating Change PQ8 from SI4134 to AO4712L.
D D

Remove PR264 and add PR410 connect PR249.1 to do PD. Remove VCCSA_VID_0
net to connect PR249.1 and change net name to VCCSA_VID_1
Change PR250 from 34K to 113K
Change PR256 from 0 to 140K
2 62 0.8V_VCCSA 7/5 Intersil VCCSA spike issue Change PR261 and 265 from 2.49K to 0 ohm.
Change PD resister PR266 and PR410 to 1K.
Depop PR249, PR260 and PR267
Change PR259 from 274K to 47.5K

3 53 7/19 Compal Add 150pF bypass capacitor for PCI noise Add PC400 to connect PR14.1 and gnd
+DCIN

Change PC56 and PC57 to 330U/9m/2V (SGA20331E0L) from 330U/9m/2.5V

4 55 +1.5V_SUS 7/19 Compal Vendor will not support this part (SGA19331D1L)

5 53 +DCIN 7/19 Compal PL3 and PL4 current rating is not enough Change PL3 and PL4 to FBMA-L18-453215-900LMA90T (SM01002078L) from
C for 130W adapter FBMJ4516HS720NT(SM010009C8L) C

Change PL1 to FBMJ4516HS720NT(SM010009C8L) from FBMA-L18-453215-

PL1 current rating is not enough for 9cell 900LMA90T (SM01002078L)
6 53 +DCIN 7/19 Compal (3.0Ah 1C) discharge current
Add PL22 FBMJ4516HS720NT(SM010009C8L)
Take off PJP45

7 53 +DCIN 7/19 Compal PR16 down size to 0402 from 0805 Change PR16 to 100k/0402 (SD02810038L) from 100k/0805 (SD01510038L)

8 54 +3V/+5V 7/19 Compal PC24 down size to 0603 from 0805 Change PC24 to 4.7u/6.3V/0603 (SE107475K8L) from 4.7u/6.3V/0805
(SE093475K8L)

Reserve 300K PD to avoid VR turn on when

9 55 +1.5V_SUS 7/19 Richtek EN/DEM is floating. Add PR508 to do PD from PU3 pin1

Change PD14 to ES2AA-13-F (SC100005A0L) from SBR3A40SA-13_SMA2

10 61 Charger 7/19 Compal solve leakage issue (SC100003J00)

B Change PD16 to ES2AA-13-F (SC100005A0L) from SBR3A40SA-13_SMA2 B

11 63 Selector 7/19 Compal solve leakage issue (SC100003J00)

12 58 +1.05V_VTT 7/19 Compal Remove PC147 for ME Interfere Remove PC147

Change PQ35 from SI4128 to AO4466L.

13 62 0.8V_VCCSA 7/19 Compal VCCSA phase node over Mosfet Vds rating Change PQ36 from SI4172 to AO4712L.

14 59 VCORE 7/19 MAXIN Fine tuning VCORE Load Line Change PR140 to 11.8k(SD03411828L) from 12.6k(SD00000AJ8L)

Reserve 33nF cap parallel with PC136 to

15 59 VCORE 7/19 MAXIN fine tuning VCORE transient Add PC401 33nF/16V/X7R/0402(SE076333K8L)

16 59 VCORE 7/19 MAXIN Fine tuning VGFX Load Line Change PR157 to 8.2k(SD00000418L) from 8.66k(SD03486618L)

Add 33nF cap parallel with PC208 to fine

A
17 60 VGFX 7/19 MAXIN tuning VGFX transient Add PC402 33nF/16V/X7R/0402(SE076333K8L) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATICS,MB A6561
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 401931
Date: Thursday, January 13, 2011 Sheet 75 of 77
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Change PU11 pin1 net name to ICREF from GNDA_CHG
Reserve adapter protection circuit Change PU11 pin26 net name to ICOUT from VCC
D 18 61 Charger 7/21 Compal for turbo mode X01 D
Reserve PR511,PR512,PR513,PR514,PC406,PQ59,PR515,PR516.PR517,PC407
PC244,PC245,PR518,PR519,PR520.PQ43,PC405,PR509,PR510

PQ27 body diode can handle surge current

19 61 Charger 7/21 Compal when adapter plug in so depop PD14 Depop PD14 SBR3A40SA (SC100003J00) X01

Change PR126 & PR127 to 165K from 150K

20 59 VCORE 7/23 MAXIN For Pass2 VCORE & VGFX OCP setup X01
Change PR134 & PR135 to 105K from 100K

Change PR118 to 1 ohm from 2 ohm

21 59/60 VCORE/VGFX 7/23 MAXIN Setting change for ICC version change X01
Change PR119 to 1 ohm from 2 ohm

Pop PR513 100k (SD03410038L)

Pop PR514 78.7k (SD03478728L)
Pop PR512 115k (SD03411538L)
Pop adapter protection componment for
22 61 Charger 7/28 TI turbo mode with TI solution Pop PR511 1.87M ()
Pop PQ59 RHU002N06 (SB50206008L)
C
Pop PR510 100K (SD02810038L) C

Pop PC406 100P (SE071101J8L)

23 57 +1.05VM 10/18 TI Fine tune OCP setting Change PR83 to 22k (SD03422028L) from 10k (SD03410028L)

24 Change PQ39 and PQ44 SI4835DDY-T1-GE3 (SB00000FF1L) from SI4835DDY-T1-E3

63 Selector 10/18 Compal Change parts to HF parts (SB00000FF0L)

Fine tune adapter protection circuit to

25 61 charger 10/18 Compal reserve H_PROCHOT# Depop PR814

26 57 +1.05VM 10/18 Compal 22u/1206/6.3V COS issue Change PC98 ~ PC105 to 22u/0805 (SE00000110L) from 22u/1206 (SE077226M8L)

Change PC123 ~ PC125, PC121, PC127, PC120, PC129 and PC130 to 22u/0805
27 58 +1.05VTT 10/18 Compal 22u/1206/6.3V COS issue (SE00000110L) from 22u/1206 (SE077226M8L)
Change PC122 and PC126 to 47u/0805 (SE00000G60L) from 22u/1206 (SE077226M8L)
B B

28 53 DCIN 10/18 Compal 6 ~ 7mA leakage current in slice Change PR2 and PR504 to 100K (SD02810038L) from 10K (SD03410028L)

Depop PR337 and PR345 0 Ohm (SD02800008L)

Fix output voltage to 0.9V for nVidia
ES sample Depop PR347 10K (SD02810028L)
29 64 GPU_Core 10/18 nVidia
Pop PR343 10K (SD02810028L)

30 64 GPU_Core 10/18 Compal Change OCP setting for new nVidia chip Change PR332 and PR339 to 5.9k (SD03459018L) from 4.22k (SD03442218L)

Fine tune VCCSA OCP setting for 2nd and

31 62 VCCSA 10/18 Compal 3rd source choke Change PR247 and PR262 to 12.7k (SD03412728L) from 11.5k (SD03411528L)

Depop PR347 10K (SD02810028L)

Pop PR343 10K (SD02810028L)
Change VID setting for new nVidia chip. Change PR344 and PR400 to 3.09k (SD00000J38L) from 3.57k (SD03435718L)
32 64 GPU_Core 11/11 nVidia Defult set 1V. Change PR341 to 412k (SD00000678L) from 402k (SD034402380)
Change PR403 to 38.3k (SD03438328L) from 200k (SD03420038L)
A
Change PR338 to 71.5k (SD03471528L) from 0 Ohm (SD02800008L) A

Change PR334 to 30.1k () from 23.7k (SD03423728L)

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
SCHEMATICS,MB A6561
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401931
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, January 13, 2011 Sheet 76 of 77

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.

Fine tune main and media battery switching

33 63 Selector 11/11 Compal to slice battery transient time Change PC270 and PC265 to 0.22uF (SE000005Z8L) from 1uF (SE00000698L)
D D

Change PR512 to 107k (SD03410738L) from 115K (SD03411538L)

Change adapter protection circuit
34 61 Charger 11/11 Compal trip point. (Adapter rated current + 0.75A) Change PR511 to 649K (SD03464938L) from 1.87M (SD00000WN0L)
Change PR514 to 80.6K (SD03480628L) from 78.7k (SD03478728L)

Pop PR522 0 Ohm (SD02800008L)

Change adapter protection event
35 61 Charger 11/11 Compal to HW from SW Depop PR521 0 Ohm (SD02800008L)
Depop PR510 100k Ohm (SD02810038L)

Fine tune the GFX initial voltage to solve

36 60 VGFX_core 12/08 Compal offset Change PR119 to 0 ohm (SD01300008L) from 1 ohm (SD014100B8L)

37 59 VCORE 12/08 Compal Fine tuning VCORE Load Line Change PR140 to 12.4k(SD00000AJ8L) from 11.8k(SD03411828L)

C
H_PROCHOT# can not pull high issue with Change PR513.1 net nam to +3.3V_ALW2 from MAX8731_REF C

38 61 Charger 12/10 Compal external circuit at DC mode Change PQ59.3, PR514.2 and PC406.2 net nam to PGND from GAND_CHG

Depop PR511 (SD03464938L)

Change PR512 to 174k (SD03417438L) from 107k (SD03410738L)
Change PR513 to 150k (SD03415038L) from 100k (SD03410038L)
Change PR514 to 113k (SD03411338L) from 80.6K (SD03480628L)
H_PROCHOT# pull low level can not meet
39 61 Charger 12/10 Compal Intel SPEC with TI solution at AC mode Pop PR515, PR517,PR520 0 Ohm (SD02800008L)
Pop PQ43 RHU002N06 (SB50206008L)
Pop PR519 221K (SD00000HX8L)
Pop PR518 1.8M (SD00000K180)
Pop PR516 20K (SD03420028L)
Depop PR509 (SD02800008L)

40 59 VCORE 12/10 Compal Fine tune the GFX Load Line Change PR157 to 8.06K ohm (SD03480618L) from 8.2K ohm (SD00000418L)

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
SCHEMATICS,MB A6561
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401931
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, January 13, 2011 Sheet 77 of 77

5 4 3 2 1