Advanced Encryption Standard (AES)

256 bit key Encryption model IP

Design Document
 INDEX
Chapter 1

 Module Description
 Features

Chapter 2

 Module Interface
 Block Diagram
 Signal Description

Chapter 3

 RTL Design and Implementation

Chapter 4

 File Archive
Chapter 1
Module Description
The Advanced Encryption Standard (AES) specifies a cryptographic algorithm that
can be used to protect electronic data. The AES-128 pipelined cipher module uses
AES algorithm which is a symmetric block cipher to encrypt information.
Encryption converts data to an unintelligible form called cipher text .Here the AES
algorithm is capable of using cryptographic keys of 256 bit to do this conversion.
This module is optimized for speed as it pipeline hardware to perform repeated
sequence called round. It is design using system Verilog HDL.

Features
1. Supports 128 bit block size (input data).
2. Supports 256 bit Cipher Key.
3. Supports one Clock domain.
4. Design is optimized for speed.
5. Supports pipelined architecture.
6. Generic RTL for AES 256 bit encryption.

Frequency
 Max Frequency: 639.391Mhz
 Constrain Frequency : 200 Mhz
Chapter 2
Module Interface
module Top_Cipher
#(
parameter DATA_W = 128, //data width
parameter KEY_L = 256 //key length
parameter NO_ROUNDS = 14 //no of rounds
)
(
input clk, //system clock
input reset, //async reset
input data_valid_in, //data valid bit
input cipherkey_valid_in, //key valid bit
input [KEY_L-1:0] cipher_key, //cipher key
input [DATA_W-1:0] plain_text, //plain text
output valid_out,
output [DATA_W-1:0] cipher_text //cipher text
);
Block Diagram

Signal Description

Sr. Signal Name Input/Output Description Size(bit)

No
1 Clock Input System clock 1

2 Reset Input Asynchronous reset 1

3 cipher_key Input cipher key 256

4 cipherkey_valid_in Input cipher key valid signal 1

5 data_valid_in Input data valid signal 1

6 data_in Input payload data from IPv6 packet 128

7 cipher_data Output Encrypted data output 128

8 data_valid_out Output output valid signal 1

Chapter 3
RTL Design and Implementation

Fig.AES 256 bit key encryption model

All modules are controlled using one clock, asynchronous reset, inputs valid
signal, outputs valid signal

 Substitute Bytes:
Uses SBox LUT to substitute every byte in the 128 bit data

 Shift Rows:
This module is used to arrange data in the state array and shifting rows of
this array.
 Mix Columns:
This Module is used to perform Mix Columns calculations (finite field
multiplication).

 Add Round Key:

This module is used for xoring data and round key
 Round:
This module is used to connect SubBytes-ShiftRows-MixColumns- Add
Round Key modules

 Round Key Gen:

This module is used to perform the process of round key generation from
input key . This module is the basic block of key expantion module
The key generation stages should be balanced with the 4 round stages
(SuBytes-ShiftRows-MixColumns- AddRoundKey)in order to let the round
key and the data meet at the Add Round Key module
Round key generation includes RotWord(for rotation), SubBytes, Xor
operations.
 Key Expansion:
The key Expansion Module is used to generate round key from cipher key
using Pipelined architecture
Instantiate number Round key Gen modules= number of rounds to get
number of round keys = number of rounds
 Top Pipelined Cipher:
The top module of the design which forms rounds and connects Key
Expansion using pipelined architecture
Instantiate Key Expansion which will feed every round with round key due
to algorithm, first cipher key will be xored with plain text
Instantiate all rounds, connect them with key expansion this is the final
round it doesn't contain mix columns.
As the final round has only three stages a delay register should be introduced
to be balanced with key expansion
Chapter 4
File archive
 AES_Encryption
o Rtl
 Top_PipelinedCipher.v
 KeyExpantion.v
 RoundKeyGen.v
 Round.v
 SubBytes.v
 SBox.v
 ShifRows.v
 MixColumns.v
 AddRoundKey.v

 Sim
 Syn
 reports
 doc
o aes_encrypt_datasheet
o design_plan