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Microelectronics Processing - Transistor Fabrication

Technical Report · January 2016

DOI: 10.13140/RG.2.1.2540.6488

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Microelectronics Processing
LAB Report
ECE 574, FALL 2015

Venkata Kishore Kajuluri

ECE 574 | December 4, 2015
Abstract

Today, MOSFETs are widely used for implementing digital design due to the high
integration density and relatively simple manufacturing associated with their
fabrication process. This report goes through four steps employed to fabricate a
CMOS transistor during Lab sessions for ECE 574. Each step is distinctly brought
to discuss with presenting corresponding pictures and results. The report is
wrapped up with presenting the electrical characterization results of the device
and drawing a conclusion.

PAGE 1
Contents
1. Introduction ......................................................................................................................... 3
2. Introduction to fabrication process ..................................................................................... 5
2.1. Preparation and spin coat
................................................................................................. 5
2.2. Soft Bake
............................................................................................................................. 5
2.3. Photolithography and Developing
................................................................................... 5
2.4. Hard bake
........................................................................................................................... 6
2.5. Etching
................................................................................................................................ 6
2.6. Thermal Oxidation
............................................................................................................. 6
3. MOSFET Fabrication .......................................................................................................... 7
3.1. Mask 1: N Diffusion
.......................................................................................................... 7
3.2. Mask 2: Gate Oxide
........................................................................................................ 10
3.3. Mask 3: Contact Opening
.............................................................................................. 13
3.4. Mask 4: Metal Etch
......................................................................................................... 15
4. Device Characterization .................................................................................................... 17
References ................................................................................................................... 19

PAGE 2
 1. Introduction
The basic principle of this kind of transistor was first patented by Julius Edgar Lilienfeld in
1925.[1] Twenty five years later, when Bell Telephone attempted to patent the junction transistor,
they found Lilienfeld already holding a patent, worded in a way that would include all types of
transistors. Bell Labs was able to work out an agreement with Lilienfeld, who was still alive at
that time (it is not known if they paid him money or not). It was at that time the Bell Labs version
was given the name bipolar junction transistor, or simply junction transistor, and Lilienfeld's
design took the name field effect transistor.

In 1959, Dawon Kahng and Martin M. (John) Atalla at Bell Labs invented the metal–oxide–
semiconductor field-effect transistor (MOSFET) as an offshoot to the patented FET design.[2]
Operationally and structurally different from the bipolar junction transistor,[3] the MOSFET was
made by putting an insulating layer on the surface of the semiconductor and then placing a
metallic gate electrode on that. It used crystalline silicon for the semiconductor and a thermally
oxidized layer of silicon dioxide for the insulator. The silicon MOSFET did not generate localized
electron traps at the interface between the silicon and its native oxide layer, and thus was
inherently free from the trapping and scattering of carriers that had impeded the performance of
earlier field-effect transistors. Following the development of clean rooms to reduce contamination
to levels never before thought necessary, and of photolithography[4] and the planar process to
allow circuits to be made in very few steps, the Si–SiO2 system possessed such technical
attractions as low cost of production (on a per circuit basis) and ease of integration. Largely
because of these two factors, the MOSFET has become the most widely used type of transistor in
integrated circuits.

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS

FET) is a type of transistor used for amplifying or switching electronic signals. Although
the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B)
terminals,[5] the body (or substrate) of the MOSFET is often connected to the source
terminal, making it a three-terminal device like other field-effect transistors (Fig. 1).
Because these two terminals are normally connected to each other (short-circuited)
internally, only three terminals appear in electrical diagrams. The MOSFET is by far the
most common transistor in both digital and analog circuits, though the bipolar junction
transistor was at one time much more common

PAGE 3
Fig. 1: MOSFET showing gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the
body by an insulating layer (white)

Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably
IBM and Intel, recently started using a chemical compound of silicon and germanium (SiGe) in
MOSFET channels. Unfortunately, many semiconductors with better electrical properties than
silicon, such as gallium arsenide, do not form good semiconductor-to-insulator interfaces, and
thus are not suitable for MOSFETs. Research continues on creating insulators with acceptable
electrical characteristics on other semiconductor material. The gate is separated from the channel
by a thin insulating layer, traditionally of silicon dioxide and later of silicon oxynitride. Some
companies have started to introduce a high-κ dielectric + metal gate combination in the 45
nanometer node. When a voltage is applied between the gate and body terminals, the electric field
generated penetrates through the oxide and creates an "inversion layer" or "channel" at the
semiconductor-insulator interface. The inversion channel is of the same type, p-type or n-type, as
the source and drain, and thus it provides a channel through which current can pass. Varying the
voltage between the gate and body modulates the conductivity of this layer and thereby controls
the current flow between drain and source. This is known as enhancement mode.

The traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer

of silicon dioxide (SiO2) on top of a silicon substrate and depositing a layer of metal or
polycrystalline silicon (the latter is commonly used). As the silicon dioxide is a dielectric material,
its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a
semiconductor. When a voltage is applied across a MOS structure, it modifies the distribution of
charges in the semiconductor. If we consider a p-type semiconductor (with the density of
acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage, , from gate to
body (see figure) creates a depletion layer by forcing the positively charged holes away from the
gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile,
negatively charged acceptor ions (see doping (semiconductor)). If is high enough, a high
concentration of negative charge carriers forms in an inversion layer located in a thin layer next

PAGE 4
to the interface between the semiconductor and the insulator. Unlike the MOSFET, where the
inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS
capacitor they are produced much more slowly by thermal generation through carrier generation
and recombination centers in the depletion region. Conventionally, the gate voltage at which the
volume density of electrons in the inversion layer is the same as the volume density of holes in
the body is called the threshold voltage. When the voltage between transistor gate and source
(VGS) exceeds the threshold voltage (Vth), it is known as overdrive voltage.

The MOSFET is used in digital complementary metal–oxide–semiconductor (CMOS) logic,

which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in
integrated circuits since ever more transistors are packed into ever smaller chips. CMOS logic
reduces power consumption because no current flows (ideally), and thus no power is consumed,
except when the inputs to logic gates are being switched. CMOS accomplishes this current
reduction by complementing every n-MOSFET with a p-MOSFET and connecting both gates and
both drains together. A high voltage on the gates will cause the n-MOSFET to conduct and the p-
MOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching
time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This
arrangement greatly reduces power consumption and heat generation.

Here we review step by step procedures of MOSFET fabrication, including the experimental
results and characterization of the device. A silicon <100> wafer with 1μm thermally grown wet
oxide is used as initial substrate for device fabrication. This Lab activity was performed at the
microelectronic processing laboratory at MTTC cleanroom during Fall 2015 semester.

2. Introduction to fabrication process

2. 1. Preparation and spin coat

Usually processing procedure starts with preparation of wafer. It could be pre-cleaning to
remove any contamination or preparing wafer for Photoresist (PR) coating. For cleaning,
depending on what kind of contamination existed on the wafer we usually use either Acetone or
HF. Then, wafer is sent for HMDS coating which is applied to the wafer to assist adhesion of PR
on Si/SiO2 substrate. To coat HMDS we used HMDS bake oven and afterward sample was sent
to spin coater.

After setting the CEE spin coater for the appropriate program (5000 rpm 30 sec), the wafer
has been centered on the chuck. Then, AZ15 18 photoresist was dispensed onto the wafer. The

PAGE 5
resist film thickness attained by spin coating represents the equilibration between centrifugal
force and solvent evaporation, both increasing with spin speed. Before starting spinning, wafer
was centralized on the chuck to achieve precise resist thickness.

2. 2. Soft Bake
After spin coat, to remove PR solvent, wafer is baked for 90s under 120oC using a hot
plate. Then wafer is ready for photolithography step.

2. 3. Photolithography and Developing

Once we coated the photoresist on the wafers, they must be exposed using the appropriate
level mask. Optical lithography typically uses ultraviolet light. Karl Suss is the tool for this
process in MTTC cleanroom. Level masks 1, 2, 3 and 4 were used for the Diffusion, Gate Oxide,
Contact Opening and Metal Etch , respectively . Before the wafer can be exposed the wafer must
be aligned with the mask. There are aligners in each mask that help to properly align the mask on
the wafer. The markings must be aligned so that the gate, vias, and contacts are positioned
properly. Once the wafer is aligned correctly with the mask it is exposed with the UV light passing
through the openings in the photo-mask. The polymer molecules in the exposed regions of the
photoresist are altered by the absorption of the UV Photons. The photoresist is then altered which
makes it more soluble in the developing solution.

Then wafers were moved to appropriate developer solution to remove exposed part of PR and
disclosing mask pattern on the wafers. MIF300 is used to developing PR in this experiment and
all wafers are soaking on the solution for about 2 mins. Right after developing, wafers are washed
5-times to make sure all solution and exposed PR are removed from the wafers. Spin Rinse Dryer
was employed to dry wafers after developing and washing process.

2. 4. Hard bake
The hard bake increases the physical and chemical stability of the remaining photoresist, to
prepare it for a more durable protecting layer in future ion implantation, wet chemical etching, or
plasma etching. All wafers were bake for 120s under 120oC.

2. 5. Etching
Wet etching is used in microfabrication to chemically remove layers from the surface of the
wafer during manufacturing. Etching is a critically important process module, and every wafer
undergoes many etching steps before it being completed. Materials that are not protected by the
masks are etched away by liquid chemicals. These masks are deposited and patterned on the

PAGE 6
wafers in a prior fabrication step using lithography. This process is totally isotropic. The proper
recipe for MOSFET manufacturing was already found during Lab sessions.

Dry etching, plasmas or etchant gasses remove the substrate material. The reaction that takes
place can be done utilizing high kinetic energy of particle beams, chemical reaction or a
combination of both. Dry etch is not subject of this work.

Here in this work, 6 : 1 Buffered Oxide Etch (BOE) has been utilized as etchant in different
time scales for various processing steps as wet etch material.

2. 6. Thermal Oxidation
In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon
dioxide) on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the
wafer at high temperature and react with it. The rate of oxide growth is often predicted by the
Deal-Grove model.

Thermal oxidation of silicon is usually performed at a temperature between 800 and 1200°C,
resulting in so called High Temperature Oxide layer (HTO). It may use either water vapor (usually
UHP steam) or molecular oxygen as the oxidant; it is consequently called either wet or dry
oxidation. The reaction is one of the following:

Si + 2HO SiO2 + 2H2 (wet oxidation)

Si + O2 SiO2 (dry oxidation)

The oxidizing ambient may also contain several percent of hydrochloric acid (HCl). The
chlorine removes metal ions that may occur in the oxide.
Thermal oxide incorporates silicon consumed from the substrate and oxygen supplied from
the ambient. Thus, it grows both down into the wafer and up out of it. For every unit thickness of
silicon consumed, 2.17 unit thicknesses of oxide will appear. Conversely, if a bare silicon surface
is oxidized, 44% of the oxide thickness will lie below the original surface, and 56% above it.

The thickness of oxide layer can be calculated using:

Where , is the oxide thickness, τ is the correction factor, and B and B/A are parabolic and
linear constants, respectively. Using the above equation for the p-type Silicon at temperature of

PAGE 7
1000oC and the average thickness of 1 μm, the calculated value of the time taken is 4:27 hours.
The wafers were oxidized over night for the purpose of this work.

3. MOSFET Fabrication Process

3.1 Mask 1: N Diffusion:

In this part, wafers are prepared for solid deposition of POCl3. We do all the processes
describe above from cleaning and preparation (HMDS and Spin coating) to spin rinse
dryer and then wafers were inspected to check patterning quality.

(a) (b) (c)

Figure 2. Schematic after N-diffusion for (a) 50𝜇𝑚 (b) 20 𝜇𝑚 (c) 100 𝜇𝑚

Figure. 3 illustrates a schematic of whole process need to be done for N-diffusion. For the
same initially we place the wafers on the hot plate for hard baking where it is baked at
120℃ for 2 min. It is only then that the wafers can be sent for oxide etching which involves
the wafers to be placed in a solution of BOE 6:1 bath for 14 min. Later they were shifted to
the QDR and cleansed for 5 cycles and then thrown into the spin dry. At this stage there
is a requirement of inspection which can be done using Nikon's microscope again.

Then the wafers were placed in a solution of H2SO4=H2O2 twice for 5 min each the
difference being the temperature of both the solutions. This is done to lift any leftover
photoresist off the wafer. Later it is transferred into the QDR and then thrown into the
spin drier. After the wafers are dried they are sent for final inspection. This is the end of
Mask 1 procedure and wafers are ready to send for N Diffusion. Figure 2 shows the
schematic with Source and Drain after mask 1 obtained while inspection at the end of the
process.

PAGE 8
Figure 3. Schematic of sample processing and preparation for N-Diffusion (mask 1). (a)
Initial wader with 1μm oxide layer, (b) Exposure after coating PR, (c) Appearance of the
pattern after developing. (d) Diffusion of dopant on the wafer

Having the solid solubility of Phosphorous about Cs = 5×1018 cm-3 and the concentration
of Boron doped substrate about CB = 1015 cm-3, the total phosphorus atoms diffused into
the substrate in this step can be calculated as follow:

PAGE 9
3.2 Mask 2: Gate Oxide:

We start with putting the wafers in the HMDS Oven. Like the previous experiment the
process remains the same for the HMDS, CEE Coater, Wafer Exposure and Wafer
Developing. The mask for this step is for etching the gate width oxide away from the
region. After all this is done, as usual the wafers are shifted to the QDR and spin dried.
Later the wafers are inspected and then sent for Hard Baking at 120℃ for about 2 min.
Figure 4 shows a schematic of the whole processes have been done during mask-2 session.

PAGE 10
Figure 4 Schematic for Gate Oxide Mask 2

The next step requires the wafers to be placed in BOE 6:1 bath for 14 min. After this process
is finished we have to place the wafers into the QDR and spin drier. The wafer is again
inspected to find minor defects.

Figure 5. Schematic for gate oxide by inspection after mask2

PAGE 11
The wafers are then placed in a solution of H2SO4=H2O2 twice for 5 min each the
difference being the temperature of both the solutions. This is done to remove any leftover
photo resist off the wafer. The next step is placing the wafers in QDR and spin drier. After
the wafers were dried, they were sent for a final inspect and the required measurements
are noted down.

Now, the sample is ready for the second step of diffusion, which is called Drive-in process.
This process requires energy (heat) to activate the impurities and diffuse them further into
the substrate. We accomplish this aim together with growing Gate Oxide. To do so, wafers
were taken to grow the Gate Oxide (GOX). 100 nm of gate oxide (GOX) was grown in the
gate region at 1100o C for 50 minutes.

In order to determine the doping profile as a function of depth after a drive-in step of 50
minutes at 1100o C, we implement following calculation:

Table 2 lists concentration of the dopant (using diffusion equation) at different distances
from the surface. To calculate these values we used Drive-In equation.

PAGE 12
Having A, B and τ for dry oxidation at 1100 o C, by applying thermal oxidation equation
presented in introduction section we can calculated the thickness of oxide layer after 50
min:

3.3 Mask 3: Contact Opening:

In mask 3 process, the GOX is etched to add contacts to source and drain pads in the next
step. Similar to the last stages, after photoresist coating, each wafer was soft baked in the
hot plate at 115℃ for about 90 seconds followed by a cool down on the metallic bench.
Subsequently, each wafer was exposed in a vacuum contact environment inside the Karl
Suss contact aligner (using Actuator, Exp. 20 s). The mask number 3 was patterned into
each of the wafers after 10 seconds of exposure to make the contacts for the transistors.
Figure 6 illustrates the process GOX etching for adding contacts.

PAGE 13
Figure 6. Schematic for Metal Contacts mask 3

When the exposure was completed the wafers were developed for 2 minutes by the MIF300
developer. Then the wafers were rinsed for 5 cycles in the QDR followed by one spin drier
cycle to remove all the water remaining. After drying wafers, Nikon microscope was used
to inspect the wafers.

(a)
Figure 7. Schematic from inspection after mask 3

Then, wafer were placed into Teflon cassette followed by a 4 minutes BOE 6:1 bath to etch
the contacts of the transistors. After the wafers were etched, the chemicals were removed
using a 5 cycle QDR. Later, wafers were placed in the spin drier. After the metrology
process was completed, wafers were placed into a H2SO4=H2O2 bath for 5 minutes
immediately followed by another H2SO4=H2O2 bath for 5 minutes more. Then, the wafers

PAGE 14
were transferred into a Teflon cassette for a 5 cycle QDR followed by drying out in the spin
drier. After this process all the photoresist was removed from the wafers. Finally, the
wafers were inspected and pictures were taken once again using the microscope from
Nikon as shown in Figure 7. After inspection, the wafers were deposited with aluminium
using vacuum evaporator deposition tool. The metal layer is deposited all over the wafer.

3.4 Mask 4: Metal Etch:

Up to this stage, the metal layer was patterned to define S, G, and D contacts to the
MOSFET. The fourth mask was used in the same way as before. Metal patterned to form
source, gate and drain contacts. After developing the wafers, cleaning and drying followed
by inspection, they were placed in a Teflon cassette for aluminium etch bath for about 20
minutes (It takes different times for etching the Al from the wafer, depending on the
placement of the wafers in the vacuum evaporator tool). Later, the cassette was placed
into the dump rinser for a 5 cycle QDR followed by a spin drier cycle.

Figure 8. Schematic for metal etching mask 4

Inspection was performed using the Nikon's microscope and then the remaining
photoresist was removed by using the AZ 300T photoresist stripper. Afterwards, the
cassette was placed for 5 cycle QDR cleaning followed by a spin dry.

PAGE 15
Figure 9. Final transistor structure after mask 4

Figure. 9 depicts final structure of device after patterning metal contacts on the wafer.
After final inspection, wafers were sent to the probe stage for electrical characterization.

The final structure of the Si wafer after the entire fabrication process is as shown in Figure
10.

PAGE 16
Figure 10. Si wafer after the fabrication process.

PAGE 17
 4. Device Characteristics
Device functions and properties were tested on fabricated wafer. The output
characterization curves (IDS vs. VDS for different VG Voltages) for different gate lengths
have been shown in Figure 13.

(a) Channel length 50um

PAGE 18
(b) Channel length 100um

PAGE 19
(c) Channel length 20um

Figure 11. Ids Vs Vds Characteristics for (a) 50𝜇𝑚 (b) 100 𝜇𝑚 (c) 20 𝜇𝑚

In order to extraction of threshold voltage, we connected gate and drain together

and plotted IV Curves for them. In fact, we have IDS vs. VG in this step, which is a diode
characteristic. As we know, in this configuration, the MOSFET has been forced to be in
saturation region. Therefore, the following relationship governs over the current and
voltage:

𝜇𝑛 𝐶𝑜𝑥 𝑊
𝐼𝐷𝑆 = ( 𝑉𝐺𝑆 − 𝑉𝑇 )2
2 𝐿
Where W is the channel width, Cox is Capacitance due to gate oxide and μn is electron
mobility in the channel region. To calculated threshold voltage, we took the square root
of the data (IDS) to reach the above mentioned formula. So, the intercept of the tangent
line with the horizontal axis gives the threshold voltage. Calculated values for different
gate length devices are listed in the table below.

PAGE 20
 Length (in 𝝁𝒎) Threshold Voltage Breakdown Voltage Mode of
Vt (in V) Vb(in V) Operation
20 -1.5 93 Depletion
50 -1 97 Depletion
100 -0.5 90 Depletion

To extract Breakdown Voltage (VBD), we look at the end of I-V curves. As high-lighted in
the attached plots (obtained from .csv file with the document), we can define a Breakdown
region, rather considering single point. Taking an average value of Breakdown Voltages
(VBD) at different VG, we will come up with the results as tabulated below.

Conclusion:

Based on the result, we come up with the conclusion that all devices (with gate length of
20, 50, 100 μm) are in the depletion mode. The transistor characteristics plot clearly shows
the operation in Cutoff, Linear, Saturation and Breakdown regions of a typical Depletion
mode MOSFET.

PAGE 21

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