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OPA627, OPA637
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015
Output
6
+In –In
3 2
–VS
4
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA627, OPA637
SBOS165A – SEPTEMBER 2000 – REVISED OCTOBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.5 Device Functional Modes........................................ 19
2 Applications ........................................................... 1 8 Application and Implementation ........................ 20
3 Description ............................................................. 1 8.1 Application Information............................................ 20
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 22
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 24
6 Specifications......................................................... 3 10 Layout................................................................... 24
6.1 Absolute Maximum Ratings ...................................... 3 10.1 Layout Guidelines ................................................. 24
6.2 ESD Ratings ............................................................ 4 10.2 Layout Example .................................................... 25
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 26
6.4 Thermal Information .................................................. 4 11.1 Device Support .................................................... 26
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ....................................... 26
6.6 Typical Characteristics .............................................. 7 11.3 Related Links ........................................................ 26
7 Detailed Description ............................................ 12 11.4 Trademarks ........................................................... 26
7.1 Overview ................................................................. 12 11.5 Electrostatic Discharge Caution ............................ 27
7.2 Functional Block Diagram ....................................... 12 11.6 Glossary ................................................................ 27
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
7.4 Settling Time ........................................................... 19 Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Removed Lead Temperature from Absolute Maximum Ratings table. ................................................................................. 3
P and D Packages
8-Pin PDIP and SOIC LMC Package
Top View 8-Pin TO-99
Top View
No Internal Connection
Offset Trim 1 8 No Internal Connection
3 5
+In 4 Offset Trim
–VS
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 Offset Trim — Input offset voltage trim (leave floating if not used)
2 –In I Inverting input
3 +In I Noninverting input
4 –VS — Negative (lowest) power supply
5 Offset Trim — Input offset voltage trim (leave floating if not used)
6 Output O Output
7 +VS — Positive (highest) power supply
8 NC — No internal connection (can be left floating)
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage ±18 V
Input Voltage Range +VS + 2 –VS – 2 V
Differential Input Total VS + 4 V
Power Dissipation 1000 mW
LMC Package –55 125
Operating Temperature °C
P, D Package –40 125
LMC Package 175
Junction Temperature °C
P, D Package 150
LMC Package –65 150
Storage temperature, Tstg °C
P, D Package –40 125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
1k 100
p-p
Noise Bandwidth:
Voltage Noise (nV/ √ Hz)
10
0.1
RMS
1 0.01
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Bandwidth (Hz)
Figure 1. Input Voltage Noise Spectral Density vs Frequency Figure 2. Total Input Voltage Noise vs Bandwidth
1k 140
–
120
+
Voltage Noise (nV/ √ Hz)
100 OPA637
Voltage Gain (dB)
RS
100
80
60
Comparison with
OPA627 + Resistor
OPA27 Bipolar Op 40
10 OPA627
Amp + Resistor
20
Spot Noise
Resistor Noise Only at 10kHz 0
1 –20
100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M
Source Resistance ( Ω) Frequency (Hz)
20 –120 20 –120
Phase (Degrees)
Phase (Degrees)
Gain (dB)
Gain (dB)
Phase Phase
75° Phase
Margin Gain
10 –150 10 –150
Gain
0 –180 0 –180
80
60
115
40
110
20
105 0
–75 –50 –25 0 25 50 75 100 125 2 20 200 2k 20k 200k 2M 20M
Temperature (°C) Frequency (Hz)
60 100
40
90
20
0 80
1 10 100 1k 10k 100k 1M 10M –15 –10 –5 0 5 10 15
Frequency (Hz) Common-Mode Voltage (V)
Figure 9. Common-Mode Rejection vs Frequency Figure 10. Common-Mode Rejection vs Input Common-Mode
Voltage
140 125
120
Power-Supply Rejection (dB)
PSR
120
CMR and PSR (dB)
100
–VS PSRR 627
80 and 637
CMR
115
60
+VS PSRR 627
40 637 110
20
0 105
1 10 100 1k 10k 100k 1M 10M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)
Figure 11. Power-Supply Rejection vs Frequency Figure 12. Power-Supply Rejection and Common-Mode
Rejection vs Temperature
+IL at VO = 0V
80
7.5
Supply Current (mA)
6 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
Figure 13. Supply Current vs Temperature Figure 14. Output Current Limit vs Temperature
24 60 120 160
Slew Rate
Gain-Bandwidth (MHz)
Gain-Bandwidth (MHz)
20 100 140
Slew Rate
16 55 80 120
GBW
GBW
12 60 100
8 50 40 80
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
Figure 15. OPA627 Gain-Bandwidth and Slew Rate vs Figure 16. OPA637 Gain-Bandwidth and Slew Rate vs
Temperature Temperature
0.1 G = +1 G = +10 1
G = +10 G = +50
VI + VO = ±10V VI + VO = ±10V
VI + VO = ±10V VI + VO = ±10V
– 600 Ω – 600Ω
100pF 5kΩ 100pF – 600Ω – 600Ω
0.01 0.1 5k Ω 100pF 5k Ω 100pF
549 Ω
549Ω 102 Ω
THD+N (%)
THD+N (%)
0.0001 0.001
G = +1
G = +10
0.00001 0.0001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)
Figure 17. OPA627 Total Harmonic Distortion + Noise vs Figure 18. OPA637 Total Harmonic Distortion + Noise vs
Frequency Frequency
TO-99
100
IB
10 Plastic
10 IOS DIP, SOIC
5
1
Figure 19. Input Bias and Offset Current vs Junction Figure 20. Input Bias Current vs Power Supply Voltage
Temperature
1.2 50
Beyond Linear
Offset Voltage Change (µV)
Input Bias Current Multiplier
Common-Mode Range
1.1 25
1 0
0.9 –25
Beyond Linear
Common-Mode Range
0.8 –50
–15 –10 –5 0 5 10 15 0 1 2 3 4 5 6
Common-Mode Voltage (V) Time From Power Turn-On (Min)
Figure 21. Input Bias Current vs Common-Mode Voltage Figure 22. Input Offset Voltage Warm-up vs Time
30 100
Output Voltage (Vp-p)
20 10
OPA627
OPA637
10 1 OPA637
OPA627
0 0.1
100k 1M 10M 100M –1 –10 –100 –1000
Frequency (Hz) Closed-Loop Gain (V/V)
Figure 23. Maximum Output Voltage vs Frequency Figure 24. Settling Time vs Closed-Loop Gain
OPA627 OPA627
500 1 G = –1
G = –1
OPA637
G = –4
0 0
0.001 0.01 0.1 1 10 0 150 200 300 400 500
Error Band (%) Load Capacitance (pF)
Figure 25. Settling Time vs Error Band Figure 26. Settling Time vs Load Capacitance
7 Detailed Description
7.1 Overview
The OPA6x7 Difet operational amplifiers provide a new level of performance in a precision FET operational
amplifier. When compared to the popular OPA111 operational amplifier, the OPA6x7 has lower noise, lower
offset voltage, and higher speed. The OPA6x7 is useful in a broad range of precision and high speed analog
circuitry.
The OPA6x7 is fabricated on a high-speed, dielectrically-isolated complementary NPN/PNP process. It operates
over a wide range of power supply voltage of ±4.5 V to ±18 V. Laser-trimmed Difet input circuitry provides high
accuracy and low-noise performance comparable with the best bipolar-input operational amplifiers.
High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not
possible with previous precision FET operational amplifiers. The OPA627 is unity-gain stable. The OPA637 is
stable in gains equal to or greater than five.
Difet fabrication achieves extremely low input bias currents without compromising input voltage noise
performance. Low input bias current is maintained over a wide input common-mode voltage range with unique
cascode circuitry.
The OPA6x7 is available in plastic PDIP, SOIC, and metal TO-99 packages. Industrial and military temperature
range models are available.
7
Trim +VS
Trim
1 5
Output
6
+In –In
3 2
–VS
4
RF < 4RI
OPA627 OPA627
– –
+ Buffer +
Non-Inverting Amp
RI G<5
RF < 4R
OPA627 RI
– – OPA627
+ +
Bandwidth Inverting Amp
Limiting G < |–4|
OPA627 OPA627
– –
+ +
Integrator Filter
Figure 27. Circuits With Noise Gain Less Than Five Require the OPA627 for Proper Stability
C2
C1 R2
–
+
OPA637
R1 C1 = CIN + CSTRAY
R1 C1
C2 =
R2
Figure 28. Circuits With Noise Gain Equal to or Greater Than Five May Use the OPA637
+VS
100kΩ
7 10kΩ to 1MΩ
1 Potentiometer
2 (100kΩ preferred)
– 5
3 6
+
OPA627/637
4
±10mV Typical
Trim Range
–VS
Non-inverting Buffer
2 2
– –
6 6
Out Out
3 In 3
In + +
OPA627 OPA627
OPA627 3 4
2
– 5
6
Out
3
+ 2 6
Board Layout for Input Guarding:
Guard top and bottom of board. 7
Alternate—use Teflon ® standoff for sen- 1
sitive input pins. 8 No Internal Connection
B.
5kΩ
(2)
HP 5082-2811
RF
VI – –VS
RI VO
+
OPA627 Clamps output
at VO = ±11.5V
200pF
CF G = +1
RO BW ≥ 1MHz
– 20Ω
+ CL
RF OPA627 5nF
G = 1+ R1
R1
+VS
–
D VO
+ OPA627
D
D: IN4148 — 25nA Leakage
Optional RS
2N4117A — 1pA Leakage
–VS Siliconix
=
(a)
IIN
–
VO
D D + OPA627
D: 2N3904
=
(b)
NC
140
PRF = -10 dbm
120 VS = r15 V
VCM = 0 V
100
60
40
20
0
10M 100M 1G 10G
Frequency (MHz)
Table 1 shows the EMIRR IN+ values for the OPA627 at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
+VS
±
50 Low-Pass Filter
+
RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling
OPA627 OPA637
CF
RI , R 1 2kΩ 500Ω
HP- CF 6pF 4pF
5082- 2kΩ Error Band ±0.5mV ±0.2mV
2835 (0.01%)
+15V
RI
High Quality –
±5V NOTE: CF is selected for best settling time performance
Pulse Generator
depending on test fixture layout. Once optimum value is
51Ω Out
+ determined, a fixed capacitor may be used.
–15V
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
+In + 1
OPA637
Differential Voltage Gain = 1 + 2R F /RG
Gain = 1000
OPA637 CMRR » 116dB
–In +
Bandwidth » 400kHz
– RF
5kΩ 10kΩ 100kΩ 5
2
Input Common-Mode
Range = ±10V INA106
RG
3pF Differential
101Ω – Output
Amplifier 6
3
+
RF 10kΩ
– 5kΩ 100kΩ
+In + 1
OPA637
(A) (B)
FPO
When used as a unity-gain buffer, large common-mode input voltage steps – G=1
produce transient variations in input-stage currents. This causes the rising
edge to be slower and falling edges to be faster than nominal slew rates +
observed in higher-gain circuits. OPA627
+10 +10
VOUT (V)
VOUT (V)
0 (C) 0 (D)
–10 –10
6pF(1)
NOTE: (1) Optimum value will
When driven with a very fast input step (left), common-mode
depend on circuit board lay-
transients cause a slight variation in input stage currents which
out and stray capacitance at
will reduce output slew rate. If the input step slew rate is reduced
the inverting input. 2kΩ
(right), output slew rate will increase slightly.
– G = –1
2kΩ
+ VOUT
OPA627
OPA637 OPA637
LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE
+10 +100
VOUT (mV)
VOUT (V)
0 (E) 0 (F)
FPO
–10 –100
4pF(1)
2kΩ
– G=5
+ VOUT
OPA637
500Ω
NOTE: (1) Optimum value will depend on circuit
board layout and capacitance at inverting input.
R4 C5
2.94 k 1 nF
±
R1 R3 Output
590 499 +
Input OPA627
C2
39 nF
0
Gain (db)
-20
-40
-60
100 1k 10k 100k 1M
Frequency (Hz)
Figure 44. OPA627 2nd Order 25 kHz, Chebyshev, Low Pass Filter
10 Layout
VIN +
RG VOUT
RF
(Schematic Representation)
Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF
Offset trim NC
RG
GND ±IN V+ GND
Non-inverting Buffer
2 2
– –
6 6
Out Out
3 In 3
In + +
OPA627 OPA627
OPA627 3 4
2
– 5
6
Out
3
+ 2 6
Board Layout for Input Guarding:
Guard top and bottom of board. 7
Alternate—use Teflon ® standoff for sen- 1
sitive input pins. 8 No Internal Connection
B.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.4 Trademarks
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Difet is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
26 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 19-Apr-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA627AM NRND TO-99 LMC 8 20 Green (RoHS AU N / A for Pkg Type OPA627AM
& no Sb/Br)
OPA627AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627AP
OPA627SM NRND TO-99 LMC 8 20 Green (RoHS AU N / A for Pkg Type OPA627SM
& no Sb/Br)
OPA637AM NRND TO-99 LMC 8 20 Green (RoHS AU N / A for Pkg Type OPA637AM
& no Sb/Br)
OPA637AM2 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA637AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637AP
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 19-Apr-2015
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA637SM NRND TO-99 LMC 8 20 Green (RoHS AU N / A for Pkg Type OPA637SM
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 19-Apr-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Apr-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Apr-2015
Pack Materials-Page 2
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