Shri Ramdeobaba College of Engineering and Management, Nagpur

Department of Electronics Engineering

Session 2019-20 CMOS VLSI Design (ENT402) Shift I and II
Teacher Assessment 2
Assignment No. 05

1. a. Do the following two circuits implement the same logic function? If yes, what is that logic
function? If no, give Boolean expressions for both circuits.

b. Will these two circuits’ output resistances always be equal to each other?

c. Will these two circuits’ rise and fall times always be equal to each other? Why or why not?

2. Consider the domino circuit in Fig.1. Assuming that all inputs of the circuit shown in Fig.1 are
initially Low (0V) during the pre-charge phase and that all internal nodes are at 0V. Ignore all
other parasitic capacitance except C1, C2, and C3. It is given that VDD=2.5V, V tn0=0.5V,
2|φF|=0.6V and γ=0.4V0.5
 Figure 1

(a) Calculate the voltage drop on Vout (OUT node voltage) if A changes to High (2.5V) during the
evaluation phase. (Hint: Don’t forget the body effect.)

(b) Calculate the voltage drop on VOUT (OUT node voltage) if both A and B change to High
(VDD=2.5V) (5pts).

(c) What is the maximum number of transistors that can be connected in series to M1 and M2
(including M1 and M2, excluding M3) if the output should not fall below 0.9V during the
evaluation phase? Assume that each one of the new transistors has the same intrinsic
capacitance (to ground) as M1 and M2 (C=5fF).

3. (a) As shown in Fig. 2, what's the function of the PTL (Pass Transistor Logic) circuit?

(b) What's the purpose of the PMOS?

(c) Given Vdd = 2.5 V, and equivalent resistance Rn(W = 1) = Rp(W = 2) = 10 kΩ, what's the static
power consumption of the gate ? (Assume the inputs are from similar PTL gates with inverters
as output buffers).

(d) If the buffer inverters have the high noise margin of 0.625 V, what's the maximum size of
the PMOS?
 Figure 2

4. Derive Boolean equations for the four outputs of the cells shown in figure 3. Is it possible to
obtain a 4 bit adder by interconnecting various cells in figure 4 ? Why or why not? Justify.

Figure 3

5. The two logic functions are given by F = A + B + C and G = A + B + C + D. Assume both true and
complementary signals are available: (i) Implement these functions in dynamic CMOS as
cascaded stages so as to minimize the total transistor count. (ii) Design an np – CMOS
implementation of the same logic functions.