VLSI PROJECT LIST (VHDL/Verilog)

S.No. PROJECT TITLES IEEE

A New VLSI Architecture of Parallel Multiplier–Accumulator
1 2010
Based on Radix-2 Modified Booth Algorithm. (Verilog)
An Efficient Architecture for 3-D Discrete Wavelet Transform.
2 2010
(Verilog)
The Design of FIR Filter Base on Improved DA Algorithm and its
3 2010
FPGA Implementation. (Verilog)
4 Design of On-Chip Bus with OCP Interface. (Verilog) 2010
Design of a Self-Motivated Arbitration Scheme for the Multilayer
5 2010
AHB Busmatrix. (Verilog)
Low Complexity and Fast Computation for Recursive MDCT and
6 2010
IMDCT Algorithms
An Efficient Architecture for 2-D Lifting-based Discrete Wavelet
7 2009
Transform. (Verilog)
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-
8 2009
Wooley Multipliers
A Spurious-Power Suppression Technique for Multimedia/DSP
9 2009
Applications(Verilog)
Design of AES (Advanced Encryption Standard) Encryption and
10 2009
Decryption Algorithm with 128-bits Key Length (VHDL)
DDR3 based lookup circuit for high-performance network
11 2009
processing. (Verilog)
12 Multiplication Acceleration Through Twin Precision 2009
13 32-bit RISC CPU Based on MIPS (VHDL) 2009
14 High Speed Hardware Implementation of 1D DCT/IDCT (Verilog) 2009
15 Efficient FPGA implementation of convolution 2009
High Speed VLSI Architecture for General Linear Feedback Shift
16 2009
Register (LFSR) Structures
Implementation of a visible Watermarking in a secure still digital
17 2009
Camera using VLSI design
18 Implementation of FFT/IFFT Blocks for OFDM 2009
Design and Implementation of Efficient Systolic Array Architecture
19 2008
for DWT (Discrete Wavelet Transform) (Verilog)
Design and Implementation of 10/100 Mbps (Mega bits per
20 2008
second) Ethernet Switch for Network applications (Verilog)
Design and Implementation of USB 2.0 Transceiver Macro-cell
21 2008
Interface (UTMI) (VHDL)
2nd floor, Solitaire plaza, Beside Image Hospital, Ameerpet, HYD-73, Ph. No: +91 40 44433434,
9885112363.www.kresttechnology.com , e-mail : Krestinfo@gmail.com.
 A Versatile Multimedia Functional Unit Design Using the Spurious
22 2007
Power Suppression Technique (Verilog)
Design and Implementation of Digital low power base band
23 2007
processor for RFID Tags (Verilog)
Design and Implementation of Reversible Watermarking for
24 2007
JPEG2000 Standard
FPGA Implementation of 3D Discrete Wavelet Transform for Real-
25 2007
Time Medical Imaging
Design and Implementation of High Speed DDR SDRAM (Dual
26 2006
Data Rate Synchronously Dynamic RAM) Controller (VHDL)
Design and Implementation of Lossless DWT/IDWT for Medical
27 2006
Images
High Performance Complex Number Multiplier Using Booth-
28 2006
Wallace Algorithm
High Speed Parallel CRC Implementation Based On Unfolding,
29 2006
Pipelining and Retiming
30 Design of an Bus Bridge between OCP and AHB Protocol (VHDL) VHDL
Design of Gigabit Ethernet MAC (Medium Access Control)
31 VHDL
Transmitter
Design of an AMBA-Advanced High performance Bus (AHB)
32 VHDL
Protocol IP Block
33 Design of Data Encryption Standard (DES) Verilog

34 Design of Distributed Arithmetic FIR Filter Verilog

35 Design of Universal Asynchronous Receiver Transmitter (UART) VHDL

36 Design of Triple Data Encryption Standard (DES) Verilog

Design of 16 Point Radix-4 FFT (Fast Fourier Transform)
37 Verilog
Algorithm
38 Design of Dual Elevator Controller Verilog

39 Design of an ATM (Automated Teller Machine) Controller Verilog

40 Design of 8-Bit Pico Processor VHDL

41 Design of JPEG Image compression standard Verilog

42 Design of Digital FM Receiver using PLL (Phase Locked Loop) VHDL

43 Design of 16-bit QPSK (Quadrature Phase Shift Keying) Verilog

44 Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator Verilog

Design of AES (Advanced Encryption Standard) Encryption

45 VHDL
Algorithm with 128-bits Key Length
2nd floor, Solitaire plaza, Beside Image Hospital, Ameerpet, HYD-73, Ph. No: +91 40 44433434,
9885112363.www.kresttechnology.com , e-mail : Krestinfo@gmail.com.
46 Design of RS-232 System Controller Verilog

47 Design of Floating-Point Multiplier using IEEE-754 Standard Verilog

48 Design of CRC (Cyclic Redundancy Check) Generator verilog

49 Design and Implementation of OFDM Transmitter VHDL

50 Design of 8-bit Microcontroller VHDL

2nd floor, Solitaire plaza, Beside Image Hospital, Ameerpet, HYD-73, Ph. No: +91 40 44433434,
9885112363.www.kresttechnology.com , e-mail : Krestinfo@gmail.com.