List of Questions for EC1404 VLSI lab

1. Design a half-adder and full-subtractor in dataflow model and also simulate the
same using Xilinx-ISE simulator.
2. Design a half-subtractor and full-adder in dataflow model and also simulate the
same using Xilinx-ISE simulator.
3. Design a half-adder and full-subtractor in structural model and also simulate the
same using Xilinx-ISE simulator.
4. Design a half-subtractor and full-adder in structural model and also simulate the
same using Xilinx-ISE simulator.
5. Implement an 8:1 MUX in structural model and also simulate the same using
Xilinx-ISE simulator.
6. Implement an 8:1 MUX in behavioral model and also simulate the same using
Xilinx-ISE simulator.
7. Implement an 8:1 MUX using 2:1 MUX and 4:1 MUX and also simulate the same
using Xilinx-ISE simulator. Using conditional operator implement 2:1 MUX and
4:1 MUX.
8. Implement an 8:1 MUX using 2:1 MUX and 4:1 MUX and also simulate the same
using Xilinx-ISE simulator. Using case statement implement 2:1 MUX and 4:1
MUX.
9. Implement an 8:1 MUX using 2:1 MUX and 4:1 MUX and also simulate the same
using Xilinx-ISE simulator. Using if-else statement implement 2:1 MUX and 4:1
MUX.
10. Design a sum of full-adder using 3 to 8 decoder and carry using simple logic
circuit and also simulate the same using Xilinx-ISE simulator.
11. Design a difference of full-subtractor using 3 to 8 decoder and borrow using
simple logic circuit and also simulate the same using Xilinx-ISE simulator.
12. Implement 4:1 MUX and 1:4 DEMUX using conditional statement.
13. Implement a 4:1 MUX using 2:1 MUX (conditional operator) and also simulate
the same using Xilinx-ISE simulator.
14. Implement a 4:1 MUX using 2:1 MUX (case statement) and also simulate the
same using Xilinx-ISE simulator.
15. Write a verilog program to convert a given BCD number to seven segment
display in common cathode mode in behavioral model and also simulate the same
using Xilinx-ISE simulator.
16. Write a verilog program to convert a given BCD number to seven segment
display in common anode mode in behavioral model and also simulate the same
using Xilinx-ISE simulator.
17. Write a verilog program to convert a given weighted-code to cyclic code and also
simulate the same using Xilinx.
18. Write a verilog program to convert a given cyclic code to weighted-code and also
simulate the same using Xilinx.
19. Write a verilog program to convert a given unit-distance code to weighted-code
and also simulate the same using Xilinx.
20. Write a verilog program to convert a given weighted-code to self-complementing
code and also simulate the same using Xilinx.
21. Write a verilog program to convert a given self-complementing code to weighted-
code and also simulate the same using Xilinx.
22. Write a verilog program to implement a Full adder using Half adder in dataflow
model and also simulate the same using Xilinx-ISE simulator.
23. Write a verilog program to implement a 5-bit Parallel adder using Full adder (in
structural model) and also simulate the same using Xilinx-ISE simulator.
24. Write a verilog program to design a 4-bit magnitude comparator using 2-bit
magnitude comparator in behavioral model and also simulate the same using
Xilinx-ISE simulator.
25. Write a verilog program to design a 4-bit magnitude comparator using 2-bit
magnitude comparator in dataflow model and also simulate the same using
Xilinx-ISE simulator.
26. Write a verilog program to design a 3 to 8 decoder using 2 to 4 decoder with
active low enable signal in behavioral model and also simulate the same using
Xilinx-ISE simulator.
27. Write a verilog program to design a full adder using 3 to 8 decoder and also
simulate the same using Xilinx-ISE simulator.
28. Write a verilog program to design a full subtractor using 3 to 8 decoder and also
simulate the same using Xilinx-ISE simulator.
29. Write a verilog program to design a full adder using 1:8 DEMUX and also
simulate the same using Xilinx-ISE simulator.
30. Write a verilog program to design a full subtractor using 1:8 DEMUX and also
simulate the same using Xilinx-ISE simulator.
31. Write a verilog program to design a 16-bit Ripple carry adder and also simulate
the same using Xilinx-ISE simulator.
32. Write a verilog program to design an 8:3 encoder in structural model and also
simulate the same using Xilinx-ISE simulator.
33. Design and simulate an asynchronous counter using JK Flip Flop with active low
CLEAR signal (behavioral model) using Xilinx-ISE simulator.
34. Design and simulate an asynchronous counter using T Flip Flop with active high
CLEAR signal (behavioral model) using Xilinx-ISE simulator.
35. Design and simulate synchronous counter using T Flip Flop with active high
CLEAR signal (behavioral model) using Xilinx-ISE simulator.
36. Design and simulate synchronous counter using JK Flip Flop with active low
CLEAR signal (behavioral model) using Xilinx-ISE simulator.
37. Write a verilog program to convert JK flip flop into SR, T and D flip flop and also
simulate the same using Xilinx-ISE simulator.
38. Design a parallel-in-parallel-out shift register and also simulate the same using
Xilinx-ISE simulator.
39. Design a serial-in-serial-out shift register and also simulate the same using Xilinx-
ISE simulator.
40. Design a serial-in-parallel-out shift register and also simulate the same using
Xilinx-ISE simulator.
41. Design a parallel-in-serial-out shift register and also simulate the same using
Xilinx-ISE simulator.
42. Write a verilog program to convert SR flip flop into JK, T and D flip flop and also
simulate the same using Xilinx-ISE simulator.
43. Write a verilog program to convert T flip flop into SR, JK and D flip flop and also
simulate the same using Xilinx-ISE simulator.
44. Write a verilog program to convert D flip flop into SR, T and JK flip flop and also
simulate the same using Xilinx-ISE simulator.
45. Write a verilog program to implement a Full subtractor using Half subtractor in
structural model and also simulate the same using Xilinx-ISE simulator.
46. Write a verilog program to implement a real time clock.
47. Write a verilog program to implement a traffic light controller such that the signal
changes with every 20sec.
48. Write a verilog program to implement a traffic light controller such that the signal
changes with every 30sec.
49. Write a verilog program to implement a parallel adder. Add 8 nos. of 12 bit each.
50. Write a verilog program to implement a multiplier. Multiply 2 nos. of 8 bit each.