DIGITAL LOGIC

SEQUENTIAL CIRCUITS

Solutions
1. How many bits can be saved in a Flip-flop?

(a) 0 (b) 1

(c) 2 (d) None of these

Sol: Option (b)

2. Which clock triggering is best when there is external disturbance, while using flip-flops?

(a) level (b) edge

(c) both (d) none

Sol: Option (b)

Explanation:

Edge triggering is used because the transparency mode will be active for very less time period.

So, the time period to change the state of the flip-flop will be very less, which is the desired
behavior for noisy (disturbance) environment.

3. Which flip flop produces invalid output for some input

(a) JK flip flop (b) T flip flop

(c) D flip flop (d) SR flip flop

Sol: Option (d)

Explanation:

SR flip flop produces invalid output when an input (1, 1) is provided.

1
4. What is the triggering method used for the clock of the given flip flop?

(a) +ve level (b) –ve level

(c) +ve edge (d) –ve edge

Sol: Option (c)

5. Which of the following circuit is not identical with others?

Sol: Option (d)

Explanation:

All these are edge triggered.

They are transparent when option:

a) Q’: 0 → 1 = 𝑄: 1 → 0

b) 𝑄: 1 → 0 Same

c) Q’: 0 → 1 = 𝑄: 1 → 0

d) 𝑄: 0 → 1 → 𝑛𝑜𝑡𝑖𝑑𝑒𝑛𝑡𝑖𝑐𝑎𝑙

2
 Common Data Questions: 6 & 7
The following is the AB flip flop:

6. What are values of A, B when change in the flip flop state from 0 to 1?

(a) 1, 𝜙 (b) 0, 𝜙

(c)1,0 (d) 𝜙, 1

Sol: Option (b)

7) What are the values of A, B to put the flip flop in latch mode

(a) 1,1 (b) 1, 𝜙

(c) 1,0 (d) 𝜙, 1

Sol: Option (c)

Explanation:

Standard method:
Characteristic equation =>𝑄𝑛 = 𝐴′ 𝑄′ + 𝐵′ 𝑄

Explanation for Q.6:

Excitation Table:

3
Simple methods:

Flip flop state 0 → 1 = 𝑄 = 0, 𝑄𝑛 = 1

𝑄𝑛 = 𝐴′ 𝑄 ′ + 𝐵′ 𝑄
1 = 𝐴′ 0′ + 𝐵′ 0 = 𝐴′ = 𝐴 = 0

Now,
1 = 0′ 0′ + 𝐵 ′ 0 = 1 = 1

So, A should be „0‟, irrespective of B value, the equation satisfies.

So, B is φ

𝑄𝑛 = 𝐴′ 𝑄 ′ + 𝐵′ 𝑄
0,0 ⇒ 𝑄𝑛 = 0′ 𝑄 ′ + 0′ 𝑄 = 1
0,1 ⇒ 𝑄𝑛 = 0′ 𝑄 ′ + 1′ 𝑄 = 𝑄 ′

1,0 ⇒ 𝑄𝑛 = 1′ 𝑄 ′ + 0′ 𝑄 = 𝑄=>𝑄𝑛 = 𝑄

1,1 ⇒ 𝑄𝑛 = 1′ 𝑄 ′ + 1′ 𝑄 = 0
i.e. Find inputs for which Qn and Q are same.
That is the input which puts flip flop in latch mode.

Explanation for Q7:

Characteristic Table:

4
Function Table:

Common Data Questions: 8 & 9

Given the following XY flip flop, answer the given questions:

8. What values of X, Y put flip flop in SET mode?

(a) 0, 0 (b) 0, ϕ

(c) ϕ, 1 (d) 1, 0

Sol: Option (d)

9. What are the values of X, Y to change the state of flip flop from 1 to 0?

(a) 0, 0 (b) 0, ϕ

(c) ϕ, 1 (d) 1, 0

Sol: Option (b)

Explanation for Q.8:

Character equation =>𝑄𝑛 = 𝑋𝑄 + 𝑌 ′ 𝑄′

5
So, X, Y = (1, 0)

Explantion For Q.9

𝑄 → 𝑄𝑛
1→0
𝑄𝑛 = 𝑋𝑄 + 𝑌 ′ 𝑄 ′
0 = 𝑋 1 + 𝑌 ′ 1′
0=𝑋+0=𝑋 =0

X should be „0‟
Y can be 0 or 1, does not matter.

So, Y is don‟t care.

(X, Y) = (0, φ)

10. Which one of the given state transitions is not possible for the given flip-flop?

(a) 0 → 0 (b) 0 → 1

(c) 1→ 0 (d) 1 → 1

Sol: Option (d)

6
Explanation:

𝑄𝑛 = 𝐴𝑄 ′ + 𝐵𝑄 ′

𝑇ℎ𝑒𝑟𝑒𝑖𝑠𝑛𝑜1 → 1

Another Method:

𝑄𝑛 = 𝐴𝑄 ′ + 𝐵𝑄 ′ = 𝐴 + 𝐵 𝑄 ′

If 1 → 1
1 = 𝐴 + 𝐵 1′
 1= 𝐴+𝐵 0
 1 = 0, but 1 ≠ 0
 1 = 0is impossible.

So, the equation does not support 𝑄, 𝑄𝑛 = 1,1

So, therefore no 1 → 1

Substitute other options too, they satisfy the equation.

7
11. Which of the following is asynchronous?

Sol: Option (d)

Explanation:

 Synchronous counters have same clock.

 Asynchronous counters will have output of one flip-flip as clock for another flip-flop.

8
12. Which of the following is synchronous?

Sol: Option (b)

Explanation:

 Synchronous counters have same clock.

 Asynchronous counters will have output of one flip-flop as clock for another flip-flop.

13. Which of the following state transitions is possible with the given counter?

9
(a) 1 → 3 (b) 3→ 2

(c) 0 → 2 (d) 0 → 3

Sol: Option (c)

Explanation:

𝐷0 = 𝑄1 , 𝐷1 = 𝑄0′

Common Data Questions: 14 & 15

14. If the given counter is mod x counter, then what is x?

(a) 2 (b) 6

(c) both (a) & (b) (d) none

Sol: Option (c)

10
Explanation:

𝐷0 = 𝑄2
𝐷1 = 𝑄0
𝐷2 = 𝑄1′

15. If the counter starts at 010, after how many cycles it reaches 111?

(a) 5 (b) 3

(c) 4 (d) 6

Sol: Option (c)

11
Explanation:

“4 cycles”

16. What mod counter is in the given circuit?

(a) mod 1 (b) mod 4

(c) mod 5 (d) mod 7

Sol: Option (a)

Explanation:

𝑄2𝑁 = 𝐷2 = 𝑄1 + 𝑄2
𝑄1𝑁 = 𝐷1 = 𝑄0
𝑄0𝑁 = 𝐷0 = 𝑄2

12
17. Which of the following are self starting?

(a) II only (b) II and III

(c) I and III (d) III only

Sol: Option (b)

Explanation:

Self starting counter is a counter where irrespective of initial state, the counter enters into
counting loop.

By definition: II and III hold the specified property.

13
18. What is the behavior of the given counter?

(a) up counter (b) down counter

(c) random counter (d) none

Sol: Option (b)

Explanation:

𝑄0𝑁 = 𝑄0′ ; 𝑓𝑜𝑟𝑒𝑣𝑒𝑟𝑦𝑐𝑙𝑜𝑐𝑘(Only when positive edge is there)

𝑄1𝑁 = 𝑄1′ ; 𝑄0 : 0 → 1

It is a down counter.

14
 Common Data Questions: 19 & 20
Given 4 bit shift register:

19. How many clock cycles required to input 4 bits of data?

(a) 0 (b) 1

(c) 3 (d) 4

Sol: Option (d)

20. How many clock cycles required to get the output?

(a) 0 (b) 1

(c) 3 (d) 4

Sol: Option (c)

Explanation:

In a shift register with „n‟ bits

clock cycles to enter input = n cycles
clock cycles to get output = n - 1 cycles

15