Static Timing Analysis

Static Timing Analysis (STA)

A design is an interconnected set of cells and nets

The functionality of a design is determined by the RTL design sources

— The functionality can be verified by a simulation tool

The performance of a device is determined by the delays of the cells

that comprise the design
— This is verified by static timing analysis

In STA the functionality of the components of the design are not

1
-
3
important
— Only the performance of the components matter
— Cells need only be classified as combinatorial or sequential

Setup and Hold Timing Analysis - 1-3 © Copyright 2016 Xilinx 108343

113133**slide
 Static Timing Paths
A static timing path is a path that Clocked elements include
— Starts at a clocked element flip-flops, block RAMs, DSP cells,
— Propagates through any number of among others
combinatorial elements and the
nets that interconnect them Combinatorial elements include
— Ends at a clocked element LUTs, wide MUXes, carry chains,
among others

1
-
4

Setup and Hold Timing Analysis - 1-4 © Copyright 2016 Xilinx 108343
 Setup Check
Checks that a change in a clocked element has time to propagate to
other clocked elements before the next clock event
— That is, from the rising edge of the clock to the next rising edge of the clock
— Checked for all static timing paths

1
-
5

Setup and Hold Timing Analysis - 1-5 © Copyright 2016 Xilinx 108343

113135**slide
 Setup Checks and Clock Networks
When a clock object is attached to a port/pin/net, the clock propagates
forward to all clocked elements

A timing check includes the propagation of the clock from the point
attached
— To the startpoint of the static timing path (Source Clock Delay)
— To the endpoint of the static timing path (Destination Clock Delay)

1
-
6

Setup and Hold Timing Analysis - 1-6 © Copyright 2016 Xilinx 108343
 Launch and Capture Edge for Setup Checks
A setup check
— Starts at the launch edge of the clock driving the startpoint
— Ends at the capture edge of the clock driving the endpoint

For a path that starts and ends on the same clock

— The launch edge is the first rising edge of the clock
— The capture edge is the second rising edge of the clock
— The timing relationship between these edges is the same as the timing
relationship between any consecutive edges

1
-
For a path that starts and ends on different clocks, different pairs of
edges will result in different requirements on the static timing path
7

— The timing engine chooses the pair of edges with the tightest requirement

Setup and Hold Timing Analysis - 1-7 © Copyright 2016 Xilinx 108343
 Static Timing Paths and I/O
1-
4

57432**slid e

Static timing paths start at clocked elements and end at clocked

elements
— Paths from internal flip-flop to internal flip-flop are constrained by clocks

Inputs and outputs of the FPGA are not startpoints/endpoints of static

timing paths
— By default, any logic between a primary I/O and an internal clocked element are not
part of a complete static timing path
— Without additional commands, no setup/hold checks are done on logic associated with
I/O

Inputs and Outputs - 1-7 © Copyright 2015 Xilinx 57428

 Synchronous Input Interfaces
1-
6

57434**slid e

Most interfaces to an FPGA use synchronous communication

— FPGA and the device driving the FPGA have some shared timing reference
 This is usually a common clock or a related clock

Complete static timing path through an input

— Starts at a clocked element in the driving device
 Referenced to a clock provided to the driving device
— Ends at a clocked element in the FPGA
 Referenced to the clock that propagates to the destination clocked element in the
FPGA
— Propagates through the elements between them
 CLK  Q of the external device
 Board propagation time
 Port of the FPGA
 Combinatorial elements in the FPGA before the destination clocked element

Inputs and Outputs - 1-8 © Copyright 2015 Xilinx 57428

 Completing the Static Timing Input Path
1-
7

57435**slid e

To complete the static timing path, you need to describe the

external elements to the Vivado static timing engine
— What clock is used by the external device?
— Delay between the external device’s clock and the arrival at the input port of
the FPGA
 Includes the CLK  Q time of the external device and the board delay

Inputs and Outputs - 1-9 © Copyright 2015 Xilinx 57428

 Set Input Delay
The path is a register-to-register path, with the launch register being in
an external device. The external contribution to the delays need to be
specified using the set_input_delay command

The set_input_delay command supplies the information required

to complete the static timing path
— set_input_delay –clock <clock_name> <delay> <objects>
 <clock_name> is the name of the clock used by the external device
o Can be a real or virtual clock
o Can be the name of a clock; does not need to be a clock object
o Can use a clock object if desired
1
-
5
 <objects> is the list of objects to which to attach the set_input_delay
command
o Usually a set of input and/or inout ports
o Usually uses the get_ports command or the all_inputs command

 <delay> is the delay from <clock_name> to the attached <objects>

o Includes the external device and board delay

I/O Constraints and Virtual Clocks - 1-5 © Copyright 2016 Xilinx 108087
 Timing Waveform
create_clock –name SysClk –period 10 [get_ports ClkIn]
set_input_delay –clock SysClk 4 [get_ports DataIn]

1
-
6

I/O Constraints and Virtual Clocks - 1-6 © Copyright 2016 Xilinx 108087
 Using a Common Clock
A set_input_delay command can be related to an already existing
clock
— Can be the clock attached to the FPGA clock pin

The value used for the set_input_delay command is the sum of

— The clock to out of the external source
— The trace delay on the board

create_clock –name SysClk –period 10 [get_ports ClkIn]

set_input_delay –clock SysClk 4 [get_ports DataIn]
1
-
7

I/O Constraints and Virtual Clocks - 1-7 © Copyright 2016 Xilinx 108087
108092**slide
 Minimum and Maximum Delays
By default, each input port can have one maximum delay and one
minimum delay
— The maximum delay is used for the setup check
— The minimum delay is used for the hold check

Without the –max or –min option, the value supplied is used for both

create_clock –name SysClk –period 10 [get_ports ClkIn]

set_input_delay –clock SysClk 4 [get_ports DataIn]
set_input_delay –clock SysClk 2 -min [get_ports DataIn]
1
-
8

I/O Constraints and Virtual Clocks - 1-8 © Copyright 2016 Xilinx 108087
 Multiple Input Delays on the Same Port
An input can have multiple set_input_delay commands associated
with it
— Use the –add_delay option
— Results in multiple static timing paths to check

set_input_delay –clock ClkA 3 [get_ports DataIn]

set_input_delay –clock ClkB 4 [get_ports DataIn]
–add_delay

1
-
9

I/O Constraints and Virtual Clocks - 1-9 © Copyright 2016 Xilinx 108087
 Creating Input Delays Using the GUI
The Timing Constraint window can be opened by selecting Window >
Timing Constraints
— A clock can be created by double-clicking Set Input Delay or in a new row in
the Set Input Delay table

1
-
1
0

I/O Constraints and Virtual Clocks - 1-10 © Copyright 2016 Xilinx 108087
 Set Input Delay Wizard
A separate constraint is required for the maximum and minimum
— The wizard retains its options between invocations, making it easy to specify
the minimum after the maximum has been specified

1
-
1
1

I/O Constraints and Virtual Clocks - 1-11 © Copyright 2016 Xilinx 108087

108097**slide
 Output Timing Overview (1)

Setup and hold at the downstream device input pins are analyzed for
timing
1
-
1
2

Source and destination clocks need to be defined, from which the tool
derives the source and destination clock edges to consider
— create_clock (actual FPGA clock and virtual downstream device clock)
— System (common) clock or forwarded clock
— create_generated_clock for forwarded output clocks
I/O Constraints and Virtual Clocks - 1-12 © Copyright 2016 Xilinx 108087
113143**slide
 Output Timing Overview (2)

Downstream device setup and hold requirements need to be specified

— Downstream setup requirement: set_output_delay -max
1
-
1
3
— Downstream hold requirement: set_output_delay -min
— Board trace delay may be included if significant
— Referenced to the destination capture clock edge

I/O Constraints and Virtual Clocks - 1-13 © Copyright 2016 Xilinx 108087
 Completing the Static Timing Output Path
To complete the static timing path, you need to describe the external
elements to the Vivado Design Suite static timing engine
— What clock is used by the external device?
— Delay between the output port of the FPGA and the external device’s clock
 Includes the required time of the external device and the board delay

1
-
1
4

I/O Constraints and Virtual Clocks - 1-14 © Copyright 2016 Xilinx 108087
108099**slide
 Multiple Output Delays on the Same Port
An output can have multiple set_output_delay commands
associated with it
— Use the –add_delay option
— Results in multiple static timing paths to check

set_output_delay –clock ClkA 1 [get_ports DataOut]

set_output_delay –clock ClkB 2 [get_ports DataOut]
–add_delay

1
-
1
5

I/O Constraints and Virtual Clocks - 1-15 © Copyright 2016 Xilinx 108087

108101**slide
 Creating Output Delays Using the GUI
The Timing Constraint window can be opened by selecting Window >
Timing Constraints
— A clock can be created by double-clicking Set Output Delay or in a new row
in the Set Output Delay table

1
-
1
6

I/O Constraints and Virtual Clocks - 1-16 © Copyright 2016 Xilinx 108087
 Set Output Delay Wizard
A separate constraint is required for the maximum and minimum
— The wizard retains its options between invocations, making it easy to specify
the minimum after the maximum has been specified

1
-
1
7

I/O Constraints and Virtual Clocks - 1-17 © Copyright 2016 Xilinx 108087

108103**slide