IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO.

3, MARCH 2020 2317

Optimization of LCL Filter With Integrated Intercell

Transformer for Two-Interleaved High-Power
Grid-Tied Converters
Ki-Bum Park , Member, IEEE, Frederick D. Kieferndorf, Member, IEEE, Uwe Drofenik, Member, IEEE,
Sami Pettersson, Member, IEEE, and Francisco Canales, Member, IEEE

Abstract—Paralleling of voltage source converters (VSCs) with a

limited maximum output power is essential when the power rating
of a system must be increased. Interleaving (ILV) of the switching
signals for parallel-connected VSCs provides a better harmonic
spectrum than hard paralleling (HP), i.e., applying identical signals
to all VSCs. This can be particularly beneficial for grid-tied convert-
ers, since a smaller LCL filter can be realized. To investigate the per-
formance limitations and the impact of ILV operation on the LCL
filter hardware, a comprehensive optimization procedure for LCL
filters and intercell transformers (ICTs) for two paralleled VSCs is
presented in this paper. In addition, a comparative evaluation of HP
and ILV operation of VSCs is carried out. The developed optimiza- Fig. 1. Parallel-connection of high-power grid-tied converters. Two voltage
tion procedure and the hardware benefits of ILV operation were source converters share one LCL filter.
verified through testing on a 260-kW full-scale system. Compared
with the commercial state-of-the-art weight-optimized LCL filter
for HP, the developed LCL filter for ILV utilizing an integrated ICT
reduces the total filter weight by 30% while guaranteeing harmonic
standard compliance and meeting thermal requirements.
Index Terms—Intercell transformer (ICT), interleaving (ILV),
LCL filter, optimization, voltage source converter (VSC).

I. INTRODUCTION
OLTAGE source converters (VSCs) are widely used in
V grid-tied converters for applications ranging from photo-
voltaic and wind power installations to UPS systems and ac
drives. To suppress the harmonic currents and voltages caused
by pulsewidth modulation (PWM) of the VSCs, an LCL filter is
usually employed [1]–[5]. The LCL filter is typically the heaviest
and bulkiest component in the system and thus a major burden
in terms of transportation, installation, and cost. Therefore, the
reduction of weight and volume of the LCL filter is a major
concern.
The primary reason to connect VSCs in parallel is to in-
crease the power rating of a system beyond that imposed by
Fig. 2. Converter hardware configuration with common dc-link configuration
Manuscript received May 26, 2018; revised November 12, 2018, February 12, according to paralleling method. (a) Hard-paralleling. (b) Interleaving.
2019, and May 10, 2019; accepted June 16, 2019. Date of publication July 1,
2019; date of current version December 13, 2019. Recommended for publication
by Associate Editor M. GE Liserre. (Corresponding author: Ki-Bum Park.) the maximum limit of a single lower power rated VSC. For
The authors are with the Power Electronics Department, ABB Corporate Re-
search, Baden CH-5405, Switzerland (e-mail: ki-bum.park@ch.abb.com; fred- example, Fig. 1 shows a high-power grid-tied converter em-
erick.kieferndorf@ch.abb.com; uwe.drofenik@ch.abb.com; sami.pettersson@ ploying a hard-paralleling (HP) scheme, where pairs of VSCs
ch.abb.com; francisco.canales@ch.abb.com). are connected in parallel sharing an LCL filter and operating with
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. the same switching signals. Fig. 2(a) shows the circuit diagram
Digital Object Identifier 10.1109/TPEL.2019.2926312 of this HP arrangement with a common dc link. The ease of

0885-8993 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2318
Fig. 3. (a) N-interleaved VSCs with common LCL filter. (b) Single-phase representation. (c) Equivalent circuit in terms of longitudinal and transverse modes.
implementation, based on existing VSCs and LCL filters, pro-
vides simple modularity and scalability. In a practical system,
though, a small inductance La is typically required to minimize
the imbalance between the paralleled converter output currents,
which can be caused by small mismatches in the timing of
switching signals and differing switching characteristics of the
semiconductor devices.
Another paralleling method for the common dc-link config-
uration is interleaving (ILV) operation, which utilizes phase-
shifted PWM carriers between VSCs [6]–[12]. The ILV PWM
cancels certain harmonic components generated by the VSCs
toward the LCL filter. As a result of the improved output har-
monic spectrum, the filtering requirements can be significantly
reduced. On the other hand, the canceled harmonic components
appear as additional circulating currents between each pair of
paralleled phases of the VSCs. To suppress this circulating
current, an intercell transformer (ICT) is inserted between each
of the paralleled phases [13]–[20]. The circuit arrangement for
ILV VSCs is shown in Fig. 2(b). In order for ILV to provide a
benefit, the total weight and volume of the LCL filter with an
ICT for ILV must be smaller than the conventional LCL filter
for HP.
It is also possible to maintain separate dc links in the parallel-
connected VSCs [42], which reduces the circulating current
caused by ILV operation substantially. On the other hand, the
current ripple cancellation benefit of ILV in the common dc-link
configuration is lost [43]. In addition, when each converter has
its own dc link, design flexibility of the total system is reduced,
since the number of load-side and grid-side converter designs
must be matched. In contrast, the common dc-link configuration
provides good modularity since the load-side and grid-side
converters can be designed independently.
Hardware design of grid-tied converters is a multidomain/
multiobjective optimization problem incorporating harmonic
standards, PWM methods, filter structure, magnetic compo-
nents, and semiconductor power losses. The literature concern-
ing ILV operation is numerous, including advanced modulation
to minimize the ICT flux [13], [19], [22], integrated magnetics
to improve power density [18], [23], [25], an arbitrary number
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020
of paralleled converters [15], [24], etc. Yet, an optimization
methodology for high-power grid-tied converters, which sys-
tematically covers all the aspects mentioned above has not been
reported. A significant contribution of this paper is providing a
comprehensive hardware optimization methodology and exper-
imental verification for two-interleaved high power (260 kW)
VSCs with an LCL filter and an integrated ICT (IICT), which is
reported for the first time in the literature with this power rating.
In Section II, the impact of the ILV number (number of inter-
leaved converters) on the LCL filter is investigated. Section III
provides minimum-weight design guidelines for an IICT taking
current imbalance into account. Section IV presents a global
optimization of two-interleaved VSCs with an LCL filter and a
detailed local optimization of the IICT. In Section V, experimen-
tal verification of the designed 260-kW rated full-scale system
is given.
II. IMPACT OF NUMBER OF INTERLEAVED VSCS ON
LCL FILTER
A. N-Interleaved Converter Modeling—Longitudinal and
Transverse Modes
Fig. 3(a) presents a circuit configuration for N-ILV VSCs,
where N is the number of interleaved VSCs, or ILV number, and
one LCL filter is shared with the VSCs though one or more ICTs.
Fig. 3(b) shows a single-phase representation. For the sake of
analysis, the output voltages of the VSCs can be transformed into
longitudinal mode (LM) and transverse mode (TM) components
[14]. From (1), it can be seen that the LM voltage, vLM , is the
average voltage of the n converter outputs vc,n while the nth TM
voltage vTM,n is the difference between vc,n and vLM , or the
nth differential voltage. Fig. 3(c) shows the equivalent circuit
in terms of LM and TM. From the converter side, vLM is the
harmonic voltage source, which generates harmonics in the grid-
side current ig . Therefore, the attenuation required of the LCL
filter, Attreq , is determined by the vLM harmonics. The N vTM
sources, on the other hand, only affect the circulating currents
between the VSCs, which is confined to the area shown in grey
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS 2319

Fig. 4. Comparison of harmonic spectrum between (a) CPWM and (b) DPWM, normalized by the fundamental ac component. vc∗ represents the converter voltage
reference. Mi = 1.05. The results are obtained with a MATLAB script based numerical computation of the open-loop modulator behavior.

Fig. 5. Highest switching harmonic voltage Vh.sw,N of two-level VSC according to interleaving number and Mi, normalized by the fundamental ac component.
Vh.sw,N shown in Fig. 4 is indicated by the arrow.

in Fig. 3(c) interleaved converters, for example: Vh.sw,1 corresponds to HP

N operation and Vh.sw,2 for 2-ILV operation.
1 
vLM = vc,n
N n=1
vTM,n = vc,n − vLM .
B. Harmonic Voltage Spectrum
The two-level VSC is selected as the target topology. Space
vector modulation [26], called continuous PWM (CPWM) in
this paper, and 60° discontinuous PWM (DPWM) are the most
widely used PWM methods, with the choice depending on the
application [21], [27], [28]. CPWM provides a good harmonic
spectrum, whereas DPWM can reduce the switching losses.
Fig. 4 shows the harmonic spectrums of both CPWM and
DPWM, where sidebands of harmonics appear around every
multiple of the carrier frequency fca . The highest magnitude har-
monic voltage in each of the harmonic sidebands is designated
as Vh.sw,n , and occurs at a frequency fh.sw,n , where n = {1, 2,
3 …}. Regarding N-ILV operation, only the sideband harmonics
of the Nth harmonic group and above appear in vLM , whereas
those below are shifted to vTM . That is, the Nth harmonic voltage
Vh.sw,N can be related to the lowest critical harmonic for N
The differences in the voltage harmonic spectrums of CPWM
(1)
and DPWM have important implications for the performance
of paralleled converter systems. In the case of HP, Vh.sw,1 for
(2) DPWM is about 50% higher than that for CPWM. In the case of
2-ILV, on the other hand, Vh.sw,2 is slightly smaller for DPWM
than for CPWM. To determine the impact of the ILV number
and the dc-link voltage on Vh.sw,N , Fig. 5 shows the variation of
Vh.sw,N as a function of the modulation index (Mi) according to
N ( = 1,2,3,4). It is remarkable that Vh.sw,N of CPWM is always
smaller than that of DPWM with HP while with 2-ILV it is the
opposite. In other words, DPWM produces a better harmonic
spectrum compared to CPWM when 2-ILV operation is used.
As for 3- and 4-ILV operation, the relative amplitude of Vh.sw,N
between CPWM and DPWM also have different dependencies
on Mi. Since grid-tied converters are the focus of this paper,
Mi = 1 will be assumed. In this case, Vh.sw,N for DPWM is
more than 2 times higher than that for CPWM when 3-ILV
operation is used, whereas Vh.sw,N for DPWM is lower with
4-ILV operation.
In summary, DPWM is a promising candidate for 2- and 4-ILV
operation owing to its superior harmonic spectrum over CPWM.
2320 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020

Fig. 6. Impact of number of interleaving and modulation scheme on LCL parameters with fca = 3.45 kHz.

In addition, DPWM can be operated with a higher fca relative TABLE I

DESIGN SPECIFICATION AND PARAMETERS FOR N-INTERLEAVED VSCS
to CPWM for the same semiconductor losses (about doubled)
[2], which makes it even more beneficial.

C. Impact of ILV on LCL Filter Parameters

The LCL filter is designed to satisfy harmonic current stan-
dards, such as IEEE519 or BDEW [1], [2], [20]. The highest
harmonic current, Ih.sw,N , which is caused by Vh.sw,N , must
be smaller than the specified limit. According to the IEEE519
harmonic current standard [2], [29], when the short-circuit ratio
is lower than 20, 0.3% of the rated current is the strictest
limitation of Ih.sw,N for the harmonic numbers higher than
Lc + Lg , (on the y-axis) are shown. When HP or 3-ILV is used,
35 (>1.75 kHz). Since fca of typical grid-tied converters for
the overall LCL values for DPWM are higher compared with
low voltage applications (<1 kV) is higher than 2 kHz, 0.3%
those for CPWM. While, in the case of 2-ILV, both CPWM and
is selected as the target IEEE519 harmonic current limitation
∗ DPWM result in similar LCL values. On the other hand, the LCL
IEEE519 in this paper. The transfer function of an LCL filter (3) is
parameters for DPWM are smaller with 4-ILV. These results
shown for several different values of the filter resonant frequency
∗ are expected from the Vh,sw,N analysis shown in Fig. 5. It is
fres in Fig. 7. The required filter attenuation to satisfy IEEE519
remarkable that already for 2-ILV the total inductance required
can be defined as (4). Based on (3) and (4), once fres and the
is only about 30% of that required for HP, when the same value
converter-side inductor Lc are given, the grid-side inductor Lg
for Cf is used.
and filter capacitor Cf can be obtained from (5) and (6)
Fig. 7 shows the impact of fres on the LCL parameters, where
ig 1 kres = fres /fca . The “Design Nr” on the x-axis of the right-side
= ,
vLM Lc Lg Cf s (s2 + ωres 2 ) graph represents the different sets of LCL combinations for the
 same filter transfer function. As fres increases, the inductance
Lc + Lg values increase while the capacitance value decreases. It is noted
ωres = 2πfres = (3)
Lc Lg C f that range of reasonable kres values is different for HP and
2-ILV. When it comes to 2-ILV, as a consequence of the fca
IIEEE519 ∗ doubling effect, the range of fres , which provides reasonable
Attreq = (4)
Vh.sw,N LCL parameters is also approximately doubled. If fres is too low,
ωres 2 the filter capacitance becomes too large, which causes significant
Lg = − Lc , reactive currents. On the other hand, when fres is too high, the
ωh.sw,N (ωh.sw,N 2 − ωres 2 ) Attreq
filter inductance become too large that results in a bulky and
ωh.sw,N = 2πfh.sw,N (5) heavy inductor realization. For example, in the case of ILV, if
Lc + Lg kres is near 50% Cf will exceed 10% p.u. while most of the
Cf = . (6) reasonable LCL parameter sets for HP can be found when kres
Lc Lg ωres 2
is less than 40%.
Table I provides the design specifications used for the LCL Fig. 8 shows the ranges of LCL filter kres values according
parameter generation. Fig. 6 shows the impact of the ILV number to the ILV number, N-ILV, which provide LCL filter parameters
N and the type of PWM on the LCL parameters. Here, per below 15% p.u. As N-ILV increases, the overall fres increases,
unit (p.u.) values of Cf (on the x-axis) and total inductance, which results in lower filter requirements, but at the cost of a
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS 2321

Fig. 7. Impact of 2-ILV on filter resonant frequency with fca = 4.5 kHz. (a) HP DPWM. (b) 2-ILV DPWM. Left-side graphs show the filter transfer function
(G(s) = ig (s)/vLM (s)) variation and right-side graphs show the LCL parameter variation as a function of kres (= fres /fca ).

implement a high-power converter and thus, the most reasonable

approach is to take the first step from HP to ILV. For this reason,
the rest of the paper will focus on the detailed analysis for
2-ILV, including optimization of the integrated converter side
magnetics for operation at a nominal current of 380 Arms .

III. WEIGHT MINIMIZATION OF ICT FOR

Fig. 8. Impact of interleaving number on filter resonant frequency ratio kres
for both CPWM and DPWM, all points shown have LCL parameter values below
15% p.u.
more careful current controller design with a higher sampling
frequency [30]–[34].
TWO-INTERLEAVED VSCS
It is evident that the LCL filter values for ILV operation are
smaller than those for HP, if the ICTs are not taken into account.
In order to gain a total system benefit from ILV, though, the addi-
tional weight of the ICTs must be less than the weight reduction
of the LCL filter achieved by ILV operation. To maximize the
benefit of ILV operation, therefore, optimization of the ICT is a
critical consideration. In this Section, detailed design guidelines
considering current imbalance and weight optimization of the
ICT for the 2-ILV case are presented.

D. Impact of Carrier Frequency on LCL Parameters A. LCL Filter Structure for 2-ILV
Fig. 9(a) shows a range of LCL parameters for different values As shown in Fig. 1, the LCL filter for high-power grid-tied
of fca while Fig. 9(b) shows the same data as a Pareto front curve converters is typically constructed within its own mechanical
trading off total inductance versus capacitance. The impact of frame, where magnetic components occupy most of the space.
ILV on LCL parameters can also be roughly described with (7), As shown in Fig. 10(a), the LCL filter used in HP is usually
i.e., there is an inverse cubic dependence of the LCL parameters implemented as two physical parts, i.e., one three-phase inductor
on fh,sw,N for Lc and another for Lg . The LCL filter for ILV, on the other
1 1 hand, requires an additional three parts, one for each ICT in
Attreq  =     . addition to those for Lc and Lg , as shown in Fig. 10(b). Although
Lc Lg Cf ωh.sw 3 Lc L C
(kω 3
h.sw )
g f
k k k the total size and weight can still be reduced with ILV operation,
(7) the overall filter structure and interconnection becomes more
From the preceding analysis and the existing large body of complex. To reduce the total number of components and further
research, it is clear that using ILV provides a significant benefit reduce the weight of the LCL filter, an IICT can be utilized as
even with only 2-ILV. On the other hand, a thorough search of shown in Fig. 10(c), where the Lc of each phase is integrated into
the literature will find few if any implemented converters with a the ICT. That is, the IICT provides the functions for both Lc and
power greater then several tens of kW. In this paper, the goal is to the ICT at the same time [17]–[19]. The single-phase equivalent
2322 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020

Fig. 9. (a) Impact of fca on LCL parameters with 2-ILV DPWM. (b) Pareto front showing tradeoff between total inductance and capacitance as a function of
frequency.

Fig. 10. LCL filter structure for (a) hard-paralleling, (b) two-interleaving
with intercell transformer, and (c) two-interleaving with integrated intercell
transformer.

Fig. 12. Phase A current waveform for two-interleaved VSCs with DPWM,
showing the relation to the standard space vector sectors when PF = 1. Simulated
in MATLAB Simulink.

Fig. 11. Single-phase representation of two-interleaved VSCs with LCL filter B. Modeling of the Integrated ICT
and intercell transformer.
The objective of the ICT is to provide impedance to suppress
the circulating current iTM , which is caused by vTM . Typically,
circuit for the 2-ILV case is shown in Fig. 11. The current an ICT is implemented with a single-phase core with two wind-
waveforms, simulated with a closed-loop current controller in ings as shown in Fig. 13(a). The TM flux λTM flows through
MATLAB Simulink, are shown in Fig. 12. The LM and TM the core, which provides a TM inductance LTM . A small LM
voltages and currents (vLM, vTM , iLM, iTM ) are defined in (8) flux λLM is also generated through the leakage flux paths, i.e.,
and (9), respectively, with the simplification that vTM = 2vTM,1 mainly through the air between the two windings. Therefore,
= −2vTM,2 from (2), which will be used in the rest of the paper the coupling coefficient between the two windings determines
      the LM flux. Since it usually is not large enough to provide
vLM 0.5 0.5 vc,1 vc,1 1 0.5 vLM
= , = the required Lc , an additional inductor is implemented for Lc
vTM 1 −1 vc,2 vc,2 1 −0.5 vTM as shown in Fig. 10(b). To provide both Lc and LTM in one
(8) component, an IICT has been introduced which is implemented
      by adding a central leg to the core [17]–[19]. Fig. 13(b) shows
iLM 1 1 ic,1 ic,1 0.5 1 iLM
= , = . the geometry of an IICT.
iTM 0.5 −0.5 ic,2 ic,2 0.5 −1 iTM Fig. 14 presents electrical and reluctance models, which can
(9) be used for both the ICT and the IICT (by setting the center-leg
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS
Fig. 13. Intercell transformer. (a) Flux paths for LM and TM. (b) Geometry of
integrated intercell transformer; “N” is number of turns for each winding. Core
depth is represented by “c”.
Fig. 14. Modeling of intercell transformer. (a) Electrical model. (b) Equivalent
circuit in terms of LLM and LTM . (c) Reluctance model; the same model can
be used for both ICT and IICT.
Fig. 15. Equivalent circuit with integrated intercell transformer indicated by
2323
C. Design Consideration of IICT for Current Imbalance
1) LM and TM Current Ripple: As shown in Fig. 12, the
maximum peak-to-peak ripple of iTM occurs at the zero crossing
of the fundamental current of the converter (if PF = 1, also zero
crossing for voltage) and each paralleled phase is independent. It
can be explained simply by the fact that the voltage pulses of the
paralleled phases become aligned 50% duty cycle waveforms of
opposite phase. This is true for both CPWM and DPWM and
can be expressed as (11) follows:
vdc
iTM,pp = . (11)
2fca LTM
The ripple of iLM on the other hand is, in principle, due to
contributions from all three phases and is slightly different for
CPWM and DPWM as expressed in (13a) and (13b), respec-
tively. The detailed derivation for DPWM is described in [20].
The location of the maximum peak-to-peak ripple in both cases is
at the peaks of the voltage fundamental waveform, and since we
are focusing on unity power factor operation, it also occurs at the
peak of the current waveforms as shown in Fig 12. By assuming
PF = 1, the derivation can be greatly simplified because the
d-axis peak current ripple is equal to the phase A peak current
ripple and occurs when the space vector voltage reference, Vc∗ ,
crosses through the intersection of sector 6 and sector 1 (i.e.,
space vector angle θ = 0° for phase A; θ = 120° for phase B;
θ = 240° for phase C), as shown in Fig. 16(a). Therefore, the
peak current ripple for this three-phase system is derived from
the d-axis peak current ripple. At this instant, only the V1 vector
and zero vectors are used to synthesize the output voltage, since
V2 and V6 approach zero duty cycle. For CPWM the average
interleaved output voltage producing the ripple is applied for
the full duty cycle of V1 as shown in Fig. 16(b) and the peak to
peak flux ripple can be calculated as follows:
λLM,pp = (V1 − Vc ∗ ) T1 (12)
∗
where V1 = 23 vdc , Vc ∗ = M i v2dc , and T1 = VVc1 .
After substitution and simplification, the current ripple can be
expressed as (13a) dividing (12) by LLM
red color. (a) LM. (b) TM. 


vdc 2 Mi 3
iLM,pp,CPWM = − Mi (13a)
fca LLM 3 2 8
width e = 0). Fig. 14(a) shows an electrical model of the ICT, For DPWM, the V1 duty cycle is reduced by the zero duty
where L is the self-inductance and M is the mutual inductance cycle of the other phase as shown in Fig. 16(c), i.e., T1 –Tz , and
of the two windings. For the sake of analysis, L and M can thus is slightly less
be transformed into the LM inductance, LLM , and the TM 


vdc 2 Mi 3Mi 1
inductance, LTM , as defined in (10). The equivalent circuit in iLM,pp,DPWM = − − . (13b)
fca LLM 3 2 4 2
terms of LLM and LTM is shown in Fig. 14(b), where iLM
and iTM flow through LLM and LTM , respectively. When using 2) LM and TM Inductance Selection: The LLM is designed
an IICT, LLM provides the converter-side inductance Lc for according to the LCL filter design procedure discussed in Section
the LCL filter, thereby eliminating the need for an additional II considering the current ripple in (13). Design guidelines for
physical Lc . Therefore, the LM equivalent circuit and the TM the LTM , on the other hand, have not yet been fully explored in
equivalent circuit with IICT can be represented as Fig. 15(a) and literature. To begin with, it is known that LTM determines the
(b), respectively ripple of iTM (11). A large LTM reduces the iTM ripple, thereby
reducing conduction losses of the semiconductors and the losses



 of the IICT itself. On the other hand, a small LTM makes the IICT
LLM 0.5 −0.5 L
= . (10) more robust against saturation of the magnetic core caused by
LTM 2 2 M
current imbalances between ic,1 and ic,2 , which can be generated
2324 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020

Given the same iTM,dc , therefore, a lower LTM will reduce the
maximum flux of the outer-leg cores. As can be seen in Fig. 17(b)
and (c), the lower the value of kTM , the lower the peak value
of λo
λo,max1 = LLM iLM,max + 0.5LTM iTM,dc
vdc
= LLM iLM,max + kTM
2fca
iTM,dc
kTM = ∝ LTM iTM,dc (15)
iTM,pp


1 vdc 1
λo,max2 = 0.5LTM (iTM,dc + iTM,pp ) = kTM + .
2 fca 2
(16)
The maximum allowed dc current imbalance, iTM,dc,max ,
below the saturation limit of the outer-leg, can be expressed in
terms of iTM,pp as (17), where Bsat is the saturation flux density
of the core and Bmax is the maximum flux density with iTM,dc
= 0. Therefore, the maximum inductance of LTM is restricted
by iTM,dc,max


1 Bsat
iTM,dc,max = − 1 iTM,pp
2 Bmax

Fig. 16. Maximum LM current ripple. (a) Space vector diagram. Switching-
cycle waveforms for (b) CPWM and (c) DPWM on the border between sector
6 and sector 1. Vc,1 and Vc,2 are the space vectors of the two-interleaved
converters. T1 , Tz , and Tca are time intervals of V1 , V7 , and carrier period,
respectively.
by transient operation or nonsymmetric parameters between the
two converters. Thus, the relationship between LTM and the
maximum flux of the core is investigated next.
Fig. 14(c) shows the reluctance model along with the flux of
each leg of the IICT. The flux of the center leg λc and the flux
of the outer legs λo can be expressed in terms of iLM and iTM as
(14). The flux, λo , is affected by both iLM and iTM while the flux,
λc , is only affected by iLM . In other words, current imbalance
between ic,1 and ic,2 , which is represented by iTM , affects only
λo
 2) Power Loss and Thermal Model: For the sake of time-
λo LLM 0.5LTM iLM
= . (14)
λc 2LLM 0 iTM
Fig. 17(a) shows the current and flux waveforms of the IICT.
The peak value of λo can be either λo,max 1 or λo,max 2, depend-
ing on the converter operating condition, and can be expressed
as (15) and (16), respectively. It can be seen that both λo,max 1
and λo,max 2 are affected by the ratio of iTM,dc to iTM,pp (kTM ),
where iTM,dc is a dc current imbalance between ic,1 and ic,2 .
In other words, kTM is proportional to both iTM,dc and LTM .
vdc Bsat
= −1 . (17)
4fca LTM Bmax
D. Weight Optimization of IICT
The main optimization objective is finding the minimum-
weight design of the IICTs for a given LLM and LTM while
satisfying constraints, such as peak flux density, maximum
temperature, and maximum mechanical dimensions.
1) Reluctance Model: LLM and LTM are expressed as (18)
and (19), respectively, with the center-leg reluctance, Rc , and
the outer-leg reluctance, Ro , shown in Fig. 14(c). Rc and Ro are
described by the geometry of the magnetic core of the IICT,
i.e., five basic parameters (a, b, c, d, e) and the air gaps in
the center and outer legs (go , gc ). A three-dimensional (3-D)
reluctance model for each core section is obtained using the
Schwarz–Christoffel transformation to improve the air gap re-
luctance accuracy considering fringing fields [35]
N2
LLM = (18)
2 (Ro + 2Rc )
2N 2
LTM = . (19)
Ro
efficient optimization, the initial winding loss is calculated based
on a 1-D field approximation [36], [37]. Once, promising design
candidates are obtained by the Optimization procedure described
below, finite-element method (FEM) simulations are performed
to obtain accurate winding losses (details are discussed in
Section IV). The core loss is calculated using the improved
generalized Steinmetz equation [37], [38]. After all the power
losses are obtained, the temperature distribution of the IICT is
estimated using a detailed thermal network based on [39], [40].
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS 2325

Fig. 17. Current and flux waveform of integrated intercell transformer with variation of current imbalance and LTM . (a) iTM,dc = 0 A. (b) iTM,dc = 20 A and
kTM = 0.25. (c) iTM,dc = 20 A and kTM = 0.5. The results are obtained by closed-loop circuit simulation in MATLAB Simulink.

Fig. 18. Impact of LLM and LTM on weight of integrated intercell transformer
and power loss of semiconductors; LLM : 50–70 μH and LTM : 250–1000 μH.
Each dot represents a different combination of LLM and LTM . The impact of
LTM variation is observed in vertical the direction.

Fig. 19. Global optimization procedure of overall system for two-interleaved

3) Optimization Procedure: Assuming a certain window uti-
lization factor, a single IICT design can be determined by six
independent parameters (a, b, c, d, e, N), and two dependent
parameters (go and gc ). The optimization algorithm searches the
6-D parameter space to achieve the target inductances (LLM and
LTM ) while satisfying the maximum peak flux density. Then,
the power losses and temperature of each design candidate are
calculated. The minimum-weight design is selected among those
satisfying the design constraints.
4) Impact of LLM and LTM on Weight: Fig. 18 shows the
impact of the LLM and the LTM on the IICT weight and semi-
conductors power loss, where each point represents an optimal
IICT design in terms of weight for the given combination of LLM
and LTM . The inductance range is selected based on the given
current ripple (11) and (13b). It is clear that LLM has the dom-
inant impact on the IICT weight, whereas LTM has a minimal
effect. Therefore, LTM can be selected by mainly considering
semiconductor losses and robustness against saturation of the
IICT, which was discussed in the previous section.
VSCs.
IV. GLOBAL OPTIMIZATION OF TWO-INTERLEAVED
GRID-TIED CONVERTERS
A. Global Optimization of Overall System
A global optimization procedure for the overall system is
shown in Fig. 19. The target system consists of two different
mechanical frames as shown in Fig. 1; one for the VSC and
another for the LCL filter. The optimization was based on an
existing VSC, where the semiconductor power losses were a
major concern because it was desired to maximize the power
output with the existing cooling system. The main hard con-
straint for the LCL filter design was the allowed maximum
mechanical dimensions. Since the filter capacitor Cf was given
for the prototype system and has negligible weight and power
loss compared with the filter magnetic components, it was not
included in the optimization procedure.
2326 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020

The main sweep variables for the optimization procedure are

fca and kres . For each combination of fca and kres , numerous
LCL parameter sets, which satisfy IEEE519 harmonic current
limits, are generated based on the criteria developed in Section II.
LTM is selected to provide robustness against saturation of the
core caused by current imbalance as discussed in Section III. For
each combination of LCL parameters and LTM with a given fca ,
current and voltage waveforms of all components are generated.
Then, the power losses of the semiconductors are calculated
using datasheet information and all the magnetic components are
designed. The three-phase inductors for Lc and Lg are designed
based on the procedure in [2]. The ICT and IICT are designed
as presented in Section III. As noted earlier, the same design
procedure used for the IICT is also used for ICT by removing
the center leg, i.e., e = 0. Once a promising magnetic design Fig. 20. Pareto front curve: semiconductor losses versus weight of total
magnetic components.
is identified with the global optimization procedure, a local
optimization of each magnetic component is performed with
FEM simulations for fine tuning.
The optimization procedure is used to perform a comparative
evaluation of HP and ILV, using the three different filter types
shown in Fig. 10. The system specification is given in Table I.
Numerous designs are explored within the following design
space:
1) Carrier frequency fca : 3–4 kHz with DPWM.
2) Filter resonant frequency ratio kres : 0.2–0.4 for HP and
0.4–0.8 for 2-ILV.
3) Semiconductor: 1200-V, 450-A insulated gate bipolar
transistor (IGBT) module from Infineon.
4) Magnetic components are as follows.
a) Magnetic core material for ICT and IICT:
10JNHF600.
b) Magnetic core material for three-phase inductors:
M600-50A.
c) Al-foil winding for all magnetic components.
d) Forced convection cooling for all magnetics.
e) Maximum flux density of magnetic core Bmax : 60%
of Bsat . Fig. 21. Local optimization procedure of integrated intercell transformer.
The saturation constraint for the ICT and IICT is expressed
as iTM,dc,max = 1/3 iTM,pp from Eq. (16), i.e., the maximum
allowed dc current imbalance between ic,1 and ic,2 is 1/3 of the
maximum peak-to-peak ripple of iTM . B. Local Optimization of the Integrated ICT
The target of the optimization is to minimize the weight of the Once the converter design parameters are selected from the
complete LCL filter while keeping the maximum power losses global optimization, local optimization of each magnetic com-
of the VSC within the cooling limitations. Fig. 20 shows Pareto ponent is carried out for fine-tuning in terms of power loss
front curves relating semiconductor power losses and the total and weight. Local optimization of the three-phase inductors is
weight of the magnetic components for three cases: HP, ILV with carried out as described in [2]. Local optimization of the IICTs
ICT, and ILV with IICT. At this point, only the weight of the base is discussed next.
materials is considered. ILV clearly shows superior performance One significant design issue of the IICT is that, it requires a
compared to HP. ILV with IICTs can achieve slightly lower large air gap in the center leg to achieve the target inductances
weight compared to ILV with ICTs with the same semiconductor of LLM and LTM simultaneously, since typically LTM is more
power losses. Considering the maximum allowed power losses than 10 times larger than LLM . The accuracy of the analytical
of the semiconductors and the mechanical size constraints of the models used for design of the IICT in Section III, decreases as the
LCL filter frame, the converter parameters to achieve minimum length of the air gap increases. Therefore, additional fine tuning
weight of the LCL filter for ILV with IICT are the following. of the IICT is necessary with FEM simulations as described in
1) fca = 3.6 kHz and fres = 2.3 kHz (kres = 0.63). the flowchart in Fig. 21.
2) Lc = 50 μH, Lg = 40 μH, Cf = 220 μF and LTM = Fig. 22 shows the results of the local optimization of the
1 mH. IICT. Since the IICT has a large air gap in the center leg,
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS
Fig. 22. Local optimization results of integrated intercell transformer.
(a) Impact of core dimension a. (b) Impact of core dimension gv . (c) Winding
loss breakdown on the selected design; x-axis shows frequency and y-axis shows
winding losses corresponding to the current waveform at each frequency. All
data are obtained from 2D FEM simulation.
the associated fringing fields significantly affect the winding
losses. Consequently, the calculation using the analytical models
underestimated the losses by about a factor of two compared to
the calculation using an approximated 1-D field equation. Based
on this analysis, the distance between the winding and the core
was adjusted to reduce the proximity losses while at the same
time keeping the weight of the IICT as low as possible. Even
though the fringing fields significantly increase high frequency
losses, compared to the total losses, the proportion is relatively
negligible compared to the fundamental component.
Looking into the details of the optimization procedure, Fig. 22
shows the results of the inner optimization loop (Fig. 21) where
the dimensions a and gv are optimized while all other parameters
are fixed. The inductances LLM and LTM are maintained close
to the design target values. All the data is derived from 2D FEM
simulations. The key for understanding the curves in Fig. 22 is
2327
Fig. 23. Magnetostatic 3D FEM simulation of integrated intercell transformer
to verify maximum flux density of outer-leg and center leg of the core; simulation
at current phase angle (a) ϕA and (b) ϕB in Fig. 17(a).
Fig. 24. Final mechanical design of integrated intercell transformer; dimen-
sions in “mm”.
the fact that the gap in the outer core leg is very small resulting
in negligible fringing field losses, while the much larger gap
of the center leg results in significant fringing field losses. As
shown in Fig. 22(a), the winding losses are smaller with smaller
dimension gv because the wire length and the associated losses
become smaller, while the increasing proximity to the outer gap’s
fringing field rises but is still negligible. Increasing dimension a
at a fixed gv increases the distance between winding and center
leg gap, which reduces the large central leg gap’s fringing field
losses.
The described effect is also shown in Fig. 22(b), where for the
given dimension a = 157 mm the dimension gv is varied. For
gv = 0 mm, the winding is closest to the outer leg gap’s fringing
field (negligible due to very small gap), whereas at gv = 15 mm,
the winding is closest to the center leg gap’s fringing field
(significant due to large gap). While the wire length and the
associated ohmic losses increase in a linear way with dimension
gv , the winding losses increase in a nonlinear fashion when
getting closer to the large gap in the center leg.
Reducing the winding losses by increasing dimension a in-
creases the core weight. As a compromise an optimal design
was finally chosen at a = 157 mm. As a side condition, we
must employ a minimum distance between core and winding for
mechanical design (bobbin) and convection cooling resulting in
gv = 5 mm.
Fig. 23 shows the results of magnetostatic 3D FEM simu-
lations used to verify the peak flux densities and the required
inductances. As shown in Fig. 17, the maximum flux of λc occurs
in phase with the peak current of iLM at an angle of ϕB , whereas
the maximum flux of λo occurs near the current zero crossing at
an angle of ϕA . Fig. 24 shows the final mechanical design and
2328
TABLE II
FINAL DESIGN PARAMETER OF INTEGRATED INTERCELL TRANSFORMER
Fig. 25. Full-scale system. (a) Overall structure of back-to-back system.
(b) Picture of total system.
Table II shows final design parameters and performance of the
IICT.
V. EXPERIMENTAL RESULTS
A. 260-kW Back-to-Back System
To verify the analysis performed and the optimization pro-
cedure, a 260-kW full-scale system was built based on the
optimization results in Section IV. To minimize power consump-
tion of the test setup, a back-to-back power circulating system
was implemented with the configuration shown in Fig. 25.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020
Fig. 26. LM and TM current control diagram; ξαβ = [ξα ξβ ]T and ξabc =
[ξa ξb ξc ]T .
Fig. 27. Timing diagram of LM and TM current controllers.
The back-to-back setup consists of two-paralleled VSCs with
a selectable LCL filter configuration and a load converter with
its own LCL filter. A transformer is inserted in the loop to prevent
a common-mode circulating current within the back-to-back
system. Since the grid impedance is negligible compared to that
of the transformer, interaction between the two-paralleled VSCs
and the load converter can be neglected in terms of harmonics
and stability. Depending on the type of testing undertaken (HP
or ILV), the proper interconnection of the VSCs and LCL filters
is established with a set of mechanical switches.
B. Longitudinal and Transverse Mode Current Controller
The overall current control structure used for ILV operation is
presented in Fig. 26, which consists of an LM current controller
and a TM current controller. All converter side currents (ic,1,abc
and ic,2,abc ) are measured. The LM current controller is based
on stationary frame αβ-coordinates, whereas the TM current
control is based on abc-coordinates. Fig. 27 shows a timing
diagram for the control system, where Tca , Tsp,LM , and Tsp,TM
represent the switching carrier period, the sampling period for
the LM current controller, and the sampling period for the TM
current controller, respectively.
For the LM current ic , sum of ic,1 and ic,2 , a proportional
resonant (PR) controller is used [41]. Without active damping
(AD) of the controller, the critical fres , beyond which the system
becomes unstable, is about 1/6 of the sampling frequency fsp
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS 2329

Fig. 28. LCL filter prototype for 260-kW two-interleaved VSCs. (a) Integrated intercell transformer. (b) LCL filter for interleaving operation. (c) Size comparison:
commercial state-of-the-art weight-optimized LCL filters for hard-paralleling versus developed LCL filter with integrated intercell transformer for interleaving
operations.

Fig. 29. Key experimental waveforms. (a) Hard-paralleling. (b) Interleaving with IICT.

[30], [31]. Since fres is rather high for the ILV operation as
discussed in Section II-C, it is difficult to stabilize ILV operation
with a standard PR controller using asymmetric regular sampling
(fsp = 2fca ). To stabilize the system without additional mea-
surements, a filter-based AD approach was adopted [32]–[34].
In addition, the control sample frequency was doubled to reduce
the digital control delay as shown in Fig. 27 i.e., fsp,LM = 4fca .
It is noted that with a four times sampling frequency, the
LM controller does not see the switching ripple because the
odd-harmonic components are removed from iLM by the ILV
operation.
To prevent saturation of the IICT caused by iTM , the dc-offset
current of iTM (iTM,dc ) is controlled to zero by the TM current
controller. To measure the average iTM , a sample frequency of
two times the carrier frequency is used as shown in Fig. 27,
i.e., fsp,TM = 2fca . To prevent interaction with the LM current
controller, the TM controller output, dTM,abc , is added to and
subtracted from the duty cycle of the paralleled phases of each
converter. A simple proportional controller is used where the
controller gain is selected so that every switching cycle iTM,dc
is adjusted to zero, i.e., deadbeat response.
The control and the modulators of the system are implemented
with a Texas Instruments TMS320F28346 floating-point digital
signal processor. The control variables are all measured directly
on the control board and sent to the controller. The gate signals
for the VSCs are sent one by one to each semiconductor through
12 fiber optic cables.
C. Measurement Data—Hard-Paralleling Versus ILV
Fig. 28(a) shows the implemented IICT based on the optimiza-
tion procedure in Section IV-B. Fig. 28(b) shows the complete
prototype LCL filter for the ILV VSC. The three IICT compo-
nents and one three-phase inductor for Lg are installed inside the
mechanical frame. A 120-W centrifugal fan was used for forced
air convection cooling. The filter capacitor Cf was attached
outside of the frame, since its power loss is negligible. Fig. 28(c)
shows the size comparison of the designed LCL filter for ILV and
2330 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 3, MARCH 2020

Fig. 30. Zoomed experimental waveforms. (a) Hard-paralleling. (b) Interleaving with IICT.

Fig. 31. Harmonic current spectrum of grid-side current ig . (a) Hard-paralleling. (b) Interleaving with IICT; the green dots represent IEEE519 harmonic limits.
Here, only odd harmonic limits are considered.

the existing LCL filter for HP. It is noted that the HP LCL filter TABLE III
EXPERIMENTAL RESULTS
is a state-of-the-art weight-optimized design, which is currently
being used for commercial products. Both filters were designed
for the specification in Table I with the same constraints, such
as maximum semiconductor power losses, maximum inductor
temperature, and maximum flux density.
Power loss of the system was measured with a Yokogawa
WT3000 precision power analyzer, the IGBT temperature was
measured with a negative temperature coefficient (NTC) ther-
mistor installed inside the semiconductor module and the IICT
temperature was monitored with multiple thermocouples in-
serted into the structure. The system was operated at the rated
power until steady state temperatures were achieved (more than
an LCL filter with 30% lower weight, total power loss reduced
2 h) to ensure thermal limits were not exceeded. Fig. 29 shows
by 6%, and THD and Ih.sw reduced while maintaining the same
the key experimental waveforms and Fig. 30 shows zoomed
temperature of the IGBTs.
in waveforms. Fig. 31 shows the harmonic spectrums of the
grid-side current ig . Overall, the harmonic current spectrums
for both cases (HP and 2-ILV) are well suppressed. In the case VI. CONCLUSION
of HP, Ih.sw appears at around fca while it appears at 2fca for The main objective of this paper is providing a comprehensive
ILV operation. It should be noted that Ih.sw for ILV satisfies the hardware optimization methodology and experimental verifica-
IEEE519 limit, which is the attenuation target of the LCL filter tion for two-interleaved high power (260 kW) VSCs with an LCL
while that of HP slightly exceeds the limit. Table III provides filter, in consideration of harmonic standards, PWM methods,
the key experimental results. In summary, ILV operation with filter structure, magnetic components, and semiconductor power
the IICTs demonstrates superior performance in every aspect: losses.
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS
First, the impact of the number of interleaved VSCs and the
PWM method on the LCL filter is investigated. It is clear that a
higher ILV number reduces the LCL filter size requirements. As
a consequence of the smaller LCL filter values though, the filter
will have a higher fres for ILV that requires a more careful current
controller design with a higher sampling frequency. It is shown
that when 2- or 4-ILV is used DPWM requires slightly lower
LCL filter values compared with CPWM to satisfy IEEE519 at
the same fca . Considering the lower switching losses of DPWM
compared to CPWM at the same fca , it becomes an even more
promising PWM method for ILV.
The design considerations for the IICT in terms of peak flux
density and current imbalance are introduced and analyzed and
the weight-optimization procedure is developed. In the global
optimization results for 2-ILV VSCs, it is shown that an overall
25%–30% weight reduction in magnetic components of the LCL
filter can be achieved with 2-ILV compared to HP under the
same semiconductor power losses, mainly owing to the smaller
required LCL filter values. In addition, implementation with
IICTs provides an additional weight reduction of 10%–15% over
that with ICTs.
A significant contribution of this paper is the development
of the highest power IICT for an LCL filter reported in the
literature. The thorough experimental verification of the IICT
in a 260-kW three-phase grid-tied converter demonstrated that
the optimization procedure met all the specifications. The exper-
imental results with the prototype showed that the total weight
of the LCL filter for 2-ILV, including the mechanical frame and
cooling system, is 30% lighter than the commercial state-of-the-
art LCL filter for HP with the same semiconductor temperatures
while maintaining the current harmonics below the IEEE519
limits.
APPENDIX A
EXTENSION TO N-INTERLEAVED VSCS
Control and modulation for N-ILV operation can be imple-
mented as shown in Fig. 32, where iLM and iTM,n are obtained
based on (20a) and (20b), respectively
N
 interleaving on AC passive components of paralleled three-phase voltage-
iLM = ic,n (20a)
n=1
iLM
iTM,n = ic,n − . (20b)
N Jun. 2011.
Compared with the 2-ILV controller shown in Fig. 26, only
the TM controller is extended for N-ILV VSCs. The sampling
frequency of the LM controller for N-ILV can be increased
to 2N fca compared with HP operation of which the sampling
frequency is 2fca . Since only the Nth harmonic contents appears
in iLM by N-ILV operation, the LM controller does not see the
switching ripples with the sampling frequency of 2N fca .
As for LCL filter implementation, it is noted that ICT and
IICT for 2-ILV VSCs can also be extended to N-ILV VSCs as
described in [15], [16].
2331
Fig. 32. LM and TM current control diagram for N-interleaving operation;
ξαβ = [ξα ξβ ]T and ξabc = [ξa ξb ξc ]T .
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Ki-Bum Park (M’10) received the B.S., M.S., and
Ph.D. degrees in electrical engineering from the Ko-
rea Advanced Institute of Science and Technology
(KAIST), Daejeon, South Korea, in 2003, 2005, and
2010, respectively.
He was a Researcher with KAIST, in 2010, fo-
cusing on Si/SiC-based high frequency power elec-
tronic converters. He is currently with ABB Corporate
Research Center, Baden, Switzerland, as a Principal
Scientist. He has authored/coauthored more than 80
papers including one-third in peer-reviewed journals.
His research interests include power conversion system for EV charging in-
frastructure, grid integration of renewables, and application of wide bandgap
semiconductor (SiC and GaN) in association with system-level optimization of
power electronics.
Frederick D. Kieferndorf (M’98) received the B.S,
M.S., and Ph.D. degrees in electrical engineer-
ing from the University of Wisconsin – Madison,
Madison, WI, USA, in 1990, 1997, and 2003, respec-
tively.
His research at the University of Wisconsin in-
volved both electric machine analysis and motor drive
technology. As a part of his thesis work, he devel-
oped an active rectifier and inverter motor drive to
analyze the effects of adjustable voltage operation
on drive components. From 2003 to 2006, he was
with International Rectifier Corporation, El Segundo, CA, USA, where he was
involved in the development of integrated power electronic ICs for automotive
applications. Since 2006, he has been with ABB Corporate Research, Baden,
Switzerland, where he has worked on a broad range of projects in the areas of
power electronics and drives, including modeling multiphase machines, control
of drives, and control of grid side converters and resonant converters. His
research interests include power electronics, control, electric machine analysis,
and high-performance electric drives.
Uwe Drofenik (M’00) received the Ph.D. degree
from the Vienna University of Technology, Wien,
Austria, in 1999.
In 2001, he joined the ETH Zurich as Postdoc Re-
searcher working on power electronics, integration,
and converter optimization. In 2008, he cofounded
the simulation software company Gecko-Research,
Zurich, Switzerland. In 1996, he was a Researcher
at the University of Tokyo, Tokyo, Japan. In 2010,
he joined ABB Corporate Research, Baden, Switzer-
land, where he is working on magnetics, power elec-
tronics, and power systems. He has authored/coauthored more than 85 papers
and patents.
Dr. Drofenik was a recipient of the “Takahashi Award” from IEE Japan, in
2005.
PARK et al.: OPTIMIZATION OF LCL FILTER WITH INTEGRATED ICT FOR TWO-INTERLEAVED HIGH-POWER GRID-TIED CONVERTERS
Sami Pettersson (M’06) received the M.Sc. and
D.Sc. degrees in electrical engineering from Tampere
University of Technology, Tampere, Finland, in 2004
and 2009, respectively.
Since 2008, he has been with ABB Corporate
Research, Baden, Switzerland, where he is currently a
Principal Scientist in the Power Electronic Converters
group. Over the years, he has been part of several
technology development projects as a Technical Spe-
cialist as well as a Project Manager in the field of low-
voltage power conversion technologies for industrial
applications, such as motor drives, solar and wind power converters, and active
power filters. His research interests include the optimized design and control of
low-voltage power converters.
2333
Francisco Canales (M’95) received the B.S. degree
in mechanical and electrical engineering from Uni-
versidad Veracruzana, Veracruz, México, the M.Sc.
degree in electronic engineering from Centro Na-
cional de Investigación y Desarrollo Tecnológico
(CENIDET), Cuernavaca, México, and the Ph.D. de-
gree in electrical engineering from the Virginia Poly-
technic Institute and State University, Blacksburg,
VA, USA, in 2003.
He was a Senior Research Assistant with the
Center for Power Electronics Systems, Virginia Tech,
Blacksburg, where he was involved in core research and several industry-
sponsored projects. He was an Associate Professor with the Department of
Electronic Engineering, CENIDET. He is currently a Corporate Research Fellow
with ABB Corporate Research Ltd., Baden, Switzerland. His research interests
include modular converter designs, resonant switching concepts, and high-
efficient conversion topologies for industrial, traction, and renewable energy
applications.