I.

Addressing modes:
1. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
Answer:B
2. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Answer: c
3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is
requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
Answer: b
4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: a
5. In the following indexed addressing mode instruction, MOV 5(R1), LOC the
effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
Answer: d
6. The addressing mode/s, which uses the PC instead of a general purpose register
is ______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
Answer: b
7. When we use auto increment or auto decrements, which of the following is/are
true?
1) In both, the address is used to retrieve the operand and then the address gets
altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory
locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
Answer: d
8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
Answer: a
9. The effective address of the following instruction is MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2]
d) 5*([R1]+[R2])
Answer: c
10. _____ addressing mode is most suitable to change the normal sequence of
execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Answer: a

II. Main Memory Organization:

1. Any electronic holding place where data can be stored and retrieved later
whenever required is ____________
a) memory
b) drive
c) disk
d) circuit
Answer: a
2. Cache memory is the onboard storage.
a) True
b) False
Answer: a
3. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory
Answer: a
4. The memory implemented using the semiconductor chips is _________
a) Cache
b) Main
c) Secondary
d) Registers
Answer: b
5. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache
Answer: a
6. Which of the following is independent of the address bus?
a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory
Answer: a
7. ____________ storage is a system where a robotic arm will connect or disconnect
off-line mass storage media according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic
Answer: c
8. What is the location of the internal registers of CPU?
a) Internal
b) On-chip
c) External
d) Motherboard
Answer: b
9. MAR stands for ___________
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register
Answer: a
10. If M denotes the number of memory locations and N denotes the word size, then
an expression that denotes the storage capacity is ______________
a) M*N
b) M+N
c) 2M+N
d) 2M-N
Answer: a

III. I/O Organization:

1. In memory-mapped I/O ____________

a) The I/O devices and the memory share the sameaddress space
b) The I/O devices have a seperate address space
c) The memory and I/O devices have an associatedaddress space
d) A part of the memory is specifically set aside for the I/Ooperation
Answer: a
2. The usual BUS structure used to connect the I/O devicesis
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer: c
3. In intel�s IA-32 architecture there is a seperate 16 bitaddress space for the
I/O devices?
a) False
b) True
Answer: b
4. The advantage of I/O mapped devices to memorymapped is
a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a biggerbuffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Answer: c
5. The system is notified of a read or write operation by
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
Answer: d
6. To overcome the lag in the operating speeds of the I/Odevice and the processor
we use
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer: b
7. The method of accessing the I/O devices by repeatedlychecking the status flags
is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
Answer: c

IV. Micro-programmed Control

1. ____________ is the raw material used as input and __________ is the processed
data obtained as output of data processing.
a) Data, Instructions
b) Instructions, Program
c) Data, Program
d) Program, Code
Answer: a
2. Which of the following is not a characteristic of a computer?
a) Diligence
b) I.Q.
c) Accuracy
d) Versatility
Answer: b
A computer is diligent because it can work continuously for hours without getting
any errors or without getting grumbled.
The accuracy of a computer is consistently high and its level of accuracy depends
on its design. A computer can perform any task if, it can be broken down into a
series of logical steps. Therefore, a computer is versatile.
3. Fill in the blank in the diagram.
computer-fundamentals-questions-answers-control-unit-q3
a) Input Unit
b) Memory Unit
c) Control Unit
d) I/O Unit
Answer: c
4. The part of a processor which contains hardware necessary to perform all the
operations required by a computer:
a) Data path
b) Controller
c) Registers
d) Cache
Answer: a
5. What does MAR stand for?
a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
d) Memory Address Register
Answer: d
6. If the control signals are generated by combinational logic, then they are
generated by a type of _______________ controlled unit.
a) Micro programmed
b) Software
c) Logic
d) Hardwired
Answer: d
7. Which is the simplest method of implementing hardwired control unit?
a) State Table Method
b) Delay Element Method
c) Sequence Counter Method
d) Using Circuits
Answer: a
8. A set of microinstructions for a single machine instruction is called
___________
a) Program
b) Command
c) Micro program
d) Micro command
Answer: c
9. Micro-program consists of a set of microinstructions which are strings of 0s and
1s.
a) True
b) False
Answer: a
10. A decoder is required in case of a ______________
a) Vertical Microinstruction
b) Horizontal Microinstruction
c) Multilevel Microinstruction
d) All types of microinstructions
Answer: a

V.Cache Memory:

1. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory
Answer: b
2. Cache Memory is implemented using the DRAM chips.
a) True
b) False
Answer: b
3. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR
Answer: a
4. LRU stands for ___________
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
Answer: c
5. When the data at a location in cache is different from the data located in the
main memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault
Answer: b
6. Which of the following is not a write policy to avoid Cache Coherence?
a) Write through
b) Write within
c) Write back
d) Buffered write
Answer: b
7. Which of the following is an efficient method of cache updating?
a) Snoopy writes
b) Write through
c) Write within
d) Buffered write
Answer: a
8. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
Answer: a
9. The number of sign bits in a 32-bit IEEE format is ____
a) 1
b) 11
c) 9
d) 23
Answer: a
10. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfer
Answer: b

VI. Secondary Storage

1. Which one of the following is not a secondary storage?

a) Magnetic disks
b) Magnetic tapes
c) RAM
d) None of the mentioned
Answer: c
2. Which private network uses storage protocol rather than networking protocol?
a) storage area network
b) local area network
c) wide area network
d) none of the mentioned
Answer: a
3. The time for the disk arm to move the heads to the cylinder containing the
desired sector is called ___________
a) disk time
b) seek time
c) arm time
d) sector time
Answer: b
4. Which algorithm of disk scheduling selects the request with the least seek time
from the current head positions?
a) SSTF scheduling
b) FCFS scheduling
c) SCAN scheduling
d) LOOK scheduling
Answer: a
5. The operating system is responsible for?
a) disk initialization
b) booting from disk
c) bad-block recovery
d) all of the mentioned
Answer: d
6. A swap space can reside in ___________
a) Separate disk partition
b) RAM
c) Cache
d) None of the mentioned
Answer: a
7. RAID level 1 refers to ___________
a) disk arrays with striping
b) disk mirroring
c) both disk arrays with striping and disk mirroring
d) none of the mentioned
Answer: b
8. When we write something on the disk, which one of the following can not happen?
a) successful completion
b) partial failure
c) total failure
d) none of the mentioned
Answer: d
9. What will happen during the recovery from a failure?
a) each pair of physical block is examined
b) specified pair of physical block is examined
c) first pair of physical block is examined
d) none of the mentioned
Answer: a
10. The replacement of a bad block generally is not totally automatic because
___________
a) data in bad block can not be replaced
b) data in bad block is usually lost
c) bad block does not contain any data
d) none of the mentioned
Answer: b

Topics matter:
Machine Instructions:
Machine Instructions are commands or programs written in machine code of a machine
(computer) that it can recognize and execute.
A machine instruction consists of several bytes in memory that tells the processor
to perform one machine operation.
The processor looks at machine instructions in main memory one after another, and
performs one machine operation for each machine instruction.
The collection of machine instructions in main memory is called a machine language
program.
Machine code or machine language is a set of instructions executed directly by a
computer�s central processing unit (CPU). Each instruction performs a very specific
task, such as a load, a jump, or an ALU operation on a unit of data in a CPU
register or memory. Every program directly executed by a CPU is made up of a series
of such instructions.
The general format of a machine instruction is
Brackets indicate that a field is optional
Label is an identifier that is assigned the address of the first byte of the
instruction in which it appears. It must be followed by �:�
Inclusion of spaces is arbitrary, except that at least one space must be inserted;
no space would lead to an ambiguity.
Comment field begins with a semicolon � ; �
Example:
Here: MOV R5,#25H ;load 25H into R5

CPU organisation:
https://www.slideshare.net/sangitavishwakarma1/cpu-organisation