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module dff(d,clk,q);

input d;
input clk;
wire d;
wire clk;
output q;
reg q;
initial
q = 1'b0;
always @(posedge clk)begin
q <= d;
end
endmodule
//************************Test Bench******************//
module FOURbit_up_B();
reg clk;
reg d;
wire [3:0]q;
initial
clk = 0;
always
#1 clk = !clk;
dff a1(!q[0],clk,q[0]);
dff a2(!q[1],!q[0],q[1]);
dff a3(!q[2],!q[1],q[2]);
dff a4(!q[3],!q[2],q[3]);
endmodule

This was Aynchronous Up counter.


Pay attention here that clock input to each FF is ~Q (Q bar). Thus for Down counter the clock
input after 1st FF will be from Q and not ~Q (Q bar)

Here is the block diagram for 4 bit Down Asynchronous Counter


Notice the clock inputs to each FF after 1st FF.

Here is the code for Down Counter 4 bit

module dff(d,clk,q);
input d;
input clk;
wire d;
wire clk;
output q;
reg q;
initial
q = 1'b0;
always @(posedge clk)begin
q <= d;
end
endmodule

module FOURbit_up_B();
reg clk;
reg d;
wire [3:0]q;
initial
clk = 0;
always
#1 clk = !clk;
dff a1(!q[0],clk,q[0]);
dff a2(!q[1],q[0],q[1]);
dff a3(!q[2],q[1],q[2]);
dff a4(!q[3],q[2],q[3]);
endmodule

and heres the simulation wave window from Xilinx iSim