Ch27 Phase-Locked Loops 1290

Phase-Locked Loops
Jieh-Tsorng Wu
July 16, 2002
ES
National Chiao-Tung University
A
1896
Department of Electronics Engineering
Phase-Locked Loops (PLLs)
VFO
Vc
Ai Phase Loop
Ao
Detector Filter
Ai = g1 (ωi t + θi ) Ao = g2 (ωot + θo) ωo = ωoo + Kc · Vc
• g1 and g2 are periodic functions with 2π period.
• When the loop is locked, the frequency of the VCO is exactly equal to the average
frequency of the input.
• The loop filter is a low-pass filter that suppresses high-frequency signal components
in the phase difference.
PLLs 27-2 Analog ICs; Jieh-Tsorng Wu

Phase-Locked Loops (PLLs)
Applications:
• Automatic frequency control.
• Frequency and phase demodulation.
• Data and clock recovery.
• Frequency synthesis.
References:
• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.
• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.
• Floyd M. Gardner, “Phaselock Techniques,” 2nd Edition, John Wiley & Sons, 1979.

Basic Model
Vd = Kd (θi − θo) ωo = ωoo + Ko × Vc

Vd Vc
θi
PD F(s) Ko/s θo
Phase Filter VFO

Detector
When the PLL is locked,
Vd (s) = Kd · [θi (s) − θo(s)] = Kd θe(s) θe = θi − θo

Vc(s) = F (s) · Vd (s)

Ko
ωod t = ωoot + KoVcd t = ωoot + θo ⇒ θo(s) = Vc(s) ·
s
• θe is the phase error, Kd is the phase-detector gain factor, and Ko is the VCO gain
factor.

Basic Model
System equations are
Ko
Vd = Kd · (θi − θo) = Kd · θe Vc = F (s) · Vd θo = Vc ·
s
The transfer functions are
θo KoKd F (s)
= = H(s)
θi s + KoKd F (s)
θe s
= = 1 − H(s)
θi s + KoKd F (s)
Vc sKd F (s) s
= = · H(s)
θi s + KoKd F (s) Ko
∆ωo Vc
⇒ H(s) = = Ko · ∆ωi = ωi − ωoo ∆ωo = ωo − ωoo
∆ωi ∆ωi
• H(s) is the closed-loop transfer function.

Second-Order PLL — Active Lag-Lead Filter
R2 C
sτ2 + 1
R1 F (s) = −
sτ1
Vi Vo
τ1 = R1 C
τ2 = R2 C

2
2ζ ωns + ωn KoKd ωn
H(s) = ωn = ζ= · τ2
s2 + 2ζ ωns + ω2n τ1 2
• ωn is the pole frequency of the loop.
• ζ is the damping factor. Qp = 1/(2ζ ) is the pole quality factor.

Second-Order PLL — Passive Lag-Lead Filter
R1
Vi Vo
sτ2 + 1
F (s) =
sτ1 + 1
R2
τ1 = (R1 + R2)C
C
τ2 = R2C

s 2ζ ωn −
2
ωn/(KoKd )
2
+ ωn
KoKd ωn 1
H(s) = ωn = ζ= τ2 +
s2 + 2ζ ωns + ω2n τ1 2 KoKd
• If R2 = 0, then
ωn ω2n
1 1
τ1 = = ωn = KoKd ωLF ζ= H(s) =
R1C ωLF 2KoKd s2 + 2ζ ωns + ω2n

High-Gain Second-Order PLL Frequency Response
If KoKd τ2 1 in the passive filter, then
2
2ζ ωns + ωn
Hpassive(s) ≈ Hactive(s) =
s2 + 2ζ ωns + ω2n
And the −3 dB bandwidth of H(s) is
1/2
ω−3dB = ωn 2ζ 2 + 1 + (2ζ 2 + 1)2 + 1
• Usually choose ωn < ωi /10 to remove the high-frequency components at ωi , 2ωi ,

. . . , existing in the phase detector’s output.
• The PD output’s high-frequency components can show up as spurious tones in the

frequency spectrum of the PLL’s output.

High-Gain Second-Order PLL Frequency Response
10
ζ = 5.0
5
ζ = 2.0
| H ( j ω) | (dB)
-5
ζ = 0.3
-10
ζ = 0.5
-15
ζ = 0.707
-20
0.1 1 10
Frequency (ω/ωn )

Step Response of a Two-Pole System
Consider the following two-pole transfer function
2
ωn
H(s) = Poles = s1,2 = −ζ ± ζ 2 − 1 ωn
s2 + 2ζ ωns + ω2n
• If ζ > 1, the system is overdamped, and both poles are real.

1 1 −k1ωnt 1 −k2ωnt
Step Response = 1 −
e − e
2 ζ 2 − 1 k1 k2

k1 = ζ − ζ 2 − 1 k2 = ζ + ζ 2 − 1
• If ζ = 1, the system is critically damped, and both poles are at −ωn .
Step Response = 1 − (1 + ωnt)e−ωnt ≈ 1 − e−ωnt/(2ζ ) if 4ζ 2 1

Step Response of a Two-Pole System
• If ζ < 1, the system is underdamped.

ζ ωn
Step Response = 1 − · sin ωd t + cos ωd t e−ζ ωnt ωd = 1 − ζ 2 · ωn
ωd
√
% Overshoot = 100e−π/ 1/ζ −1
2
Step Response
Overshoot
Error Band
√
• For PLL, choose ζ > 1/ 2 = 0.707 to avoid excessive ringing.

Phase Jitter
Probability
Density
V
N nt
θn θn
2 2
Vs nc pdf = √
1 −θ /(2σ )
e n n
2πσn
v(t) = s(t) + n(t) = Vs sin(2πfot) + n(t)

n(t) = nc(t) sin(2πfot) + nt (t) cos(2πfot)
The phase jitter is

nt (t)
nt (t)
θn(t) = tan ≈
Vs + nc(t) Vs

Phase Jitter
Assume that
1 2 1 2
n2 = ·n + ·n n2c = n2t
2 c 2 t
Then, we have
n2t n2 1 1
σn2 = θn2 = = = ·
Vs2
Vs2 2 SNR
• SNR is the signal-to-noise ratio, and can be expressed as
2
Vs /2
SNR ≡
n2

Phase Noise
Power Ps
Spectral
Density
L(fm)
Pssb
fm
Freq
fo
v(t) = Vs sin [2πfot + θn(t)]

Phase Noise
• The phase noise L(fm ), usually in dBc, is the ratio of the single-sideband (SSB) power
in a 1-Hz bandwidth fm Hz away from the carrier to the total signal power, i.e.,
Ps
L(fm) ≡
Pssb
• Let Sθn (f ) be the power spectral density of θn(t) in frequency domain, it can be shown
that ∞
Sθn (fm) ≈ 2L(fm) and θn2 = Sθn (f )d f
0

PLL Noise Response
θn,i nvc θn,vf o
θi Kd F(s) Ko/s θo
Let θn,o be the phase noise in θo, we have

Sθn,o KoKd F (s) 2
= 2
s + K K F (s) = |H(j ω)|
Sθn,i o d s=j ω
2
Sθn,o s
= = | 1 − H(j ω) |
2
Sθn,vf o s + KoKd F (s) s=j ω
Sθn,o Ko
2

Ko 2

=

= [1 − H(j ω)] ·
Snv s + KoKd F (s) s=j ω j ω
c

PLL Noise Response
Consider only a white noise Sθn,i (f ) in θi ,

∞
2
θn,o = Sθn,i (f )|H(j 2πf )|2 d f = Sθn,i (f ) × BL
0
BL is the noise bandwidth of H(j 2πf ), i.e.,

∞
BL ≡ |H(j 2πf )|2d f
0
For the 2nd-order PLL with active lag-lead filter

1 1
BL = ωn ζ +
2 4ζ
• BL,mi n occurs at ζ = 0.5.
• BL < 1.25BL,mi n for 0.25 < ζ < 1.0.

Phase Detection Using Analog Multiplier
V1
Vd
V2 Vd
− 12 π 3
π
2 2π
θe
−2π − 32 π 1
π
2
-π π
V1(t) = V1 sin(ωt + θ1) V2(t) = V2 cos(ωt + θ2)

1
Vd (t) = kV1 (t)V2 (t) = kV1 V2 [sin(θ1 − θ2) + sin(2ω + θ1 + θ2)]
2

Phase Detection Using Analog Multiplier
The 2ω component will be filtered out by the loop filter, hence consider the dc component
only
1
Vd = kV1 V2 sin(θ1 − θ2) = Kd · sin(θe) θe = θ 1 − θ 2
2
• Kd is the phase-detector gain factor, and θe is the phase error.
• If θe 1, vd ≈ Kd θe.
◦
• V1(t) and V2 (t) are 90 out of phase when θe = 0.

PLL Tracking Performance — Hold-In Range
From the final value theorem
2
s θi (s)
lim θe(t) = lim sθe(s) = lim
t→∞ s→0 s→0 s + KoKd F (s)
The hold-in range, ∆ωH , is the frequency range in which a PLL can maintain lock
statically.
∆ωH
ωi = ωo + ∆ωH θi (t) = ∆ωH · t θi (s) = ∆ωH /s 2
⇒ lim θe(t) =
t→∞ KoKd F (0)
• For a sinusoidal PD, the criterion becomes
∆ωH
lim sin θe(t) = <1 ⇒ ∆ωH = KoKd F (0)
t→∞ KoKd F (0)
For a 2nd-order PLL with active filter, F (0) → ∞, thus ∆ωH → ∞.

PLL Tracking Performance — Pull-Out Range
The pull-out range ∆ωP O is the frequency-step limit below which the PLL does not skip
cycles but remains in lock.
• For a sinusoidal PD
∆ωP O = 1.8ωn(ζ + 1) for 0.5 < ζ < 1.4

Noisy PLL Tracking Performance
Define the SNR of a PLL as

1
SNRL ≡
2
2θn,o
• As a rule of thumb, SNRL > 6 dB is required for stable operation.
For low SNRL, the VFO phase occasionally slips one or more cycles as compared to the
input. Define TAV as the average time between cycle slips.
4SNRL
• For a 1st-order loop TAV ≈ π
4BL
e , where BL is the PLL noise bandwidth.
1 πSNRL
• For a 2nd-order loop with ζ = 0.707 TAV ≈ BL
e .
• The slips of a 1st-order loop are almost always single, isolated events.
• The slips in a 2nd-order loop tend to bunch in bursts.

PLL Acquisition Behavior
Loop Filter
VFO
Vi Phase
F(s) Vo
Detector
• The process of bringing a PLL into lock is called acquisition.
• Acquisition is inherently a nonlinear phenomenon.
• An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integrator

there is associated a state variable of the loop: phase, frequency, frequency rate,
and so on. To force the loop into lock, it is necessary to bring each of the state
variables close to the corresponding parameters of the input signal. Therefore, we
should speak of phase acquisition, frequency acquisition, and so forth.

Phase Acquisition of a First-Order Loop
θ˙e
Ko Kd
∆ω
Ko Kd
− sin θe
VCO
Vd
Vi Phase
Vo
Detector
θe
Vd = Kd · sin θe ωo = ωoo + Ko · Vd θe = θi − θo
t
θe = θi − θo = ωi t − ωoot − KoKd sin θed t − θo(0)
0
d θe
⇒ = θ˙e = ∆ω − KoKd sin θe ∆ω = ωi − ωoo
dt
• The loop is locked when θ˙e = 0.
• There is no cycle skipping in the acquisition process.

Phase Acquisition of a Second-Order Loop
The lock-in range, ∆ωL, is the frequency range over which the PLL can acquire lock
without cycle slipping.
log |F (j f )|
By practical considerations, the lock-

in process of a higher-order loop is
so fast that it can be approximated by
the phase acquisition process of a 1st- τ2
F (∞) =
order loop with gain K = KoKd F (∞). τ1
log f
• For a PLL with with sinusoidal PD,
1
Lock-In Range = ∆ωL ≈ KoKd F (∞) = 2ζ ωn Lock-In Time = TL ≈
ωn

Frequency Acquisition — The Pull-In Process
ωi
The pull-in range, ∆ωP , is the

maximum initial frequency ωo ∆ω
offset for the pull-in process
to occur.
t
Tp
• For a 2nd-order PLL,

8 8
Pull-In Range = ∆ωP ≈ ζ ωnKoKd − ω2n ≈ ζ ωnKoKd if KoKd ωn
π π
2
∆ω
Pull-In Time = Tp ≈
2ζ ω3n

Aided Frequency Acquisition — Frequency Sweeping
Vi Phase Loop
Detector Filter
VFO
Lock Sweep
Detector Generator
• Use sweep to bring the VFO close to the frequency of locking.

Aided Frequency Acquisition — Loop Filter Switching
Low R
Vi Phase
Detector
High R
VFO Loop Filter
Lock
Detector
Low R if unlocked; High R if locked
• The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a wider
loop bandwidth is preferred.

Aided Frequency Acquisition — Dual Loops
Vi Phase LP
Detector Filter 1
VFO
Frequency LP
Detector Filter 2
• Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).
• The FLL should dominate during frequency acquisition.
• The PLL should dominant when the phase is locked.

Digital Phase-Locked Loops (DPLLs)
Loop Filter
Vd Vc
Vi PD F(s) Vo
VFO
1/N
Frequency Divider
To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.
ω ωoo Ko
ωo = ωoo + Ko · Vd ⇒ ω
o = = + · Vd = ω
oo + Ko
· Vd
N N N
ωoo Ko θo
ω
oo =
Ko =
θo =
N N N
• θi and θo are not available except during the rising and falling transitions.

XOR Phase Detector
u1
u1
Q u2
u2
Q
u1
Averaged Q
u2
Q
u1
θe u2
−π − π2 0 π π
2 Q
• The PD characteristic is strongly dependent on the duty-cycle of u1 and u2.

Edge-Triggered Set-Reset Phase Detector
u1
u1 S
Q u2
u2 R
Q
Averaged Q u1
u2
Q
u1
θe
−2π −π 0 π 2π u2
Q
Frequency Discrimination Capability
u1 u1
u2 u2
Q Q

Edge-Triggered Set-Reset Phase Detector
• The PD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.
• If f1 f2 or f1 f2, the PD has frequency discrimination capability, which can

improve frequency acquisition speed of the PLL.
• However, when f1 ≈ f2, the frequency-sensitive behavior is lost, and the PLL relys on
the pull-in process for frequency acquisition.

Sequential Phase-Frequency Detector (PFD)
u1
u1
1 D Q UP
u2
R
UP
R DN
1 D Q DN
u2 u1
u2
Averaged (UP-DW)
UP
DN
θe
−2π −π 0 π 2π

Sequential Phase-Frequency Detector (PFD)
• The PFD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.
• The PFD can discriminate the frequency difference for even the smallest f1 − f2.
• A PLL with the PFD can have infinite pull-in range. The frequency acquisition aid
provided by the PFD is akin to frequency sweeping.
• When using the PFD, a missing transition or an extra one in either u1 or u2 can cause
a large error signal to appear. The effects will propagate for more than one cycle.
Great caution is required to use the PFD in a noisy environment.

Charge-Pump Phase-Locked Loops
IP
PFD
Vi u1 UP Ie VFO
Vc
Vo
u2 DN
R
IP C
The “on” time of either UP or DN is tp = |θe|/ωi for each period 1/fi of the input signal.
The average error current Ie over a cycle is
tp θe 2π
Ie = IP × = IP × ωi = 2πfi =
Ti 2π Ti

The voltage Vc can be expressed as

1 IP 1
Vc(s) = Ie(s) R + = θe(s) × R+
sC 2π sC

Vc(s) IP 1
= Kd F (s) = R+
θe(s) 2π sC
The VFO has the following characteristic:
Ko
ωo = ωoo + Ko · Vc ⇔ fo = foo + Ko
· Vc Ko
=
2π
Using the continuous-time approximation, we have
2
θe(s) s θo(s)
= He(s) = = H(s) = 1 − He(s)
θi (s) s2 + 2ζ ωns + ω2n θi (s)
1/2

IP 1
1/2
ωn = Ko × ζ= K × (IP R) × (RC)
C 2 o

• The PLL behaves as a 2nd-order loop with active lag-lead filter.
• Discrete-time model can be used for more accurate analysis. Reference: Hein, z-
Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 1393–1400.
• During the pump interval tp, a voltage step of IP R occurs at the VFO input. This
granularity effect may be intolerable in some systems.
• The voltage step IP R may overload the VFO, making the previous linear analysis
invalid.
• The granularity effect can be mitigated with an additional capacitor Cp in parallel with
the earlier RC network, thus forming a 3rd-order PLL.
• Reference: Floyd Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun.,

Nov. 1980, pp. 1849–1858.

PFD and Charge-Pump Filter
IP1
u1
∆Vc
UP
1 D Q S1
R
Vc
θe
R
1 C Dead Zone
D Q S2
DN
u2
IP2
• The dead zone is caused by the slowness of the S1 and S2 switches.

PFD and Charge-Pump Filter
• When θe falls in the dead zone, the PFD’s conversion gain is decreased, causing a
reduction in ωn and ζ , and the degradation of θo phase noise.
• The dead zone can be eliminated by allowing UP and DN to be activated

simultaneously for a short time even if the phase difference is zero. Then, any
mismatch between IP 1 and IP 2 can cause a phase offset and consequently spurs
in the output spectrum.
• The finite output impedance of the IP 1 and IP 2 current sources can also cause phase
offset.
• Charge sharing in the S1 and S2 switches can also cause glitches at Vc.

PFD with Delayed Reset
u1
UP
Delay
DN
u2

Third-Order Charge-Pump PLLs
IP |L(j ω)| (dB)
UP Ie
Vc
ωt ωp
DN 0 ω
R1
C2 ωz
IP C1
The loop filter transfer function is

Vc(s) IP 1 1 IP sR1 C1 + 1
= Kd F (s) = R1 + = ×
θe(s) 2π sC1 sC2 2πs(C1 + C2) sR1 (C1 C2) + 1
1 1
ωz = ωp =
R1 C1 R1(C1C2)

Third-Order Charge-Pump PLLs
The loop gain of the 3-order PLL is
Ko KoIP s/ωz + 1
L(s) = × Kd F (s) = ×
s s (C1 + C2) s/ωp + 1
2
Let ωt /ωz = α > 1 and ωp/ωt = β > 1, then
KoIP C1
ωt ≈ = Ko
· IP R1 ·
(C1 + C2 )ωz C1 + C2
1 α 1
R1 =
· ωt C1 = Ko
IP · C2 = Ko
IP ·
KoIP ω2t β · ω2t
◦
• α = 4 and β = 4 gives a phase margin ≈ 60 .

Multi-Path Charge-Pump Filter
Ca
Ie1
Vc
Va
Vc Vb
Ie2
Va
Vb
Rb Cb ω
ωz ωt ωp
θe θe
Ie1 = IP 1 × Ie1 = IP 2 ×
2π 2π

Multi-Path Charge-Pump Filter
The loop filter transfer function is

sRb Cb + Ca ·
IP 2
+1
Vc(s) IP 1 1 IP 2 1 IP 1 IP 1
= Kd F (s) = · + Rb = ×
θe(s) 2π Ca 2π sCb 2πsCa sRb Cb + 1

1 IP 2 IP 2 1
= Rb Cb + Ca · ≈ RbCa · = RbCb
ωz IP 1 IP 1 ωp
The loop’s unity-gain frequency is
KoIP 1
ωt ≈ = Ko
· IP 2Rb
Caωz
• ωz , ωp, and ωt , can be set using smaller capacitors and resistors.
• Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800

Frequency Synthesizer, JSSC, 12/98, pp. 2054–2065.

Ch27 Phase-Locked Loops 1290

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Phase-Locked Loops

July 16, 2002

Ai = g1 (ωi t + θi ) Ao = g2 (ωot + θo) ωo = ωoo + Kc · Vc

• g1 and g2 are periodic functions with 2π period.

PLLs 27-2 Analog ICs; Jieh-Tsorng Wu

• Automatic frequency control.

• Frequency and phase demodulation.

• Data and clock recovery.

• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.

• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.

PLLs 27-3 Analog ICs; Jieh-Tsorng Wu

Vd = Kd (θi − θo) ωo = ωoo + Ko × Vc

Phase Filter VFO

When the PLL is locked,

Vd (s) = Kd · [θi (s) − θo(s)] = Kd θe(s) θe = θi − θo

PLLs 27-4 Analog ICs; Jieh-Tsorng Wu

System equations are

The transfer functions are

• H(s) is the closed-loop transfer function.

PLLs 27-5 Analog ICs; Jieh-Tsorng Wu

• ωn is the pole frequency of the loop.

• ζ is the damping factor. Qp = 1/(2ζ ) is the pole quality factor.

PLLs 27-6 Analog ICs; Jieh-Tsorng Wu

PLLs 27-7 Analog ICs; Jieh-Tsorng Wu

If KoKd τ2 1 in the passive filter, then

And the −3 dB bandwidth of H(s) is

• Usually choose ωn < ωi /10 to remove the high-frequency components at ωi , 2ωi ,

• The PD output’s high-frequency components can show up as spurious tones in the

PLLs 27-8 Analog ICs; Jieh-Tsorng Wu

PLLs 27-9 Analog ICs; Jieh-Tsorng Wu

Consider the following two-pole transfer function

• If ζ > 1, the system is overdamped, and both poles are real.

• If ζ = 1, the system is critically damped, and both poles are at −ωn .

Step Response = 1 − (1 + ωnt)e−ωnt ≈ 1 − e−ωnt/(2ζ ) if 4ζ 2 1

PLLs 27-10 Analog ICs; Jieh-Tsorng Wu

• If ζ < 1, the system is underdamped.

PLLs 27-11 Analog ICs; Jieh-Tsorng Wu

v(t) = s(t) + n(t) = Vs sin(2πfot) + n(t)

The phase jitter is 

PLLs 27-12 Analog ICs; Jieh-Tsorng Wu

• SNR is the signal-to-noise ratio, and can be expressed as

PLLs 27-13 Analog ICs; Jieh-Tsorng Wu

v(t) = Vs sin [2πfot + θn(t)]

PLLs 27-14 Analog ICs; Jieh-Tsorng Wu

PLLs 27-15 Analog ICs; Jieh-Tsorng Wu

θn,i nvc θn,vf o

Let θn,o be the phase noise in θo, we have

PLLs 27-16 Analog ICs; Jieh-Tsorng Wu

Consider only a white noise Sθn,i (f ) in θi ,

BL is the noise bandwidth of H(j 2πf ), i.e.,

For the 2nd-order PLL with active lag-lead filter

• BL,mi n occurs at ζ = 0.5.

• BL < 1.25BL,mi n for 0.25 < ζ < 1.0.

PLLs 27-17 Analog ICs; Jieh-Tsorng Wu

V1(t) = V1 sin(ωt + θ1) V2(t) = V2 cos(ωt + θ2)

PLLs 27-18 Analog ICs; Jieh-Tsorng Wu

• Kd is the phase-detector gain factor, and θe is the phase error.

PLLs 27-19 Analog ICs; Jieh-Tsorng Wu

From the final value theorem

• For a sinusoidal PD, the criterion becomes

For a 2nd-order PLL with active filter, F (0) → ∞, thus ∆ωH → ∞.

PLLs 27-20 Analog ICs; Jieh-Tsorng Wu

∆ωP O = 1.8ωn(ζ + 1) for 0.5 < ζ < 1.4

The phase jitter is

• If f1 f2 or f1 f2, the PD has frequency discrimination capability, which can