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1, FEBRUARY 2010
Abstract—A 64-kb subnanosecond Josephson–CMOS hybrid problem in superconducting digital technology, particularly
random-access memory (RAM) has been developed with ultra- for high-end computing applications. Some superconducting
fast hybrid interface circuits. The hybrid memory is designed memory systems were demonstrated using purely Josephson
and fabricated using a commercial 0.18-μm CMOS process and
NEC-SRL’s 2.5-kA/cm2 Nb process for Josephson circuits. The junction (JJ) technology, which, however, were both
millivolt-level Josephson signals are amplified to volt-level CMOS insufficiently dense and too small in capacity for high-end
digital signals by a hybrid interface amplifier, which is the most applications [2], [3].
challenging part of the memory system. The performance of this Josephson–CMOS hybrid RAMs have the potential to re-
amplifier is optimized by minimizing its parasitic capacitance move the memory bottleneck faced by JJ digital technology.
loading. The 4-K operation of short-channel CMOS devices and
circuits is reviewed, and a complete 4-K CMOS BSIM3 model, The basic idea is to use high-density CMOS memory and inter-
which has been verified by experiments, is discussed. The memory face it to high-speed ultralow-power superconductive devices.
bit-line output currents are detected by ultralow-power high-speed Fig. 1 shows the system block diagram. The memory core and
Josephson devices. Here, we report the first high-frequency access- decoders have been fabricated in a commercial CMOS technol-
time measurements on the full critical path showing 600 ps for a ogy; the current sensors are fabricated using standard Nb tech-
single bit. We discuss future designs made to reduce the crosstalk
and improve margins, as well as plans to reduce power dissipation nology, and the interface circuits involve both technologies. The
and latency. memory cell is modified from the traditional three-transistor
dynamic RAM (DRAM) cell, which works as a static memory
Index Terms—Access time, high-speed measurement, hybrid
memory, interface circuit. cell at 4 K due to nearly zero subthreshold leakage current.
This approach was proposed in 1993 [4], and some preliminary
I. I NTRODUCTION simulations and measurements that confirm its feasibility have
been reported [5], [6]. In this paper, high-frequency component
Fig. 1. Hybrid memory system of 64 kb for measuring delays including overall access time for a single cell.
our hybrid memory, current flows from the cell to a very low
impedance and ultralow-power high-speed Josephson current
sensor at the end of the bit line, which translates a current into
a millivolt pulse that goes to the processor.
The decoder for the 64-kb memory is an eight-input AND
gate circuit. In order to have minimum power consumption and
more robustness, the “static” CMOS logic family is chosen
[10]. The “logical effort” approach [10] has been used to
minimize the delay in the critical path. In addition, for mini-
mum delay, the decoder is designed such that the low-to-high
transition is faster than the high-to-low transition. Simulations
show a 400-ps total delay for the driver, decoder, memory cell,
and current sensor.
Fig. 2. 3-T memory cell. Upon accessing the cell, current will flow down the
III. I NPUT I NTERFACE A MPLIFIER
BL Read line if charge representing a “1” is stored at node X.
The most challenging part of this hybrid approach is the
input interface between the two logic families. In order to
5) Ring oscillator measurements indicate a logic speed in-
convert millivolt-level superconductor digital signals to volt-
crease of about 50%.
level CMOS digital signals with minimum delay and power
6) Static power is essentially eliminated, so the total power
dissipation, the hybrid interface amplifier shown in Fig. 3 was
dissipation is appreciably reduced.
implemented [11].
In order to simulate the 0.18-μm CMOS circuits used in this Part 1 of the interface amplifier is the so-called Suzuki stack
4-K experiment, we modified the room-temperature BSIM-3 [12], which has widely been studied for converting millivolt
model file according to our experimental data and verified it pulses to multi-millivolt signals [13]. Based on simulations, the
by measuring simple circuits, including ring oscillators. Several delay time is about 20 ps for a Suzuki stack with a 40-mV
important parameters (threshold voltage, average mobility, and output.
subthreshold swing) were extracted from the 4-K I–V curves. The operation of Part 2 of this hybrid amplifier is as follows:
By adjusting other parameters, the model was trimmed, so that When the clock is high, M1 is biased so that the current
the simulated I–V curves closely fit the measured ones. Then, in M1 , M2 , and the N -junction array is a little less than
the 4-K capacitances are measured and added to the model. the critical current in the N junctions, which is typically
In this paper, the so-called 3-T DRAM cell (Fig. 2) is chosen 0.8Ic . When the 40-mV input arrives at the gate of M1 , this
as the memory cell for its high density and because a nonde- n-channel MOS transistor acts like a voltage-controlled current
structive readout is desired. Upon readout in standard room- source, increasing the current by ΔiM 1 = vin gm , where gm
temperature operation, the voltage on the bit line is sensed to is the transconductance of M1 at the given bias point. Note
determine whether a “0” or a “1” is stored [10]. However, in that ΔiM1 must be much greater than the process variation of
16 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO. 1, FEBRUARY 2010
Fig. 3. Input interface amplifier. Part 1 is the so-called Suzuki stack with
16 junctions in each leg. It converts the 200-μA input pulse into a 40-mV pulse
that drives Part 2 of the amplifier. The junctions in both the Suzuki stack and
the 400-junction load array have critical currents of 400 μA.
critical currents in order to achieve robust switching and should Fig. 4. 5 mm × 5 mm Josephson chip. (The circuits in the center are for other
provide enough overdrive to switch the output stack at a high experiments.)
speed. When the current in the junctions exceeds the critical
current, all of the junctions switch, and the output voltage is
lowered by NVg by discharging capacitor C0 , which represents
all the parasitic capacitances at that node. In the present design,
N is 400 and gives a 1.1-V voltage drop. The M3 p-channel
MOS transistor is provided to speed up the resetting. When
the clock is low, M2 is off, and M3 is on, the output voltage
is charged up to VDD via M3 , and all N junctions return to
the zero-voltage state. When the clock is high again, all the
junctions are biased at 0.8Ic and are waiting for the next input.
The delay time of the Part 2 amplifier depends on the
discharging process of the output node that occurs when the
400-junction array goes into the voltage state, so the output-
to-ground capacitance is very critical. Several approaches
have been reported to decrease that parasitic capacitance [9],
[14]. Simulations using the currently employed 2.5-kA/cm2
Josephson technology and 0.25-μm CMOS process indicate a
delay of 170 ps with VDD = 1.5 V.
The stage following the interface amplifier is a CMOS in-
verter. The delay of the interface circuit also strongly depends
on the voltage level needed to trigger that inverter and can be re-
duced by lowering the VDD of the interface circuit. To minimize
capacitive loading, a minimum-size inverter is used. Due to the
sharp threshold characteristics and the larger threshold voltage, Fig. 5. 2.4 mm × 2.4 mm 64-kb CMOS memory chip. The gray cross strips
the initial inverter gate voltage can be as low as VDD − Vt are a requirement for the processing. The square surrounding the cross strips is
the boundary of the memory. The target memory cell is beneath those strips.
without compromising the output level. (The PMOS is still off
with an extremely small leakage current.) Given a 1.5-V VDD IV. H IGH -F REQUENCY M EASUREMENTS
of the CMOS digital circuits and 0.55-V threshold voltage, the
A. Test Setup
VDD of the interface amplifier can be as low as 1.0 V. We need
only 0.5-V voltage drop rather than 1.0-V voltage drop from The chips for the hybrid memory were fabricated using a
the interface amplifier to drive the following inverter. We have standard 0.18-μm CMOS process and NEC-SRL’s 2.5-kA/cm2
seen from simulation that the delay of the interface amplifier Nb Josephson process. The physical sizes are 5 mm × 5 mm for
can be reduced to less than 100 ps. The simulation results for the JJ chip shown in Fig. 4 and 2.4 mm × 2.4 mm for the CMOS
the complete critical path show that the total memory access chip shown in Fig. 5. In our previously reported measurements
time can be about 500 ps. [6], wire bonding was used to connect the Josephson and
FUJIWARA et al.: DELAY-TIME MEASUREMENT ON JOSEPHSON–CMOS HYBRID MEMORY WITH ACCESS TIME 17
Fig. 6. Circuit used for making delay measurements on various parts of the memory system. The arrays of four JJs are used to provide sharp rise time signals for
the oscilloscope. For example, the Suzuki stack and Part 2 comprise the input interface amplifier; when a clock signal (CLK1 ) is applied, current flows into the
OUT1 array and switches it. It also switches both parts of the interface amplifier and current flows into the OUT2 array, causing it to switch. With the oscilloscope
connected to OUT1 and OUT2 , the signals appear as in the sketch, and the delay can be measured. Other delays in the circuit can be measured in the same way,
including the overall delay, or access time.
with scaling, one can calculate that the hybrid memory ac- [9] Q. Liu, “Josephson-CMOS hybrid memories,” Ph.D. dissertation, Univ.
cess time for 90-nm CMOS will be 240 ps, whereas power California, Berkeley, Apr. 2007.
[10] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated
dissipation decreases only a little, because the interface static Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-
power dominates [17]. Furthermore, if a special low-voltage Hall, 2002.
4-K CMOS process becomes available, the power dissipation [11] U. S. Ghoshal, “Josephson-CMOS memories,” Ph.D. dissertation, Univ.
California, Berkeley, Jan. 1995.
can greatly be reduced. [12] H. Suzuki, A. Inoue, T. Imamura, and S. Hasuo, “A Josephson driver
to interface Josephson junctions to semiconductor transistors,” in IEDM
Tech. Dig., 1988, pp. 290–293.
VI. C ONCLUSION [13] M. Suzuki, M. Maezawa, H. Takato, H. Nakagawa, F. Hirayama,
S. Kiryu, M. Aoyagi, T. Sekigawa, and A. Shoji, “An interface circuit for a
The complete critical path of a 64-kb hybrid memory has Josephson–CMOS hybrid digital system,” IEEE Trans. Appl. Supercond.,
vol. 9, no. 2, pp. 3314–3317, Jun. 1999.
been measured for the first time; a 600-ps access time, as well [14] T. Van Duzer, Q. Liu, X. Meng, S. Whitely, and N. Yoshikawa, “High-
as the delay of components of the memory system, was shown. speed interface amplifiers for SFQ-to-CMOS signal conversion,” in ISEC
The measured delays are somewhat larger than simulated ones, Ext. Abstr., Sydney, Australia, Jul. 2003. Paper PMo35.
[15] R. E. Jewett and T. Van Duzer, “Low-probability punchthrough in
and the possible reasons and potential improvements were Josephson junctions,” IEEE Trans. Magn., vol. MAG-17, no. 1, pp. 599–
discussed. Future elimination of crosstalk and the correction 602, Jan. 1981.
of the small-margin problem were also discussed. With a [16] L. A. Abelson and G. L. Kerber, “Superconductor integrated circuit
fabrication technology,” Proc. IEEE, vol. 92, no. 10, pp. 1769–1771,
20-kA/cm2 process and a 90-nm CMOS process, the total Oct. 2004.
access time for a 64-kb hybrid memory will be about 240 ps, [17] Q. Liu, T. Van Duzer, K. Fujiwara, and N. Yoshikawa, “Hybrid
and power dissipation will be somewhat lower than that for the Josephson–CMOS memory in advanced technologies and larger sizes,”
J. Phys., Conf. Ser., vol. 43, pp. 1171–1174, 2006.
present design. The power dissipation can further be improved
if a special CMOS technology targeted at 4-K operation could
be used.
ACKNOWLEDGMENT Kan Fujiwara received the B.E., M.E., and Ph.D. degrees in electrical and
computer engineering from Yokohama National University, Yokohama, Japan,
The authors would like to thank the reviewers for their in 2000, 2002, and 2005, respectively.
careful reading and their insightful comments. Q. Liu would From 2005 to 2007, he was a Postdoctoral Researcher in the Department
like to thank J. Wieser and J. Zhang of NSC for their help of Electrical Engineering and Computer Sciences, University of California,
Berkeley, where he worked on the Josephson–CMOS hybrid random access
on the CMOS layout. K. Fujiwara would like to thank SRL re- memory project. From 2007 to 2008, he was a JSPS Research Fellow with
searchers Dr. M. Hidaka, Dr. Y. Hashimoto, Dr. Y. Kameda, and ISTEC-SRL. He is currently with SanDisk Limited, Yokkaichi, Japan, as a
Dr. T. Miyazaki, and all the people who worked in the Process Process Integration Engineer. His research interests include superconductive
devices and their applications, particularly memory circuits in digital systems.
Group at SRL for the Nb JJ foundry service and the generous
help in making the bump-bonded samples.
R EFERENCES
[1] K. K. Likharev and V. K. Semenov, “RSFQ logic/memory family: A new Qingguo Liu (S’03–M’07) received the B.S. and M.S. degrees from Nanjing
Josephson-junction technology for sub-terahertz-clock-frequency digi- University, Nanjing, China, in 1999 and 2002, respectively, and the Ph.D.
tal systems,” IEEE Trans. Appl. Supercond., vol. 1, no. 1, pp. 3–28, degree from the University of California, Berkeley, in 2007.
Mar. 1991. He is currently with NS Labs, National Semiconductor Corporation,
[2] S. Tahara, I. Ishida, Y. Ajisawa, and Y. Wada, “Experimental vortex tran- Santa Clara, CA. His research interests include superconductive electronics and
sitional nondestructive read-out Josephson memory cell,” J. Appl. Phys., CMOS circuits in power management for energy storage and conversion.
vol. 65, no. 2, pp. 851–856, Jan. 1989.
[3] S. Nagasawa, S. Tahara, H. Numata, and S. Tsuchida, “A miniaturized
vortex transitional memory cell for a Josephson high-speed RAM,” in
IEDM Tech. Dig., Dec. 1992, pp. 793–796.
[4] U. Ghoshal, H. Kroger, and T. Van Dnzer, “Superconductor-
semiconductor memories,” IEEE Trans. Appl. Supercond., vol. 3,
no. 1, pp. 2315–2318, Mar. 1993. Theodore Van Duzer (S’52–A’54–M’60–SM’75–F’77–LF’93) received the
[5] Q. Liu, T. Van Duzer, X. Meng, S. R. Whiteley, K. Fujiwara, T. Tomida, B.S. degree in electrical engineering from Rutgers University, New Brunswick,
K. Tokuda, and N. Yoshikawa, “Simulation and measurements on a NJ, in 1954, the M.S. degree in engineering from the University of California,
64-kbit hybrid Josephson–CMOS memory,” IEEE Trans. Appl. Los Angeles, in 1957, and the Ph.D. degree in electrical engineering from the
Supercond., vol. 15, no. 2, pp. 415–418, Jun. 2005. University of California, Berkeley, in 1960.
[6] Q. Liu, K. Fujiwara, X. Meng, S. R. Whiteley, T. Van Duzer, Since 1961, he has been with the Department of Electrical Engineering and
N. Yoshikawa, Y. Thakahashi, T. Hikida, and N. Kawai, “Latency and Computer Sciences, University of California, Berkeley, where he is currently an
power measurements on a 64-kb hybrid Josephson–CMOS memory,” Emeritus Professor. Since 1968, he has led a research group in superconductive
IEEE Trans. Appl. Supercond., vol. 17, no. 2, pp. 526–529, Jun. 2007. electronics, including both devices and circuits. He is a coauthor (with S. Ramo
[7] N. Yoshikawa, T. Tomida, K. Tokuda, Q. Liu, X. Meng, S. R. Whiteley, and J. R. Whinnery) of Fields and Waves in Communication Electronics and
and T. Van Duzer, “Characterization of 4 K CMOS devices and circuits a coauthor (with C. W. Turner) of Introduction to Superconductive Devices.
for hybrid Josephson–CMOS systems,” IEEE Trans. Appl. Supercond., His current research interests include hybrid superconductor/semiconductor
vol. 15, no. 2, pp. 267–271, Jun. 2005. 4-K random access memory.
[8] N. Kawai, Y. Takahashi, K. Gotoh, N. Yoshikawa, and T. Van Duzer, Prof. Van Duzer initiated and served as the founding Editor-in-Chief of the
“Characterization of 90 nm Cryo-CMOS devices and circuits for hy- IEEE T RANSACTIONS ON A PPLIED S UPERCONDUCTIVITY and as a Guest
brid Josephson–CMOS memories,” in ISEC Ext. Abstr., Washington, DC, Editor for several IEEE journal special issues. He is a member of the U.S.
Jun. 2007. Paper PB01. National Academy of Engineering.
20 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO. 1, FEBRUARY 2010
Xiaofan Meng received the B.S. and Ph.D. degrees (equivalent) from Peking Nobuyuki Yoshikawa (M’06) received the B.E., M.E., and Ph.D. degrees
University, Shenzhen, China, in 1962 and 1976, respectively, both in physics. in electrical and computer engineering from Yokohama National University,
He is currently a Senior Development Engineer in the Department of Elec- Yokohama, Japan, in 1984, 1986, and 1989, respectively.
trical Engineering and Computer Sciences, University of California, Berkeley Since 1989, he has been with the Department of Electrical and Computer
(UC Berkeley). Beginning in 1984, he was an Assistant and Associate Professor Engineering, Yokohama National University, where he is currently a Professor.
and then the Director of the Superconducting Electronics Group, Department His research interests include superconductive devices and their applications in
of Physics, Peking University. During 1987–1991, he was a Visiting Asso- digital and analog circuits, and single-electron-tunneling devices and quantum
ciate Professor in the Department of Electrical Engineering and Department computing devices.
of Physics, University of Virginia, Charlottesville. In 1991, he became a Prof. Yoshikawa is a member of the Institute of Electronics, Information and
Senior Visiting Scientist in the Department of Electrical Engineering and Communication Engineers of Japan, Japan Society of Applied Physics, Institute
Computer Sciences, UC Berkeley. He is also a Consultant to many high- of Electrical Engineers of Japan, and Institute of Electrical and Electronics
technology companies. He has extensive research experience in superconductor Engineers.
and semiconductor electronics, MEMS and other devices, and IC fabrication,
including thin-film deposition, photolithography, wet and dry etching, mate-
rial characterization, low-temperature technology, high and ultrahigh vacuum
technology, nanotechnology, and clean room fabrication. He is a coauthor
(with Y. X. Pan) of the book Brief History of Science and Technology in Ancient
China (Beijing, China: People’s Publishing House of China) and a co-translator
(with G.J. Cui) of the Chinese edition of Physics and Application of Josephson
Effect (Beijing, China: Metrology Publishing House of China) (A. Barone and
G. Paterno). He has more than 80 publications on superconductive electronics
and other fields. His current research interest is superconductor device and
circuit fabrication, including Josephson junctions, ICs, and superconductor
bolometer arrays.
Dr. Meng was the recipient of awards from Peking University, Peking
Commission of Science and Technology, and Chinese National Commission
of Science and Technology for superconductor device and low temperature
research; the Wel Zeilinger Staff Excellence Award; and Distinguished Service
Awards from the Department of Electrical Engineering and Computer Sciences,
UC Berkeley.