ANALYZING AND PREDICTING ELECTROCHEMICAL MIGRATION FAILURES ON

FIELD FAILURE RETURNS

Renee J. Michalkiewicz
Trace Laboratories, Inc.
Hunt Valley, MD, USA
rmichalkiewicz@tracelabs.com

ABSTRACT
Electrochemical Migration has been discovered on your
assembly after burn-in, or worse yet, on a product returned
from the field. A leakage current developed between two
isolated circuits and a short circuit occurred. You build IPC
Class 2, Dedicated Service Electronic, and Class 3, High
Performance Electronic, Products, so this type of failure is
of great concern to your company. You want to know if this
is an isolated incident or is your whole lot in danger of
failing in the field? This article outlines options that are
available to analyze this specific lot of assemblies and steps
that can be taken to prevent ECM failures on future lots.
IPC J-STD-001, Requirements for Soldered Electrical and
Electronic Assemblies 1 , is used as a guideline in preparing a
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customized test procedure. This article outlines exact

procedures that may be used to assess non-failed assemblies Photograph 1. Dendritic growth observed between parallel
for ECM potential. isolated circuits.

Case studies are included. The general procedure is as Electrochemical migration (ECM) failures can be difficult to
follows: Monitoring points connected to the area of concern isolate. Dendrites can form and disappear in a matter of
are isolated, often by removing components or cutting other minutes. These intermittent failures may cause disastrous
traces and wires are soldered. The assemblies are placed in outcomes. An intermittent short occurring on a printed
a temperature/humidity chamber and a bias is applied across circuit assembly (PCA) could cause a plane to crash or a
the suspect location. The resistance between these isolated heart/lung machine to stop.
points is monitored for sudden or slow drops that are
indicative of leakage current development or dendritic
growth. If ECM development is observed on these
assemblies from the same lot, the entire lot should be
considered at risk.

Key Words: Electrochemical Migration, ECM, Dendritic

Growth, Leakage Current, Field Failure

INTRODUCTION

Metal migration between isolated conductors on a

completed printed circuit assembly may produce electrical
shorts. Why does this growth occur and what do you need
to look for? Basically, we need to know if our assemblies
are “dirty.” By dirty, we mean littered with ions. Ions on
printed circuit assembly surfaces can cause short circuits. In If dendritic growth is suspected or observed on a field
simple terms, shorts occur when the space between the failure return, it is advisable to assess the risk of this failure
conductors is bridged by dendrites formed by re-deposited occurring on the remainder of the product in the field. The
metal ions (See Photograph 1). This metal migration is steps outlined below are not the “best” way to evaluate the
best described as a reverse plating of the conductors in the propensity of a process to develop leakage current because it
presence of ions, water and an electrical potential. 2
P is a reactive approach, but it can useful in estimating future
risk.
 • Monitoring points connected to the area of concern
are isolated, often by removing components or
cutting other traces and wires are soldered.
• The assemblies are placed in a contaminants are not washed away due to the low-
temperature/humidity chamber and a bias is
applied across the suspect location.
• The resistance between these isolated points is
monitored for sudden or slow drops that are
indicative of leakage current development or
dendritic growth.
• If ECM development is observed on these
assemblies from the same lot, the entire lot should
be considered at risk.
A better way of assessing risk of leakage current
development is through a preventive approach. The first
step in reducing the risk of ECM failure is purchasing
boards and components that are ionically “clean” and
choosing soldering pastes and fluxes that meet the
requirements of an international standard such as IPC J-
STD-004 3 and processing them correctly.
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The second step in reducing the risk of ECM failure is
assessing the assembly process. How likely is the
combination of products used in the assembly process to
develop leakage current in the field? Contract
Manufacturers (CM’s) and/or Original Equipment
Manufacturers (OEM’s) are tasked with the responsibility of
performing this risk assessment. One way to evaluate the
effectiveness of the assembly process is to recreate the exact
steps they use in their processes and assess the product via
an accelerated reliability test. Manufacturers may choose
to evaluate their process using a Surface Insulation
Resistance (SIR) test with temperature and humidity
because they want to simulate the exposure of their product
in the field. PCA’s are used in products that are exposed to
environments that range from cold and dry to hot and moist,
often fluctuating between the two.
Those companies on the forefront of product evaluation take
SIR testing a step beyond the routine. With the printed
circuit board industry moving to fine-pitched, low-
clearance, lead-free products, the risk for ECM failure is
ever increasing. Those companies in need of the most
reliable PCA possible (IPC Class 3 High Performance
Electronic Products) want to evaluate what effect these
assembly changes will have on long term performance.
REACTIVE APPROACH - TWO CASE STUDIES
Dendritic growth has been observed or leakage current is
suspected on a field failure return. Where should you start
with determining the cause of the failure? The most
common causes of leakage current development on printed
circuit assemblies are the following:
• Incoming printed circuit boards contained high
levels of surface ionic contaminants and the boards
were assembled using a no-clean process, hence
leaving the board contaminants in place
• Incoming components contained high levels of
surface ionic contaminants and the components
were assembled using a process that is cleaned, but
clearance nature of the components 4P
• Incoming components contain ionic contamination
which is not washed away for reasons listed above
• Unactivated flux remains on the board due to
improper reflow program, inadequate washing, or
sloppy rework process
• A combination of products is present on the
assembly that stimulates the development of
leakage current
Case Study Number 1
A small OEM purchased components from one of their
suppliers. Upon inspection, a contaminant was observed on
the leads of the device. Once the components were
soldered, the contaminant was still visible. The OEM was
concerned that the contaminant, if left in place, could
develop corrosion or leakage current. The component
supplier reworked the components to the best of their
ability, but there was still visible contamination present.
Because the contamination was observed prior to assembly,
the study could be isolated to address the component
problem alone. The footprint of the component was such
that it could be soldered to a standard SIR test board (See
Photograph 2). To best assess the potential for leakage
current, clean IPC-B-25 were supplied to the OEM and they
attached the components to the test boards using their
standard assembly procedures.
Please note that this analysis does not assess the interaction
that could occur between the PCB chemistry and the
component chemistry, but because the boards were not yet
assembled with the questionable components, scrap product
could be minimized by utilizing standard test boards for the
analysis. Additionally, in this case it is acceptable that the
suspect location on the component see the heat of assembly
as this is the process it will see prior to going out in the
field. In case study 2, the importance of not adding
additional heat following assembly will be addressed.
Photograph 2. Positioning of component on standard test
board used to assess leakage current development.
Because the boards were assembled using a no-clean
process, a standard test environment of 40°C and 93%RH 14.00

was chosen. Temperatures below 50°C should be used for 13.00

Resistance (Log Ohms)

no-clean low-solids soldering materials because the organic 12.00

acid portion of the paste/flux will sublimate above this 11.00

temperature. The test duration was 1008 hours. The bias 10.00
voltage which was applied was 50 volts Direct Current (DC) 9.00
with a measurement voltage also of 50 volts DC with the 8.00
same polarity as the bias voltage. When internal component 7.00
circuitry shorts the isolated circuits it must be removed from 6.00
the circuit either by cutting the leads or removing the

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internal circuitry.

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For the component assessment outlined above, the
insulation resistance of the isolated circuits was monitored
throughout the test. The data is presented below (see
Figures 1 and 2).
H
In
Figure 2. Graphic Representation of IR Values in Ohms
Exhibiting the Typical Bathtub-Shaped Curve with
Evidence of Leakage Current Development

A B C D E F The data above is indicative of leakage current development

Initial 12.81 12.68 12.60 12.45 12.42 12.37 in the areas that drop down in the 10 6 log ohm range. The
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24 Hour 7.93 7.77 7.99 7.84 8.09 7.97

48 Hour 8.24 8.16 8.26 8.19 8.35 8.27
typical bathtub curve was observed with IR values dropping
72 Hour 8.35 8.27 8.36 8.30 8.45 8.38 during the first 24 hours of testing but remaining relatively
96 Hour 8.42 8.34 8.42 8.38 8.51 8.45 consistent throughout the forty-two day exposure except for
120 Hour 8.47 8.39 8.47 8.42 8.55 8.49
144 Hour 8.52 8.43 8.52 8.47 8.60 8.54
the two points indicated. A drop of one decade or more in
168 Hour 8.54 8.45 6.54 8.50 8.62 8.56 resistance is indicative of leakage current development. A
192 Hour 8.56 8.48 6.57 8.52 8.64 8.58 visual examination of the boards post-exposure showed
216 Hour 8.58 8.50 8.59 8.55 8.66 8.60
240 Hour 8.60 8.52 8.61 8.57 8.68 8.62
carbonized debris which is indicative of a dendrite forming
264 Hour 8.61 8.53 8.62 8.58 8.69 8.63 and burning off. Following this test, the customer decided
288 Hour 8.62 8.54 8.63 8.59 8.70 8.64 that reworking the components was not an option and that
312 Hour 8.64 8.55 8.65 8.60 8.71 8.66
336 Hour 8.64 8.56 8.65 8.61 8.72 8.66 they would move to an alternate source.
360 Hour 8.65 8.57 8.66 8.62 8.73 8.66
384 Hour 8.65 8.58 8.66 8.62 8.74 8.67
408 Hour 8.66 8.59 8.67 8.63 8.74 8.68
Case Study Number 2
432 Hour 8.66 8.59 8.68 8.64 8.75 8.68 A more common issue presented to a laboratory for
456 Hour 8.66 8.59 8.67 8.64 8.74 8.68 assessment is the field failure return with a suspected
480 Hour 8.67 8.60 8.68 8.64 8.75 8.69
504 Hour 8.60 8.54 8.52 8.56 8.67 8.63
electromigration failure. Assemblies or boards from the
528 Hour 8.60 8.54 8.51 8.56 8.66 8.62 same lot will be required for the analysis. Please note that
552 Hour 8.58 8.51 8.48 8.59 8.63 8.62 this procedure is not an industry-recognized procedure. In
576 Hour 8.56 8.53 8.49 8.58 8.65 8.66
600 Hour 8.64 8.54 8.51 8.58 8.62 8.72
cases where no initial process validation was performed, an
624 Hour 8.64 8.60 8.53 8.60 8.71 8.74 ECM failure has been observed, and there is no time to use
648 Hour 8.67 8.62 8.55 8.64 8.69 8.75 standard process validation techniques, this method is the
672 Hour 8.66 8.67 8.53 8.68 8.69 8.74
696 Hour 8.69 8.67 8.55 8.69 8.72 6.74 only option aside from a full product recall in the case of
720 Hour 8.71 8.66 8.55 8.71 8.75 6.73 Class 2 or 3 high reliability product. The risk of not
744 Hour 8.77 8.68 8.55 8.81 8.72 8.80 recalling the product is the sole responsibility of the OEM at
768 Hour 8.76 8.65 8.52 8.71 8.76 8.79
792 Hour 8.80 8.75 8.51 8.89 8.72 8.78 this point, so a thorough risk assessment should be
816 Hour 8.84 8.73 8.62 8.76 8.75 6.82 performed by the company’s Technical Review Board
840 Hour 8.81 8.78 8.58 8.77 8.73 8.85
864 Hour 8.81 8.80 8.55 8.73 8.75 8.81
(TRB). In no way is the author guaranteeing reliability
888 Hour 8.77 8.77 8.51 8.73 8.74 8.81 based on the outcome of these procedures. A TRB’s
912 Hour 8.77 8.78 8.56 8.77 8.76 8.80 decision will vary depending on industry segment, the end
936 Hour 8.80 8.82 8.60 8.75 8.74 8.81
960 Hour 8.84 8.84 8.63 8.76 8.74 8.82
item requirements, the end-use environment, consequences
984 Hour 8.81 8.91 8.69 8.77 8.77 8.79 of failure and which aspect of reliability is being discussed.
1008 Hour 8.81 8.96 8.74 8.77 8.79 8.76 Acceptable risk for a cell phone may not be acceptable for
Final 12.32 12.14 12.26 12.30 12.31 12.31
an implantable medical device 5 . P P

Figure 1. Representative Insulation Resistance Values in

Log Ohms The devices pictured below were submitted because an
electrochemical migration failure on the lot was suspected.
See Photos 3 and 4.
 Large pads 3A and 3B and large pads 1A and 1B also
connect to their smaller counterparts. The samples were
wired accordingly and placed within the
temperature/humidity chamber. Initial ambient data was
collected, and in this case, the customer elected to run a
twenty-one day electromigration test at 65°C and 85%RH
with a 10 VDC bias and measurement voltage. The data is
outlined in Figure 3. Based on these electrical results and
visual observations, it does not appear that a substance on
the bare board in the suspect locations would have alone
induced an ECM-type failure.

96 Hour 500 Hour

Board Board
Test Point Result (ohms) Test Point Result (ohms)
ID ID
1 2.29E+09 1 7.76E+09
Panel 1 2 2.24E+09 Panel 1 2 9.12E+09
Board 1 3 1.95E+09 Board 1 3 6.03E+09
Photograph 3. Boards submitted for evaluation of ECM
potential. 1 3.55E+09 1 1.55E+10
Panel 1 2 2.57E+09 Panel 1 2 1.32E+10
Board 2 3 4.47E+09 Board 2 3 6.92E+09

Average Insulation Average Insulation

2.72E+09 9.19E+09
Resistance Resistance
Minimum Requirement 2.72E+08
Pass / Fail PASS
96 Hour 500 Hour
Board Board
Test Point Result (ohms) Test Point Result (ohms)
ID ID
1 2.40E+09 1 1.51E+10
Panel 2 2 3.16E+09 Panel 2 2 1.07E+10
Board 1 3 9.77E+08 Board 1 3 9.55E+09

1 4.37E+09 1 1.17E+10
Panel 2 2 1.48E+09 Panel 2 2 1.66E+10
Board 2 3 1.66E+09 Board 2 3 9.77E+09

Average Insulation Average Insulation

2.07E+09 1.20E+10
Resistance Resistance
Minimum Requirement 2.07E+08
Pass / Fail PASS

Photograph 4. Test sites identified.

Figure 3. ECM Data Collected for Case Study 2
In this case, the board supplier’s customer is questioning the
cleanliness of their incoming bare boards, so bare boards are
submitted for testing. The board supplier’s customer is Test Board Visual Observations
seeing intermittent shorts on product in the field. Panel 1 Board 1 No Anomalies Observed
Panel 1 Board 2 No Anomalies Observed
The first step in preparing a plan to assess ECM potential is
to identify the locations where potential ECM has occurred. Panel 2 Board 1 No Anomalies Observed
These sites should not be soldered to directly because the Panel 2 Board 2 No Anomalies Observed
heat presented during the solder step could very easily Figure 4. Visual Examination Results for Case Study 2
eliminate the contaminant causing the failure. Instead, the
artwork files should be used to track out to alternate sources Below, in Photographs 5 and 6, is another example of
for soldering that are away from the intended test site. production printed circuit assemblies being assessed through
Starting on the left in photo 4 above, large pad 2A runs applying temperature, humidity and bias to suspect test
internally to small pad 2A and large pad 2B runs to small sites. The sites that are soldered below lead to other
pad 2B. By soldering to large pads 2A and 2B, we will be locations on this small two inch by three inch assembly used
assessing the adjacent smaller pads, 2A and 2B. By in the implantable medical industry.
soldering to the larger pads, soldering heat is kept away
from the suspect location. Removal of components in order
to isolate to parallel circuits is often required. Removal of
components should be done by a mechanical means and
should not disturb the suspect location.

Photograph 5. Example of Fine Soldering Required to
Assess Products Such as Implantable Medical Products
Photograph 6. Dendritic Growth Observed Following
Temperature Humidity Exposure With Bias
REACTIVE APPROACH CONCLUSIONS
The reactive approach is not the optimum way to analyze
the potential threat of electrochemical migration and leakage
current which can lead to product short circuits. Because
this is not an industry-accepted method and all aspects of
the test are product specific, you cannot apply industry-
accepted pass/fail criteria. For example, although a decade
drop may not be observed during the test, results in the 10 7
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ohm range may not be acceptable based on the product
spacing and actual current application. The use of standard
test boards with established pass/fail criteria is a better
solution if you are in the position to take a preventive
approach and are not already reacting to a failure returned
from the field.
THE PREVENTIVE APPROACH
What does it mean to take a preventive approach when it
comes to assessing ECM potential? As was mentioned
above, the first step in reducing the risk of ECM failure is
purchasing boards and components that are ionically “clean”
and choosing soldering pastes and fluxes that meet the
requirements of an international standard such as IPC J-
STD-004 and processing them correctly. This will require a
bit of research and testing on the part of the CM or OEM.
If you choose soldering products that are purchased from
reputable companies that are able to provide you actual data
as it relates to meeting the J-STD-004 requirements, than
process validation need only be performed. Please note that
there are paste and flux manufacturers that will advertise
their products meet the requirements of this or other
international standards, but 10 years or more may have
elapsed since the product was actually tested. As one can
imagine, although it may be unintentional, raw materials
and formulae will change over the years, so ongoing
confirmation that the material is still classified as the same
reactivity level is imperative.
The same holds true for the board and component suppliers.
If only low level contamination is acceptable in your
process due to tight spacing, low tolerances and need for
high reliability, then these requirements should be spelled
out on purchasing documents AND they should be
periodically confirmed on incoming inspection. Although it
is true that requirements specified on purchasing documents
are binding and legal recourse could be taken if a
cleanliness problem is discovered, product will already be in
the field and a recall situation will be required. This
expense would be much greater than the cost of initially
confirming that the assembly process is under tight control.
The way to keep the assembly process under control as it
relates to cleanliness will be discussed below.
ASSESSING CLEANLINESS OF THE ASSEMBLY
PROCESS
IPC J-STD-001D, Appendix C 6 contains information
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regarding assessing cleanliness of the assembly process as
well as compatibility of the materials used within the
process. This is assessed through a required Surface
Insulation Resistance (SIR) test and optional ionic tests,
Resistivity of Solvent Extract (ROSE) and Ion
Chromatography (IC).
The current SIR recommended test vehicle is the IPC-B-36
board pictured in photograph 6 without components and in
picture 7 with components.
Photograph 7. IPC-B-36 Board Prior to Assembly
Photograph 8. IPC-B-36 Assembly With Dummy
Components
There are ten test sites on this board (see Figure 5). Four of
these are comb patterns, M1, M3, M5 and M8. The fingers
of the comb patterns run perpendicularly to each other, so
that entrapment of residues may be better assessed (i.e., the
direction of the flow of cleaning, if cleaning takes place,
will more easily rinse residues from one pattern versus the
other). The spacing of the comb pattern is .0065 inches.
Test points M2 and M4 are daisy-chained pads. Every other
pad is connected so that on patterns C and D below, the spot
between every pad is being assessed. Dummy components,
those with the circuitry removed, are applied to the test
board and soldered to these pads. 68PLCC’s (plastic
leadless chip carriers) are typically used for this test.
Test points M6, M7, M9 and M10 are perimeter patterns.
They are not covered by the components and lie uncovered
around the periphery of the component area. Because these
areas are not covered, they are the easiest to clean.
Figure 5. Illustration Showing the Ten Test Points of the
IPC-B-36 Board
Best Cleaning/Process Assessment
The most effective way to assess the “cleaning” process is
to have your printed circuit board supplier manufacture the
test boards using the same laminate, solder mask and plating
chemistry that is typically used on your supplied product.
The boards would then be assembled using the standard
profiles that are used in your assembly process. This should
also include the addition of any rework materials that may
be used in the process of manufacturing the product. This is
the most effective way to assess the “cleaning” process.
“Cleaning” is in quotations because this test procedure can
be used to assess no-clean processes, as well. Trapped
unreacted no-clean flux can as easily cause ECM as a non-
rinsed aqueous-cleaned product.
Ten assemblies are prepared by the CM/OEM and submitted
for testing. The boards are wired, placed in a
temperature/humidity chamber for 168 hours and monitored
for the development of leakage current. If the boards are
not conformally coated a static environment is used. If the
boards are conformally coated, they may be tested in a
condensing environment to confirm the effective
functioning of the coating.
Each “type” of cleaning challenge is assessed, the comb
patterns, the pads and the periphery patterns. Based on the
results, adjustments may be made to the assembly process
and the test repeated. The test is repeated until satisfactory
results are obtained. This test may then be repeated
periodically to confirm that the assembly process is still in
control.
Assessing Cleaning Only
Often, the time and expense is too great or the risk low
enough that a CM/OEM will decide to test their process
only. In this case, standard FR4 boards with bare copper are
used. These boards are cleaned prior to testing and then
processed as usual. In this case, the board production
chemistry and its interaction with the assembly process
chemicals are not being assessed.
IPC J-STD-001 UNDER REVISION
The current J-STD-001 Appendix C is currently under
revision. It has been recognized that a single component
style does not represent everyone’s process. Often the 0.004
inch standoff is much more of a challenge for those trying to
utilize this method than is typical of their assembly process.
Bent leads and/or solder mask bumps are one way to adjust
the IPC-B-36 design to give a larger standoff. Additionally,
J-STD-001 does not specify that an assembler must use the
standard board test board. They have the option of
designing their own and proving the design an effective
indicator, but is obvious that there is additional expense
when using this option.
There is a new test board that is being analyzed. It is called
the IPC-B-52 board (see Photograph 8). This test board
includes the following locations that have been specifically
designed for SIR testing 7 :
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•
Horizontal Connector
• 0402 Capacitor Field
•
SM IEEE1386 Connector
• 0805 Cap Fields
• Ball Grid Array (BGA)
• Quad Flat Pack (QFP) 160
• QFP80
• 0603 Cap Field
• SOIC16 (U4-U7)
• 1206 Cap Field
• Vertical Connector (J1)
Photograph 9. IPC-B-52 Board
With all the options listed above as it relates to tests sites
available, one can see how beneficial this standard test
board will be. Studies are currently underway to establish
pass/fail criteria for this new test board which will be
incorporated in to the newest revision of J-STD-001.
FUTURE WORK
Future work will focus on forming an IPC task group to
determine if a guideline document can be developed to
assist CM’s and OEM’s who are in a reactive position. This
document would require additional research and round
robins to establish a suggested test protocol.
ACKNOWLEDGEMENTS
This author would like to acknowledge Debora Obitz,
Elizabeth Allison and Michael Allison of Trace Laboratories
- MD for their work in providing the data and photographs
and the real-time dendritic growth video that will be shown
during the presentation of this paper.
Originally published in the proceedings of the Pan Pacific
Microelectronics Symposium Kauai, Hawaii, February
2008.
REFERENCES
[1] IPC/ANSI J-STD-001D, Requirements for Soldered
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Electrical and Electronic Assemblies , February 2005.
U
[2] Electrochemical Migration: Electrochemically Induced
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Failures in Printed Wiring Boards and Assemblies: IPC-TR-
476A , 1984, Northbrook, IL, IPC.
U
[3] IPC/ANSI J-STD-004, Requirements for Soldering
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Fluxes , January 2004.
U
[4] T. Munson, “Component Cleanliness in a No-Clean
World”, Circuits Assembly , March 2003, pp. 58.
U U
[5] D. Pauls, C. Slack, “Process Qualification Using the
IPC-B-52 Standard Test Assembly”, Presented at IPC
Printed Circuits Expo®, APEX® and the Designers Summit
2006.
[6] IPC/ANSI J-STD-001D, Requirements for Soldered
U
Electrical and Electronic Assemblies , February 2005,
U
Appendix C.
[7] D. Pauls, C. Slack, “Process Qualification Using the
IPC-B-52 Standard Test Assembly”, Presented at IPC
Printed Circuits Expo®, APEX® and the Designers Summit
2006.