International Journal of Management, Technology And Engineering ISSN NO : 2249-7455

Design and Implementation of FIR Filter using FPGA

R. Srikala madhuri ¹ , B. Usha rani 1 , K. Harika 1, J. Sunil Kumar 2

1.Department of Electronics and Communication Engineering , Vignan Institute of Management

and Technology for Women , E-mail: srikalamadhuri@gmail.com, bonuga.ushareddy@gmail.com,
korivi.harika@gmail.com
2. Department of Electronics and Communication Engineering, Assistant professor, Vignan
Institute of Management and Technology for Women, E-mail: sunil5718@gmail.com

ABSTRACT
FIR filter (Finite impulse response) - The
finite impulse response filter is the most basic
components in digital signal processing
systems and are widely used in
communications , image processing and
pattern recognition. Based on FPGA (editable
logic device ). In Digital signal processing,
Filter is used almost in all devices. Filters are
used to extract the useful part from the input
signal and the required part of the signal is
reached to the receiver. For linear
characteristics devices, FIR filter is used
which is nothing but a combination of
multiplier and adder[1]. In this project, FIR
filter has been designed by using Vedic
multiplier and CLA adder. Combination of
Vedic multiplier and Carry look ahead adder
makes FIR filter faster. RTL synthesis has
been done by using Xilinx 14.7 and
simulation is done by using Xilinx I sim. In
this work we compare the Finite impulse
response filter with MAC unit consisting of
Vedic multiplier with FIR filter with adder.
By the proposed work of FIR filter with MAC
unit we can get effective results in terms of
Area, Delay and Power consumption aspects.
Keywords—Vedic multiplier; carry look ahead
adder; MAC unit; FIR Filter;
from source to destination it lost some
information due to the presence of noise in the
channel. This information should be retained in
its original form by the signal until it reaches to
the destination so that there is a complete
information transfer without any loss in signal.
A signal has high frequency range, low
frequency range and mid frequency range.
Sometime useful information is contained by
using only high frequencies or low frequencies
or mid frequencies range. This useful
information is extracted by filters. These filters
are different for analog and digital signals. For
DSP applications we use digital filters. FIR filter
is a type of digital filter which is used for linear
characteristics applications. Various types of
techniques have been proposed for the designing
of FIR filter. Designing of FIR filter by using
MAC[2] unit is easy as compare to window
techniques.
MAC unit is multiplier accumulation unit. It
comprises of multiplier and adder. To make FIR
filter faster a multiplier and an adder, selected
for MAC unit should be faster. A reconfigurable
booth multiplier has been selected which is a
high speed multiplier. Carry Look Ahead adder
is used for the purpose of final addition. This
combination has made the device faster.
II. Literature Survey:

I. INTRODUCTION Multipliers are extensively used in

Digital signal processing is an important part
of electronic devices whereas a signal is an
integral part of DSP. A signal is information
which we want to transfer from source to
destination through a medium called channel.
When any signal containing information travels
Microprocessors, DSP and Communication
applications. For higher order Multiplications, a
huge number of adders are to be used to perform
the partial product addition. The need of low
power and high speed Multiplier is increasing as
the need of high speed processors are increasing.

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International Journal of Management, Technology And Engineering
The Vedic multiplication technique is based on
16 Vedic sutras or aphorisms, which are actually
word formulae describing natural ways of
solving a whole range of mathematical problems.
The mathematical operations using, [3]Vedic
Method are very fast and requires less hardware,
this can be used to improve the computational
speed of processors. This paper describes the
design and implementation of 4x4 bit Vedic
multiplier based on Urdhva- Tiryakbhyam sutra
(Vertically and Crosswise technique) of Vedic
Mathematics. The use of Vedic mathematics lies
in the fact that it reduces the typical calculations
in conventional mathematics to very simple ones.
This is so because the Vedic formulae are
claimed to be based on the natural principles on
which the human mind works. Vedic
Mathematics is a methodology of arithmetic
rules that allow more efficient speed
implementation. It also provides some effective
algorithms which can be applied to various
branches of engineering such as computing.
III. IMPLEMENTATION OF PROPOSED
MAC UNIT:
Proposed MAC unit is a combination of Vedic
multiplier and Carry Look Ahead Adder. Vedic
multiplier has been described in subsection A
and complete MAC unit which is proposed has
been described in subsection B.
A. Vedic multiplier.
In multiplier, Carry Look-ahead helps in
improving the speed of addition operation.
Using this algorithm(Vedic multiplier – UT
Sutra), the carry bits for the successive stages
can be calculated in advance depending on the
input signals. CLA calculates the next carry by
exploiting the fact that the carry generated at
any bit-position depends on the three inputs to
that position[4].
Pi=Xi XOR Yi (Carry Propagation), Gi=Xi
AND Yi (Carry Generation), Si=Xi XOR Yi
XOR Ci (Sum Generation) and Ci+1=Gi OR (Pi
AND Ci) (Next Carry)
B. Carry look ahead adder.
Carry-lookahead adder (CLA) or fast adder is a
type of adder used digital logic. A carry-look
ahead adder improves speed by reducing the
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ISSN NO : 2249-7455
amount of time required to determine carry bits.
It can be contrasted with the simpler, but usually
slower, ripple-carry-adder (RCA)[5], for which
the carry bit is calculated alongside the sum bit,
and each stage must wait until the previous carry
bit has been calculated to begin calculating its
own sum bit and carry bit. The carry-lookahead
adder calculates one or more carry bits before
the sum, which reduces the wait time to
calculate the result of the larger-value bits of the
adder.
C. Finite Impulse Response (FIR) Filter.
The filter in which impulse response is of finite
duration is defined as Finite Impulse Response.
FIR filters can be designed with different
methods. The objective of FIR filter is to
produce ideal results2,3. The transfer function of
FIR filter is when the order of the filter increases
the complexity and amount needed for
processing the input is also increased. The
function of an FIR filter is to accept the input
signal and blocking specific frequency and
passing the real signal minus those components
to the output side. Where FIR is a digital filter
the filter operates on the digital input and
provides the digital output.
FIR Filter Design
The FIR filter are generally designed using basic
building blocks such as multiplier, adders and
the series number of delays. Figure 1 shows
the general FIR filter of length N. The delays
considered in the filter operate on the input data.
The Coefficient value added to the filter is used
for multiplication.
Figure 1. Conventional FIR filter.
Y[n] = ∑ x[n-k]* h[n]
For 8 bit computation again product is 32 bit.
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International Journal of Management, Technology And Engineering
We have to extract the part from 24th to 9th bit.
This is the useful part and we get the 16 bit
output result of FIR filter. Fig 2 shows a flow
chart in which we have shown reconfigurable
Booth multiplier with the concept of
configuration register. For 16 bit input
configuration register will be high for MSB bit
that is 100 and no part of the product will be
extracted.
D. Proposed MAC unit Proposed.
MAC unit is designed as shown in fig 2. As
shown in figure first of all two inputs to the
MAC unit get multiplied by using Vedic
multiplier and then the multiplication result is
get added to the previous stored result of
MAC unit. This can be understood with the
following example: an input ai has been taken
which is constant throughout the computation
another input bi which is FIR filter coefficient.
These two inputs get multiplied by using
reconfigurable booth multiplier and then the
result is feed to the Carry Look Ahead Adder.
There is another variable ain. Initially ain is
set to the zero and it works as second input to
the adder. In next cycle, ain is now previous
output of MAC unit. Hence a register is used
in main programming to store the previous
result which works as second input to the
adder in each next cycle.
Vedic Multiplier
Fig.2. Architecture of proposed MAC unit
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ISSN NO : 2249-7455
IV.SIMULATION & RESULT
ANALYSIS
A. SIMULATION
Write and invoke code for submodules using
Verilog HDL language and then write the Top
level module code to connect all submodules.
According to the FIR filter block diagram use
Verilog HDL description to compile and then
use XILINX ISE14.7 software simulation.
Finally we need a top level module to connect
all submodules. It is important to note that the
process of writing the top level module to
submodules connection ports one by one
mapping is correct therefore the neutron
module variable name the program code needs
to be distinguished and cannot be confused.
After completing the Verilog HDL code for all
modules and top level module , you will still
need the top level modules motivation test file,
which gives you input incentives so that you
can simulate it. Finally completed Verilog
HDL test bench preparation , After simulation
the code to be dumped into the 32 BIT FPGA
for hardware implementation.
B. ANALYSIS
In figure 3 we can see the corresponding
waveforms of each signal of 16 BIT FIR filter,
where temp1, temp2 are the required filter
inputs as multiplied and added corresponding
inputs as(x1*h1) simultaneously as past
output is accumulated with present outputs.
In figure 4 represents the instantiation of 16
BIT FILTER as a 32 BIT FIR filter output.
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International Journal of Management, Technology And Engineering ISSN NO : 2249-7455

is high speed unit which makes FIR filter

faster.

REFERENCES
[1] Santosh B., B.M., Chirag S., “FPGA
implementation of efficient FIR filter with
quantized fixed point coefficients” IEEE
international conference on emerging
trend in communication, pp. 1-6, 2013
[2] M Sai Kumar, D. Ashok Kumar, P.S.,
“Design and performance analysis of
multiply accumulate MAC unit”, IEEE
International Conference on Circuit,
Power and Computing Technologies, pp.
Figure 3 : Simulation waveform of 16-bit FIR
1084- 1089, 2014
Filter
[3] Swee. K.L.S., Lo Hai Hiung,
“Performance comparison review of
32-bit multiplier designs”, IEEE
international conference on intelligent and
advanced systems, vol. 2, pp. 836-841,
June 2012
[4] Andrew D. Booth, “A signed binary
multiplication technique”, quart. Journal
Mech. and applied math., vol. 4, pt. 2, pp.
236-240, 1950
[5] B. Rashidi, B. Rashidi, M.
Pourormazd, “Design and implementation
of low power digital FIR filter based on
low power multipliers and adders on
Xilinx FPGA”, IEEE international
Figure 4 : Simulation waveform of 32-bit FIR conference on electronics computer
Filter tecnology, vol. 2, pp. 18-22, 2011
[6] Mohamed Aly and Ahmed Sayed, “A
study of signed multipliers on FPGAs”,
IEEE international conference on
electronic design, systems and application,
pp. 33-38, 2012
V. CONCLUSION:

A FIR filter has been designed by using Vedic

multiplier, which is working on the concept of
crosswise multiplication. Proposed FIR filter
has been designed by using behavioral
modeling. Synthesis of proposed work has
been done successfully. Proposed MAC unit
can work for n number of bits. For this project,
synthesis has been done for 32- bit. MAC unit

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