Biatris Patino

Homework #4

1. Describe the difference between CISC and RISC architectures and compare the two
architectures based on:
- The number of machine instructions generated by a compiler from a high-level
program
- The number of microinstructions per machine code
- CPI
- Clock.
- List at least two microprocessors implementations that are from each architecture
type.
CISC RISC
The number of Large number of instructions Small number of fixed length
machine instructions instruction
generated by a
compiler from a high-
level program

The number of Varies 32 bits=word

microinstructions per
machine code

CPI Several instructions can take several Single-cycle instructions

clock cycles
Clock Slower Faster
List at least two IBM 370/168 Alpha
microprocessors Intel 80486 AVER
implementations that VAX 11/780 Power Architecture
are from each
architecture type.

1. Problem 2.14 Provide the instruction type, assembly language instruction, and
binary representation of instruction described by the following RISC-V fields:

opcode=0x33, funct3=0x0, funct7=0x20, rs2=5, rs1=7, rd=6

R-Format
Func7 Rs2 Rs1 Funct3 Rd Opcode
0010100 00101 00111 000 00110 0110011
 Binary: 001010000101001110000011001100112

Hex: 2853833316

Decimal: 67656171510

add x6, x7, x5

2. Problem 2.15 Provide the instruction type, assembly language instruction, and
binary representation of instruction described by the following RISC-V fields :

opcode=0x3, funct3=0x3, rs1=27, rd=3, imm=0x4

I-Format
Imm[11:0] Rs1 Funct3 Rd Opcode
000000000100 11011 011 00011 0000011

Binary: 000000000100110110110001100000112

Hex: 4DB18316

Decimal: 509171510

ld x3, 27(x3)

3. Problem 2.16 Assume that we would like to expand the RISC-V register file to
128 registers and expand the instruction set to contain four times as many
instructions.

a) How would this affect the size of each of the bit fields in the R-type
instructions?

Expanding the register file to 128 bits adds 2 bits to rs , rt, rd. It will increase
them to 7 bits each. The instruction expands by 2 bits – 8 bits total. And the
opcode reserves the values that could accommodate this without expansion.

b) How would this affect the size of each of the bit fields in the I-type
instructions?

2 bits each are added to rs,rt and the opcode

 c) How could each of the two proposed changes decrease the size of a RISC-V
assembly program? On the other hand, how could the proposed change
increase the size of an RISC-V assembly program?

by reducing the instances in which the register contents “spill” into other
registers/ memory and by allowing more complex operations to be
implemented in one instruction vs requiring multiple instructions. They
could increase the size of a program by requiring adding bits to the opcode
and register fields, there by increasing memory width.

4. Problem 2.18 Find the shortest sequence of RISC-V instructions that extracts bits
16 down to 11 from register x5 and uses the value of this field to replace bits 31
down to 26 in register x6 without changing the other bits of registers x5 or x6.
(Be sure to test your code using x5 = 0 and x6 = 0xffffffffffffffff.
Doing so may reveal a common oversight.)

Addi x7, x0, 0x3f //bit mask for bits 16 to 11

Slli x7, x7, 11 //shift

And x28, x5, x7 //apply mask to x5

Slli x7, x6, 15 //shift mask to cover bits 31 to 26

Xori x7, x7, -1

And x6, x6, x7

Slli x28, x28, 15 //move x5 into position 31 to 36

Or x6, x6, x28 //load bits 31 to 26 from x28

5. Problem 2.24 Consider the following RISC-V loop:

LOOP: beqx6, x0, DONE

addi x6, x6, -1

 addi x5, x5, 2

jalx0, LOOP

DONE:

a) Assume that the register x6 is initialized to the value 10. What is the final
value in register x5 assuming the x5 is initially zero?

X5=20

b) For the loop above, write the equivalent C code. Assume that the registers x5
and x6 are integers acc and i, respectively.

acc=0;

i=10;

while(i!=0)

acc+=2;

i - - j

c) For the loop written in RISC-V assembly above, assume that the register x6
is initialized to the value N. How many RISC-V instructions are executed?

4N + 1 Instructions

d) For the loop written in RISC-V assembly above, replace the instruction “beq
x6, x0, DONE” with the instruction “blt x6, x0, DONE” and write the
equivalent C code.

change condition: ! = to >= in the while loop

acc=0;

i=10;
 while (i>=0)

acc + = 2

i - - j

6. Problem 2.27 Translate the following loop into C. Assume that the C-level integer
i is held in register x5,x6 holds the C-level integer called result, and x10
holds the base address of the integer

MemArray.

addi x6, x0, 0

addi x29, x0, 100

LOOP: ldx7, 0(x10)

addx5, x5, x7

addi x10, x10, 8

addi x6, x6, 1

bltx6, x29, LOOP

7. Problem 2.29 Implement the following C code in RISC-V assembly. Hint:

Remember that the stack pointer must remain aligned on a multiple of 16.

int fib(int n){

if (n==0)
return 0;
else if (n == 1)
return 1;
else
 return fib(n−1) + fib(n−2);
}
______________________________________________

__start:

li A0,10
j loop
mov A0,V0
li V0,2
syscall
la A0,11
syscall

Loop: sub sp, sp, 16

sw A0,0(sp)
sw S0, 16(sp)
sw RA,32(sp)
bgt A0,1,NOT1
mov V0,A0
b ret

NOT1:sub A0,A0,1
j loop
mov s0,v0
sub a0,a0,1
j loop
add v0,v0,s0

RET: lw a0, 0(sp)

lw s0,16(sp)
lw ra,32(sp)
add sp,sp,16
jr ra
.data