A STUDY AND REVIEW OF SWITCHING
switching devices turn-on and turn-off controls are
LOSSES IN METAL OXIDE SEMICONDUCTOR
the key concern when it works with the parasitic
Kamal Singh
Associate Professorinductors generated by the PCB layout and the
Department of Electricaldevice
Institute of Engineering & Technology Lucknow
kamalsingh32@gmail.com
Abstract: In this paper a study and review of switching
losses in metal oxide semiconductor field effect
transistor is presented. The objective of this paper is to
bring awareness of the switching losses under the
influence of a variety of factors such as load current,
switching speed etc. It is very essential to understand
the switching losses and their impact on the system
under operating conditions. The different types of
switching losses models are presented in this paper for
MOSFET in which different methodologies for analysis
of power switching losses are evaluated. The switching
losses can be minimised by separating the source
connection between the power path and the driver path
of MOSFET. Thus, the paper provides helpful study of
switching losses in in MOSFET.
Keywords- Dc-dc converter, SEPIC converter, Power
Semiconductor Devices.
I. INTRODUCTION
The power MOSFET is one of two predominately
used, fully controlled semiconductor devices in
power electronics. As such, it's modeling is of prime
importance for the construction of any power
electronic converter. Obtaining a reliable and
accurate result for their losses during conduction and
switching is an important step in the goal for
performance evaluation of a given circuit. High
efficiency becomes a necessary requirement in
switching mode power supply (SMPS) design. To
achieve this requirement, a lot of power
semiconductor researchers developed
fast switching devices i.e., the parasitic capacitance
of the devices are minimized, with the low
conduction channel resistance to save both switching
losses and conduction loss.
These fast switching devices trigger switching
transient overshoot. It creates critical SMPS design
issue on the PCB layout, and the gate signal
oscillation. To overcome switching transient
overshoot, designers usually slows down devices
switching speed by increasing the gate resistor value
with appropriate snubber circuit for damping
overshoot, but it will suffer relatively high switching
losses. There always is a tradeoff between the
efficiency and the ease of use for the fast switching
devices in standard through hole package. The fast
package. Especially, the package source
Engineering
parasitic inductors are the critical factor on the
devices control. Fast switching MOSFET separates
the source connection into two current paths: one for
a power connection and another for the driver
connection. It allows the device keeping the
switching speed without sacrificing the turn-on and
turn-off controls ability [1, 8]. Megawatt power
applications require efficient and high power-density
converters that are capable of operating at elevated
temperatures. The performance of Si-based power
transistors is limited due to low junction operating
temperatures and low blocking voltage. With the
improved performance available from wide band-gap
semiconductor materials such as SiC, devices
composed of such materials will make the present
power converter constraints less of a burden. SiC
switching devices have been studied and developed
in the power electronics industry throughout the last
decade.
Some commercial power supplies using SiC
diodes are already available in the market[2, 10-11].
Electronic power processing technology has evolved
around two fundamentally different circuit schemes:
duty cycle modulation, commonly known as Pulse
Width Modulation (PWM), and resonance. The PWM
technique processes power by interrupting the power
flow and controlling the duty cycle, thus, resulting in
pulsating current and voltage waveforms. The
resonant technique processes power in a sinusoidal
form. Due to circuit simplicity and ease of control,
the PWM technique has been used predominantly in
today's power electronics industries, particularly, in
low-power power supply applications, and is quickly
becoming a mature technology. Resonant technology,
although well established in high-power SCR motor
drives and uninterrupted power supplies, has not been
widely used in low-power dc/dc converter
applications due to its circuit complexity[3-4].
The switching loss of power MOSFETs becomes
a dominant factor in the total power loss of power
electronics converters when the switching frequency
is increased to improve dynamic performance and
reduce size. A simple yet reasonably accurate method
of estimating power MOSFET switching losses using
device datasheet information is highly desirable for
predicting maximum junction temperatures and
overall power converter efficiencies. However, the
complex switching behavior and switching losses of a
power MOSFET are difficult to model analytically
due to the nonlinear characteristics of MOSFET
parasitic capacitances [5-7, 9]. An accurate power
loss model can enable converter designers to make
fast calculations, compare between different
semiconductors, and size the heat sink properly. As
the switching frequency is increased to improve the
converter performance, the switching losses of power
MOSFETs becomes a dominant factor in the total
power losses. Traditional loss models treat the
switching waveforms as piecewise linear, providing a
simple and fast calculation based on datasheet
information. However, it does not account for the
parasitic inductances and nonlinear characteristics of
the parasitic capacitors which significantly affect the
switching process in practice. Many detailed
analytical models that considering such parasitics
have been proposed[12-14].
II. POWER MOSFET BEHAVIORIAL MODEL
In this section, the different behavioural models of
power MOSFET are shown which are as follows:
Fig. 1(a-e) Power MOSFET behavioural model
The operation of the MOSFET turn-off transient will
be described step by step. The operation of an ideal
MOSFET in the hard switching turn-off transient is
shown in Fig. 2. The different stages of operation are
as follows:
Stage 1:
Operation begins after a turn-off signal providing
from the driver and the MOSFET capacitor between
gate to source, Cgs, will start to discharge. During
this time, the MOSFET blocking characteristics
keeps unchanged. This phase is called time delay and
it characterizes the response time of the MOSFET.
This period ends when the MOSFET gate to source
voltage, Vgs, reaches to the gate plateau voltage,
Vgs(Miller).
Stage 2:
After Vgs is equal to Vgs(Miller), its voltage level
will remain unchanged at this stage. The MOSFET
capacitor between drain to source, Cds, will be
charging up by the load current to re-build the space
charge region. This period ends until the MOSFET
drain to source voltage, Vds, reaches to the circuit
output voltage.
Stage 3:
Cgs will keep on discharging. The drain current, Id,
and Vgs are started to decease linearly breaking the
MOSFET conduction channel. This period is ended
when Vgs level is the same as the gate threshold
voltage, Vgs(th) and Id became zero. MOSFET will
be completely turn-off after this stage ends.
Stage 4:
Cgs is continually discharged by the gate drive until
the voltage level of Vgs becomes zero.
Fig.2 MOSFET equivalent model
III . POWER MOSFET SWITCHING ANALYSIS
For power MOSFETs, Fig. 3(a) shows a
simplified equivalent circuit of one phase leg,
including the most relevant parasitics present in
actual power converters, such as parasitic inductances
in series with drain and source terminals of the
MOSFET, and inherent parasitic capacitances 𝐶𝑔�,
𝐶𝑔�, 𝐶��. The Turn-on and Turn-off processes can
be explained as follows:
A. Turn-on Process
Fig. 3(b)-(e) shows the equivalent circuits at different
periods of the turn-on process.
Period I:
For simplicity, a freewheeling diode is used instead
of the bottom switch during the commutation period.
The commutation time is sufficiently short, the load
current can be treated as a dc current source �𝑙𝑜𝑎�.
Therefore, Fig. 3(a) can be further simplified as Fig.
3(b). At �0, the gate voltage ��� is added to the top
switch, charging the input capacitances 𝐶𝑔� and 𝐶𝑔�.
Fig.3 Turn-on Process: (a) equivalent circuit (b)
This period ends when the gate voltage 𝑣𝑔� has risen
period I: delay period; (c) period II: turn-on
to the threshold voltage ��ℎ at �1. At this sub stage,
transition;(c) Period III: reverse recovery; (d) period
the drain current �� of the top switch is still zero;
III: ringing.
there is no power loss during this period.
Period II:
At �1, the drain current �� starts to take over the load
current.
Period III:
At �2, the top switch takes over the load current �load
and the bottom diode starts to recover, but still cannot
block the voltage. �� reaches its peak value at �3 when
the diode starts to block voltage. Beyond �3, the
ringing continues and assumed to be completely
damped at �4. The equivalent circuits for [�2, �3] and
[�3, �4] are shown in Figs. 3(c) and (d), respectively.
B. Turn-off Process
Fig. 4(a)-(c) shows the equivalent circuits at different
periods of the turn-off transition.
Period I:
At �5, the gate circuit starts to discharge the
capacitances 𝐶𝑔� and 𝐶𝑔�, causing the gate-source
voltage 𝑣𝑔� starts to fall. But 𝑣�� and �� do not change
in this period. This period ends when 𝑣𝑔� decreases to
the plateau voltage at �6. Power losses can be
neglected during [�5, �6] as this period is very short.

Fig. 4 Turn-off Process: (a) period II: turn-off
transition; (b) period II: 𝑣�� continue rising; (c)
period III: ringing.
Period II:
At �6, the drain-source voltage 𝑣�� starts to rise while
the gate voltage is held at the plateau level. The
excess current charges the capacitances. �� does not
change until 𝑣�� reaches the input voltage at �7. After
that, 𝑣�� continues rising due to the existence of the
parasitics. This period ends at �8 when the drain
current reaches zero. At this moment, the drain-
source voltage reaches its peak voltage ��.
Period III:
A voltage ringing period continues after �8 until 𝑣��
reaches its steady-state value at �9.
Now the overall Turn-on and Turn-off process
waveforms can be summarized as the following
switching waveform:
Fig.5 Waveforms of MOSFET switching
IV. CONCLUSIONS
Impact of fast switching MOSFET package parasitic
inductor in the switching performance has been
analyzed in this paper. The package source inductors
act as a key parameter on the transient period which
is highly related to the switching speed and the
switching control ability due to the gate oscillation.
The purposed separated source package MOSFET
minimizes the negative influence generated by the
common source package parasitic inductor. As the
switching frequency is boosted into the megahertz
range, the abrupt switching approach used in the
conventional PWM converters encounters formidable
difficulties. In particular, the switching stresses and
losses, which are suppressed by means of snubber
circuits or ignored at lower frequencies, become into
liable at high-frequency operations.
Since the power devices arc switching under a zero-
voltage condition, this technique offers several
distinct advantages like as elimination of switching
losses and stresses while achieving high efficiency by
keeping the device's conduction loss minimal. The
switching losses been eliminated include the loss
internal to the device due to the discharging of
junction capacitance s when the device is turned on.
This internal loss becomes significant when the
switching frequency exceeds one MHz in a PWM
converter or a conventional resonant converter,
elimination of dv/dt noise due to device switching.
The noise is often coupled into the drive circuit by
means of the Miller effect, and is one of the primary
limiting factors for designing at very high frequency
with low electromagnetic interference.
REFERENCES
[1] K. K. M. Siu, M. K. H. Cheung and F. P. Stückler,
"Performance analysis of package parasitic inductances for
fast switching MOSFET in converter," 2014 International
Power Electronics and Application Conference and
Exposition, Shanghai, 2014, pp. 314-319.
[2] Hsin-Ju Chen, G. L. Kusic and G. F. Reed, "Comparative
PSCAD and Matlab/Simulink simulation models of power
losses for SiC MOSFET and Si IGBT devices," 2012 IEEE
Power and Energy Conference at Illinois, Champaign, IL,
2012, pp. 1-5.
[3] K. H. Liu and F. C. Lee, "Zero-voltage switching technique in
DC/DC converters," 1986 17th Annual IEEE Power
Electronics Specialists Conference, Vancouver, Canada, 1986,
pp. 58-70.
[4] S. Sathyan, H. M. Suryawanshi, B. Singh, C. Chakraborty, V.
Verma and M. S. Ballal, "ZVS–ZCS High Voltage Gain
Integrated Boost Converter for DC Microgrid," in IEEE
Transactions on Industrial Electronics, vol. 63, no. 11, pp.
6898-6908, Nov. 2016.
[5] Y. Xiong, S. Sun, H. Jia, P. Shea and Z. John Shen, "New
Physical Insights on Power MOSFET Switching Losses,"
 in IEEE Transactions on Power Electronics, vol. 24, no. 2, pp.
525-531, Feb. 2009.
[6] X. Li, L. Zhang, S. Guo, Y. Lei, A. Q. Huang and B. Zhang,
"Understanding switching losses in SiC MOSFET: Toward
lossless switching," 2015 IEEE 3rd Workshop on Wide
Bandgap Power Devices and Applications (WiPDA),
Blacksburg, VA, 2015, pp. 257-262.
[7] L. E. A. Lirio, M. D. Bellar, J. A. M. Neto, M. S. d. Reis and
M. Aredes, "Switching losses analysis in sic power
mosfet," 2015 IEEE 13th Brazilian Power Electronics
Conference and 1st Southern Power Electronics Conference
(COBEP/SPEC), Fortaleza, 2015, pp. 1-6.
[8] V. Dimitrov, P. Goranov and D. Hvarchilkov, "An analytical
approach to model the switching losses of a power
MOSFET," 2016 IEEE International Power Electronics and
Motion Control Conference (PEMC), Varna, 2016, pp. 928-
933.
[9] Z. J. Shen, Y. Xiong, X. Cheng, Y. Fu and P. Kumar, "Power
MOSFET Switching Loss Analysis: A New
Insight," Conference Record of the 2006 IEEE Industry
Applications Conference Forty-First IAS Annual Meeting,
Tampa, FL, 2006, pp. 1438-1442.
[10] J. Fu, Z. Zhang, Y. F. Liu and P. C. Sen, "MOSFET Switching
Loss Model and Optimal Design of a Current Source Driver
Considering the Current Diversion Problem," in IEEE
Transactions on Power Electronics, vol. 27, no. 2, pp. 998-
1012, Feb. 2012.
[11] A. Van den Bossche, R. Stoyanov, N. Dukov, V. Valchev and
A. Marinov, "Analytical simulation and experimental
comparison of the losses in resonant DC/DC converter with Si
and SiC switches," 2016 IEEE International Power
Electronics and Motion Control Conference (PEMC), Varna,
2016, pp. 934-939.
[12] L. Jin, S. Norrga and O. Wallmark, "Analysis of power losses
in power MOSFET based stacked polyphase bridges
converters," 2016 IEEE 8th International Power Electronics
and Motion Control Conference (IPEMC-ECCE Asia), Hefei,
2016, pp. 3050-3055.
[13] P. Grzejszczak and R. Barlik, "Switching losses in a new high-
voltage MOSFETs," 2016 Progress in Applied Electrical
Engineering (PAEE), Koscielisko-Zakopane, 2016, pp. 1-6.
[14] A. P. Arribas, M. Krishnamurthy and K. Shenai, "Accurate
characterization of switching losses in high-speed, high-
voltage Power MOSFETs," 2015 IEEE International
Workshop on Integrated Power Packaging (IWIPP), Chicago,
IL, 2015, pp. 95-98.