Lecture 2251 2018

RMIT University
School Electrical & Computer Engineering
EEET-2251
Digital Systems Design 1

Lecture Notes
Design is the ability to take a client

specification and create a solution. It
requires imagination, technical skills,
and determination. This course will
help you advance in all these areas.
What will you learn?

• Basic electronics and
construction methods.
• Digital devices such as
gates and flip-flops.
• Digital systems design and
implementation.
• Fault finding.
• System level design
methods. Dr. Pj Radcliffe, 2018
EEET-2251 Digital Systems Design 1 :
Table of Contents
1 Introduction........................................................................5
1.1 Example Digital Systems......................................................7
1.2 Basic Educational Theory.....................................................8
1.3 Occupational Health & Safety............................................12
2 Basic Electronics...............................................................13
2.1 Components, Schematics and Wiring Diagrams................14
2.2 Construction Techniques....................................................18
2.3 DC Voltage, Current, Power and Resistance......................22
2.4 Kirchoff's Laws...................................................................27
2.5 The Multimeter...................................................................29
2.6 Time Varying (AC) Voltages..............................................31
2.7 Diodes, LEDs, BJTs, & FETs.............................................33
2.8 Capacitors............................................................................36
2.9 Inductors..............................................................................38
2.10 Switches and Relays.........................................................39
2.11 Integrated Circuits.............................................................42
2.12 HC Logic...........................................................................44
3 Digital Electronics.............................................................45
3.1 Combinational Logic..........................................................46
3.2 Boolean Algebra.................................................................50
3.3 Combinational Logic Minimization...................................52
3.4 Simulators............................................................................59
3.5 State Diagrams....................................................................60
3.6 Sequential Logic.................................................................65
3.6.1 Synchronous Logic............................................................66
3.6.2 Synchronous Logic Example 1..........................................71
3.6.3 Synchronous Logic Example 2..........................................72
3.6.4 Finite State Machine Using Memory.................................79
3.6.5 Timing Calculations...........................................................80
3.7 Digital Device Zoo..............................................................82
3.8 Logic Families & Compatibility.........................................85
3.9 Programmable Logic...........................................................89
4 Testing and Debugging....................................................91
4.1 Specific Testing/Debug Methods.......................................94
4.2 Intermittent Faults...............................................................98
4.3 Digital Design Construction & Debugging......................100
4.3.1 Time Management...........................................................100
4.3.2 Simulation........................................................................100
4.3.3 Basic Soldering................................................................100
4.3.4 Devices & Wiring............................................................101
4.3.5 Breadboards.....................................................................101
Copyright © Pj Radcliffe 2018 Page 2
4.3.6 Debugging Techniques....................................................101

4.3.7 Beyond the Multi-Meter..................................................103
5 Interface Electronics.......................................................105
5.1 Sources of Interference.....................................................105
5.2 Interference Solutions.......................................................109
6 System Level Design.......................................................113
6.1 Functional Block Diagrams..............................................114
6.2 Flow Charts.......................................................................124
6.3 Activity Diagrams.............................................................125
6.4 Resolving Flowcharts and Block Diagrams.....................126
6.5 Mind Maps........................................................................128
7 Project Life Cycles..........................................................131
7.1 Waterfall Models & 2167A..............................................134
7.2 Spiral Life-cycle Model....................................................140
7.3 Prototyping Life-cycle......................................................142
8 Worked Problems...........................................................146
8.1 Problems Without Answers..............................................146
8.1.1 Number Systems..............................................................146
8.1.2 Boolean logic...................................................................147
8.1.3 Basic Logic......................................................................147
8.1.4 Simple K-Maps................................................................149
8.1.5 K-Maps and Motor Control.............................................150
8.1.6 Five Input K-Maps...........................................................151
8.1.7 Synchronous Circuit Analysis.........................................152
8.1.8 Synchronous Circuit Design 1.........................................153
8.1.10 River Height Indicator for Third World Countries........154
8.1.11 FBD for Hospital Ward Automation.............................155
8.2 Problems with Answers....................................................156
8.2.1 Number Systems..............................................................156
8.2.2 Boolean logic...................................................................157
8.2.3 Basic Logic......................................................................159
8.2.4 Simple K-Maps................................................................161
8.2.5 K-Maps and Motor Control Part 1...................................163
8.2.6 Five Input K-Maps...........................................................165
8.2.7 Synchronous Logic Analysis...........................................166
8.2.9 Synchronous Circuit Design: Motor Control...................171
8.2.10 River Height Indicator for Third World Countries........173
8.2.11 FBD for Hospital Ward Automation.............................176
8.2.12 K-Maps and Motor Control Part 2.................................179
9 Appendix 1......................................................................180
9.1 Number Systems...............................................................180
9.1.1 The Binary Number System............................................181

9.1.2 Negative Binary Numbers...............................................181
9.1.3 Binary Number Problems................................................182
9.1.4 Octal and Hexadecimal....................................................184
9.1.5 Converting Between Bases..............................................185
9.1.6 Non-Column Weighted Codes.........................................186
10 References......................................................................187
11 Index..............................................................................188
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EEET-2251 Digital Systems Design 1 : Introduction
1 Introduction
Before talking about the course content there are fundamental
principles about university education that you must understand.
QUESTION: why are engineers paid

more than food retail workers? Typical Salaries as of April 2017
Food retail ≈ $38,000 per year average
ANSWER: they have knowledge, skills, Graduate Electrical Engineer
work ethics, professional skills and ≈ $67,000 per year median
attitudes that are valuable. Source:
https://calculate.fairwork.gov.au/FindYourAward
ADDITIONALLY engineering jobs tend http://www.professionalsaustralia.org.au/financia
to have better salary increases, more l-edge/salary-calculators/graduate-engineer-
interesting work, are healthier, and can be calculator/
continued to retirement age.
A CAREER ! In short engineering is a wonderful career if you take it seriously.
QUESTION: what makes a graduate attractive to an employer at the job application and
interview? You need to know this as not all graduates get a job!
• Marks average better than 65-70%.
• Professional skills: reliable, timely, good work ethic, easy to manage, works well in a team
or as an individual, pleasant and helpful, knows when to report, shows initiative.
• Communication skills: both written and oral, and the ability to work with clients.
• Design ability: be able to work with clients to create a requirements statement, propose a
solution path at a system level, propose subsystems, implement subsystems and systems,
test and commission a subsystem and system.
The professional and communication skills are sometime called the “soft skills”.
EMPLOYERS are quite clever and they have good ways to evaluate your abilities. They value
demonstrated achievements over potential ability.
Marks are used as a hurdle to be allowed to the next level of evaluation. You must get over
each hurdle, and acquire real engineering and soft skills in order to get a job.

IMPLICATIONS FOR YOU: your university career must be a dedicated period where you as
an individual must strive to identify and acquire all of the above attributes. Marks are only one
part of the equation.
Make sure you build a portfolio of proven abilities that you can take to the job interview.
Consider the following statements on your CV, perhaps backed up by photos-
• As an optional activity I …
• I designed and built the communications system for RMIT's electric racing car.
• I designed and built a novel power controller for solar panels.
• I designed and built an Android controlled front door lock.
HOW WILL THIS COURSE HELP YOU? This course will help you become an employee
who is attractive to an employer, and help you get ready for later courses.
The emphasis of this course is design though there is opportunity to gain other attributes as
well.
• Design process: you will learn and practice the process of reading requirements analysis,
system design, subsystem design, implementation, and testing.
• Formal methods: you will learn formal methods such as block diagrams, state diagrams,
and more.
• Basic knowledge: you will learn the basics of electronic and digital systems.
• Actual design: you will use formal methods to build real electronic and digital circuits.
• Professional behavior: we will talk about and practice some important behaviors valued in
industry.
LECTURE NOTE FORMAT: these notes differ from traditional overheads-

• Harder to follow: they are dense and a little harder to follow in the lecture compared to
traditional Power Point slides.
• Long term: unlike many overheads these notes have good material that will guide labs and
may be useful later.
• Lecture only some: the lecturer will only go through some parts in detail and ask you to
read other parts.
GO FURTHER? These notes give a bare outline of what you should master. Particularly if
you are interested, use the web or a good text book to learn more. If you find anything
confusing again consult these references.

1.1 Example Digital Systems

This course will teach the basics of digital systems; the logic devices and interfaces.
Examples of digital systems include-
FAILSAFE CIRCUITS must always work in all circumstances.

Software systems are simply not reliable enough and so digital
hardware is used for implementation.
The pedal opposite is a dead man pedal as used on many trains.
Should the driver go limp or spasm the pedal will not be in the Illustration 1: Dead-man Pedal
middle position and so stop the train.
Digital logic can also stop software crashes from
damaging hardware or causing malfunctions.
SENSOR SYSTEMS need the inputs to be captured and

conditioned. This requires analogue electronics and often Illustration 2: Sensor Capture
digital electronics.
CONTROL SYSTEMS use digital logic to drive

actuators.
GLUE LOGIC is digital logic that sits between a

microprocessor and the outside world for several reasons-
• The logic can handle higher currents and voltages than
the microprocessor, on both inputs and outputs. Illustration 3: Tattoo via a CNC Machine
• The logic protects the processor.
• Digital logic can work much faster than
software and may reduce the load on
software.
SMALL SYSTEMS that are very reliable and

very fast can be made with just digital logic. Illustration 4: Traffic Lights; Simple and Reliable
YOU CAN BUILD impressive systems if you understand

digital logic + microprocessor software + electronics.
This course will give you the basics of electronics and digital
logic.
Illustration 5: Quadcopter

1.2 Basic Educational Theory

This section summarizes some key
insights on how to learn. This is probably
the most important section in the entire
notes!
REMEMBERING: you will find the

lectures and labs much easier, and get a
better exam mark, if you can remember
the lecture material. Studies on university
students has shown several simple but
effective methods that will improve your https://www.ole.bris.ac.uk/bbcswebdav/institution/Recycle
memory and understanding- %20Bin/educational_theory.html
• The lecture/tutorial: stay awake by
underlining, writing down, and adding comments to notes. If the session is interactive
make sure you contribute. If you remain still then your brain will turn off.
The process of listening, editing, and writing helps keep you awake , helps you remember,
and improves understanding.
• Reread the material twice within 48 hours. Going home on public transport is a good time.
Good to go through it the next day also.
• Linkage: link the new material to your existing knowledge base, or possible uses and
applications. Imagine how you could use the material or what problems it could help you
avoid.
• Self test: do the exercises suggested by the lecturer, or make up your own.
HANDS-ON: there is no substitute for hands on work or Performance predictor: we

using the lecture material on problems. Take every lecturers can nearly always pick
opportunity to build, design, or calculate. If there are no who will get good marks. People
set tasks think up a few yourself. Do these things as with a hands-on orientation, can do
early as possible to allow time to fail and recover. attitude are nearly always good, or
will become good quite quickly.
COPYING: this is a quote from my first boss-

“The only time it's wrong to copy is when you get sued. Copying will save time and effort, and
is more likely to result in something that works.”
He was right, so why are universities so strident about the evils of plagiarism and copying?
The reason is simple: when you copy you do not learn, and on the next task you will be even
further behind and have to copy, and then often fail an exam.
It is actually an unkind deed to give anyone the complete answer as you are pushing them down
the path to failure.

Learning things and doing the work yourself is hard Delayed Gratification: the ability
work but worthwhile. The ability to work now, for to ignore immediate desires (avoid
benefits later, is called “delayed gratification” and is a work) to gain a superior long term
key feature of successful people. gain (competency and a job).
NEVER COPY OR GET HELP? No no no … the

anti-copying message is often understood to mean don't
look at what other people have done and don't get help.
Indeed you should always try first to do the work
yourself and then-
• References: read the references and the web to
solve your problem.
• Team work: discuss what you have done with your
friends or the team. It's very likely that if you have
made a mistake or get stuck then someone else
may be able to help.
Usually team discussion can generate better ideas
than an individual (this is called the group IQ
effect).
*** Those who explain things always gain, those
who listen sometimes gain. “If I have seen further it is by
• Tutor/lecturer/boss/mentor ... If you are still stuck standing on the shoulders of
see these people. Take care to be very well giants.”
prepared and waste as little of their time as
possible. Sir Isaac Newton, probably the
• Stuck? Learning is a balance between impatience world's greatest scientist.
and obsession, spending too little time on a
problem will reduce your learning, spending too much time will waste your valuable time
and reduce output.
Go and get help if you are stuck too long, or move onto another task.
• State of the art: in engineering it is vital to avoid “reinventing the wheel”. Engineers must
read widely and look at what others have done. Consider text books, industry publications,
academic publications and the web. First have your own ideas and then look at what others
have done.
*** In written work always reference your sources, this proves you have read the state of
the art and will help your marks!

CONTINUOUS IMPROVEMENT: a successful professional must live a life of continual self

improvement. If you fail at this task then you will stagnate and fall behind. Key tasks here
include-
• Reflection: evaluate your performance and think how you could do a better job. Look at
technical and professional attitudes.
Set yourself regular times to reflect on your professional life.
• Update: an industry rule of thumb is that you should spend half a day per week improving
your skills and knowledge.
RESILIENCE is your ability to (sensibly) keep on trying

in the face of failure and setbacks. Resilience is generally
accepted as the best predictor of success in a whole range
of situations including work and personal life. Good
resilience helps make people happier and is particularly
important for kids.
Most competent job interviewers will ask questions to try
and gauge your resilience. http://www.cyh.com/HealthTopics/HealthTop
Attitudes which hurt your resilience include; blame the lab icDetailsKids.aspx?p=335&np=287&id=1758
guide, blame the tutor, this is stupid, I have better things

to do, I don't care, I can copy the answer ... Question: in year 7, what factor is
Attitudes which help resilience include; let's try again, the best predictor of mathematics
where did I go wrong, I can beat this, let's try a different success in year 12?
way, let's think about this, let's do it, the instructions are Answer: the best by far is
wrong but I can work around that … resilience.
Question: how good is your resilience? What attitudes
can you adopt to help improve your resilience?
Remember: when the going gets tough, the tough get going.
HAVE A GOAL: self motivation and learning is improved if you have a goal. There are a
whole range of goals and activities to discover goals-
• Employers: what employers do you like? Check www.adzuna.com.au and www.seek.com.
Next work out what technical and professional skills the employers are after and work on
those skills.
• Marks: always a good goal and the first filter for job interviews.
• Enjoy: what areas inspire you? Work on them and see if you can turn it into a career.

PROACTIVE: in primary school you waited for the teacher to give you material and to tell
you what to do. Professionals take charge of their own education, they use the resources
available but plan what to do and then execute those plans.
Question: do you just wait to be told what to do?
IMPORTANT !!! This section is the most important part of the notes and I urge you to reread
it carefully and think how you can become a better professional.
In this course exam questions will be asked about this material!
Your job interviews will certainly focus on this material!

1.3 Occupational Health & Safety

Occupational Health and Safety ( OH&S) is
concerned with the health and safety of anyone
engaged in work or being a client of a work place.
In most countries OH&S requirements are set by
laws and the requirements of insurers.
AUSTRALIA has strict laws that require Different Times, Different Cultures
management and workers to be proactive in
identifying hazards and removing hazards. All What is acceptable OH&S varies with
staff should have OH&S training. Enterprises time and with culture.
must develop OH&S guidelines that minimize • Germany brought in the first
hazards. workers protections in 1884.
Employers must have OH&S insurance and Before that there was no
premiums rise significantly for a bad accident compensation for workplace
record. accidents and many workplaces
had appalling accident records.
All RMIT staff must pass an OH&S on-line test
every 2 years. The following is copied from that • In Australia there were 184
course! accidental deaths at work in 2014.
7000 deaths each year are related
to work related diseases.
Hazards can generally be put into five main Total costs are estimated at 5%
categories: GDP.
1. Environmental (e.g. lighting, noise, air quality, • Australia has tough OH&S laws,
temperature); and low accident rates.
2. Materials (e.g. wood, metals, fabrics, plastics, • Many 3rd world countries have
chemicals);
much worse OH&S which reduces
3. Design and management of programs (e.g. employers costs but can devastate
supervision, scheduling, facilities); workers.
4. Equipment and machines (e.g. tools, machinery,
electrical, plant and equipment);
See http://www.safeatwork.org.au/about-us/what-ohs
5. Work processes (e.g. safe work instructions, how
we perform activities, training and induction).
All RMIT employees and contractors must:

 Work safely at all times;
 Report any potential or existing hazards you encounter;
 Observe and participate in the resolution process where appropriate;
 Participate in all safety programs and training being implemented;
 Use equipment properly and as instructed.
RMIT Students are required to work within the RMIT guidelines. You will be required to
watch the OH&S video and read OH&S rules before you can be in the labs.

EEET-2251 Digital Systems Design 1 : Basic Electronics
2 Basic Electronics
This chapter aims to help
Aside: Associative Memory
you understand the basics of
electricity and the components The human brain has a remarkable ability to link facts
that you will use in your projects. and so help you generate solutions to problems.
As in the box opposite, you must Have you ever thought about a problem and then some
build up your knowledge base in time later the solution “pops” into your mind? Quite
order to be good at design and unconsciously your brain has been pattern matching the
solving problems. problem statement and your knowledge. When it finds a
match this is placed into your conscious mind.
If you succeed in building your
knowledge base then engineering To use this remarkable ability you must clearly state the
becomes something you can problem in your own mind, and have a huge knowledge
understand, control, and fix if it of the problem domain (engineering). You must start
goes wrong. If you do not have building your knowledge base now and continue adding
this knowledge base then to it all your life.
engineering becomes very Associative memory, or intuitive problem solving, is
confusing and you will be lost if only one method of solving problems but a particularly
the lab instructions are the powerful one.
slightest bit wrong or incomplete.
WATER ANALOGY: to help you gain a conceptual or gut feel for electricity it is useful to
form an analogy with water. The match between water and electricity is not ideal but enough to
give you that feel.
Water-Electricity Analogy
Water Based Feature Electrical equivalent.
Water flows through pipes. Electrons are like an electron fluid that
flows through conductive wires (usually a
metal). Electrons do not flow through
insulators (usually non-metals).
Plumbing devices control the flow of water, Electrical devices can control the flow of
for example thin pipes, and one way valves. electricity and have a water equivalent, for
example resistors and diodes.
Loop? Water may have a source but it can be Loop! Electricity sources have two
left anywhere. There is no need for water to terminals, electrons must flow out one and
be returned to the source. via a conductive loop back into the other.
The water-electricity analogy is not perfect,
but good enough to be very useful.

2.1 Components, Schematics and Wiring Diagrams

Your first electronic project will be assembling
simple electronic components into an electronic circuit.
Use this simple project to build skills needed for the
bigger projects you will do in the near future. These skills
include-
• Identify: be able to identify components and be able
to work out which way around the component must
be mounted. Some components are “polarized” and
will not work if mounted the wrong way around. Illustration 6: Electronic Components
• Schematic diagram: be able to relate a physical
component to a logical diagram of the circuit called a schematic circuit diagram.
• Wiring : be able to relate the schematic diagram to the physical circuit.
• Systematic: your construction should be done in a careful and systematic manner. The
small increase in time and effort here is usually much less than the cost of fixing a fault
construction.
• Testing, debugging, and repair: testing is systematically checking the circuit works,
debugging is finding out why it does not work.
SCHEMATIC DIAGRAM: to describe a circuit you could draw a

wiring diagram which is a picture of the real system. The problem is
that this will be hard to understand and time consuming to draw. The
solution is to draw a circuit schematic diagram that shows the circuit
elements arranged in a logical order.
*** You must develop the skill of relating a schematic diagram to the
real hardware.
STANDARDS: there are two circuit symbol standards in common

use-
• Traditional American: the ANSI standard Y32, also known as
IEEE Std 315 is commonly found in hobbyist magazines and Illustration 7: Wiring versus
older books. Schematic Diagram
This standard is not so tightly copyrighted and this makes it
popular.
• IEC 60617 is a European standard that has now been adopted by many US organizations
such as DoD. It is in theory better but the copyright is more tightly held so any program
that uses these symbols should pay a fee.

KEY DIFFERENCES: the symbols are similar for most simple IEEE ANSI
electronic components with the exception of resistors and logic gates. Resistor Symbol
DRAWING CONVENTIONS: schematic circuits have a variety of

drawing conventions that make them easier to understand- Illustration 8: Resistor
symbols
• Left to right: usually the flow of energy is left to right, inputs on the
left and outputs on the right.
• Vertical and horizontal: most wires and components are oriented along a vertical and
horizontal grid. There are seldom any diagonal lines.
ANSI SYMBOLS are shown on the next page. Detailed explanations of the component types
is be given later.


DIGITAL GATES have quite different representation. Below are the IEC, ANSI US, and a
German standard.

2.2 Construction Techniques

If you have a schematic for an electronic circuit then you will need to build it to ensure it
works properly. How can you do this?
CLIPS AND WIRES: very

simple circuits may be
prototyped using alligator
clips and wires twisted
together. This approach is
not robust or reliable and
barely deserves a mention.
Illustration 9: Alligator Clip Construction
BREAD BOARDS are a matrix of holes

each of which has a socket that can
receive a wire, the leg of a component, or
the leg of an integrated circuit. Rows of
sockets (the shorter vertical rows
opposite) are connected together. Wires
stripped at each end can be used to
connect components together.
Breadboards are a good way to prototype
small circuits and are very easy to
change. They are notorious for having
bad connections especially when
transported in a bag. Constructions Illustration 10: http://www.buildcircuit.com/category/basic-
beyond 2 or 3 integrated circuits tends to electronics-2/mini-breadboard/
be too unreliable even for prototyping.
INTERNAL CONNECTIONS on a breadboard are

shown with hand drawn lines in the diagram opposite. All
breadboards have the north-south internal connections
between pins. Some breadboards also have an additional
edge unit that has east-west connections as shown opposite.
These are useful for distributing zero volts and power.
Some east-west power lines have a break in the middle

which must be bridged by a wire link.
Illustration 11: Breadboard Internal
Connections

BREADBOARD JUMPERS are wire links

used to connect devices and components
together.
Most breadboards are designed to take 22
AWG (American Gauge Wire), 0.644mm,
which is the diameter of the wire on a
standard 1/4 watt resistor. Breadboards will
take wire a little smaller but not much larger.
The length of wire inserted into a breadboard
Illustration 12: Breadboard with Staples as Links
should typically be around 0.2" to 0.3" to
ensure a good connection. The holes in a
breadboard are 0.1" apart so they can make a convenient measure.
• Staples can be used to cover small distances.

Be very careful to select staples that do not have a plastic cover as these will give an
open circuit.
• Bare copper wire can be cut easily cut and bent into shape. Be careful to only use this
approach when there is no danger of short circuits between this wire and other wires or
component leads. Off cuts from resistors can be used as short links.
• Stripping wires yourself is the traditional way to make connections.

See the following link for a clever way to strip wires-
http://www.instructables.com/id/Stripping-Small-Jumper-Wires/
• Connection kits are cheap and save you the

effort of cutting and stripping wires.
The looping wire style shown opposite is OK
for small circuits but is not suitable for larger
circuits as the circuit becomes almost
impossible to follow with all the long looping
wires. This makes debugging much more
difficult.
Illustration 13: Breadboard Connection Kit

• U shaped connection kits are available
for only a few dollars. These are
probably the best type of kits as they
make it easy to follow the circuit you
have built and so make debugging
easier.
Illustration 14: U Jumper Kit

SOLDERING USES low melting point metals that can be melted with a soldering iron and
spread across metal surfaces. When the solder cools the metal pieces are held together with an
electrically conductive metal bond.
Make sure you view the soldering video to understand more about this process. Incorrect
technique may result in bonds that break (usually just before you are being marked), or look
good but have no electrical contact.
Electronic solders are low melting point alloys and must be eutectic; they go from solid to
liquid without a paste state of mixed solid and liquid. Lead-tin solder melts at about 188 deg C
and is no longer favored due to lead toxicity. Lead free solder based on Tin-Copper-Silver
melts around 230 deg C and is more brittle than Tin-Lead. Most solders also contain a flux
which dissolves any metal oxide which stops solder bonding to a surface.
MATRIX BOARD is a circuit board with a regular matrix of holes, usually 0.1 inch pitch to
match the leg separation of integrated circuits. Some boards have copper rings on each side of
the board, and copper through the holes to help soldering. Components are connected by
bending their legs and soldering, and by adding wires and soldering.
Matrix board is robust and a good technique if you are reasonably certain of your circuit.
Changes are quite possible though slower than a breadboard.
Illustration 15: Matrix Board

PRINTED CIRCUIT BOARD (PCB) is the the

most robust construction and suited to mass
manufacture. Copper tracks connect between
components with the components soldered into
place.
Opposite is a hand made two layer board that
takes pin-hole components. This can be hand
soldered with ease.
Illustration 16: Two Layer PCB, Pin-Hole
It takes a lot of effort to create a PCB layout and Components
make the physical board so it only makes sense to
make a PCB if you are very certain that the circuit works. Generally you should have proved
the circuit works using one of the other construction methods or use a high quality circuit
simulator.
SURFACE MOUNT allows the use of tiny components that

are almost too small to see. The board opposite was student
constructed and the track area is about 2.5 cm square.
Surface mount suits mass automated manufacture and can
produce very low cost devices.
In industry the smallest surface mount components are 0.1mm
square. Some PC motherboards have 1000 pin packages and Illustration 17: Surface Mount PCB
20+ layers of copper tracks, plus power planes.

2.3 DC Voltage, Current, Power and Resistance

There is a good analogy between the flow of water and the flow of electricity which helps
get a feeling for electrical measurements.
Direct Current (DC) Power Supplies supply a steady source of energy.

Water current is the volume of water per Electric current is the number of electrons
second that passes down a pipe. per second passing down a wire.
SI units: cubic meters/second. SI units: amps (columbs/second).
Water pressure inside a pipe can result in no Voltage is an electron pressure. A battery
water movement if the pipe is sealed, or a lot can have a voltage with no current flowing.
of water current if the pipe has an exit. e23055 If there is an electrical loop then
electric current can flow.
SI units: pascal. SI units: volts.
MORE ANALOGOUS BEHAVIOR-

• Sparks: if water pressure is too high then the pipe bursts and water leaks out.
If the voltage is too high then electrons may leap out in the form of a spark.
• Heat: a lot of water current rushing down a pipe can make it a little warm.
High electrical current can make electrical components hot, even burn them out.
• Power: the power lost in a water pipe is current* pressure.
The power lost in a wire is current*voltage.
COMMON UNITS you will see include-
Volts Description Amps Description

uV Microvolt, 1/1,000,000 of a volt. uA Microamp, 1/1,000,000 of an amp.
Tiny ECG signals are about 100 uV. A quartz watch may draw 1 uA.
mV Millivolt, 1/1000 of a volt. mA Milliamp, 1/1000 of an amp.
Thermo-couple sensors output An small LED uses around 10 ma.
about 100mV.
V Volt. Batteries are usually 1.5v or A Amp. 1 amp is drawn by the old
3v. Stacked cells make 9v or 12 v. incandescent car door lights.
kV Thousand volts, dangerous! kA Thousand amps, 50 homes.
MV Million volts, very dangerous. MA Mega amps, very dangerous.
Big transmission lines may be ½
MV.

DC POWER SUPPLIES: all DC (Direct Current) power supplies have a plus (+) and minus (-)
terminal.
• Electrons flow from the – the the + terminal.
• Conventional current is said to flow from the + to
the – terminal.
Yes this is silly, but electricity was used long
before the negatively charged electron was
discovered. Rather than rewrite the text books
about which way current flowed, the concept of
conventional current and electron current
(opposite direction) was developed. Illustration 18: Conventional and Electron Currents
All circuit theory uses conventional current which
flows from + to -.
Examples of DC power supplies include-
• Primary batteries can supply voltages in the range of 1 to 3
volts, and can be put in series to increase voltages. They
convert chemical energy to electrical energy and when
exhausted are thrown away, or even better recycled.
• Secondary batteries and like primary batteries but can be
recharged.
• Power supplies are generally powered from mains
electricity (which is not DC) and convert this to DC. A Illustration 19: Batteries
good example are the 5 volt USB chargers used by most
phones and tablets.
• DC lab power supplies are usually mains electricity
powered and deliver one or more independent DC
supplies. They have meters to show you voltage and
current in any supply, can adjust voltage, and may set an
upper current limit (so as not to destroy circuits).
POWER AND ENERGY: the power that comes out of a Illustration 20: Lab DC Power Supply
battery or power supply can be calculated from the voltage
and current.
P=V*I V = voltage in volts, I = current in amps, P = power in watts.
E=P*t E=energy in joules, t = time period in seconds.
Other energy units ( power * time) are amp-hours (A-h), milliamp-hours (ma-h), and kilowatt-
hours (kW-h). Examples include-
• A 1.5v AAA alkaline battery has a capacity of 1-2 A-h.
• A typical lead-acid car battery is 40 A-h.

RESISTANCE is a basic feature of water pipes and electrical conductors. Some energy is lost
as the current flows through.
Resistance: resists the flow of current.

For the same water pressure, a thin pipe will For the same voltage, a conductor with high
allow less water to flow than a thick pipe. resistance will let little electric current flow.
If a pipe is blocked (infinite resistance) then If there is no conductive loop across a
there may be water pressure but no water battery terminal then there is voltage, but no
current. electric current.
If a pipe bursts near a water main then there If a battery is short circuited by metal bar
is little resistance and a huge amount of then a large current will flow, the battery
water flows. and metal may get hot, and discharge the
battery.
SI units: pascal/cubic meter. SI units: ohm.
THE PERFECT RESISTOR: in electronics there are components

called resistors that are close to ideal. They follow Ohm's law where-
Voltage across resistor (volts)
= Current Through resistor (amps)* Resistance (ohms)
V=I*R Illustration 21: Which Pipe
The power dissipated by a resistor can be derived using the previous has High Resistance?
equation P=V*I
P = V2/R = I2*R
Real resistors are shown in the image

opposite. Items (a) and (b) are ¼ watt
resistors typically ranging from 1 ohm to 10
million ohms. Items (c) are power resistors
up to 10 watts. Item (d) are variable
resistors, turn the knob and the resistance
varies.
SYMBOLS & UNITS

Ω is the ohm symbol Illustration 22: Real Resistors
1mΩ = 1mohm = 1m = 0.001 ohms
1kΩ = 1kohm = 1k = 1000 ohms.
1MΩ = 1Mohm = 1M = 1,000,000 ohms

RESISTOR NETWORKS: resistors may be placed in

R1 R2 R3 R4
series or parallel, and the value of an equivalent
resistor calculated as in the diagram opposite.
Why would you ever use several resistors? There are R total = Ra + Rb + Rc + ...
several reasons- Ra
• Precision: resistors come in fixed values, to get Rb
2.4 kohm you could use a 2.2 kohm and 220 ohm
in series. Rc
Rd
• Power: the resistors can share the power
dissipation, for example you can built a 1 watt 1/R total = 1/Ra + 1/Rb + 1/Rc + ...
resistor out of four ¼ watt resistors. Illustration 23: Parallel and Series Resistors
• Voltage: resistors have a voltage limit, several in
series will each see a fraction of the total voltage. Ra
Example: you have the following resistors 1k, 1.2k, R1 R2 R3 Rb
1.5k, 1.8k, 2.2k. 3.3k, 4.7k, 5.6k, 6.8k, 8.2k.
Rc
Using two resistors, find two ways to get close to 3.7k
as a total value.
Rx Ry
COMPLEX NETWORKS of resistance can be

progressively reduced to a single resistor value.
Rz
Illustration 24: Complex Resistor Simplification
IMPERFECT RESISTORS: even our best resistors are Voltage

imperfect, they change value a little with temperature and Current
burn out if they get too hot. High voltages may cause limit.
sparking. Resistors like all devices are limited to a voltage
Voltage
range, a current range, and a maximum power limit. limit.
In the labs you may well get to burn a resistor so you
remember this fact! Slope=R=V/I
Resistors have a tolerance which means they will not be
exactly the quoted value. For example a 1000 ohm 1% Power limit.
resistor may be 990 to 1010 ohms.
Current
Illustration 25: Resistor Limits
Challenge: using the equations given produce an equation
for the shape of the power limit. Note the power and current has a fixed constant value (the
upper limit for the device).
Question: consider a 10 ohm ¼ watt resistor. Is this safe to put across a 12 volt car battery?

COLOR CODES: resistors are frequently defined by color codes. You will need to learn these
codes, though as a slow back up you can use a multi-meter to measure their values.
Illustration 26: Resistor Color Codes
VOLTAGE DIVIDER: resistors are often in series and it

Vtotal
is useful to work out the voltage across each resistor.
R1 R2 R3 R4
...
V1 V2 V3
VOLTAGE SAG: power sources such as batteries and
electronic power supplies are all designed to deliver a Rtotal = R1 + R2 + R3 + ...
constant voltage regardless of the current drawn but there V1 = Vtotal * R1 / Rtotal
are limits- Vn = Vtotal * Rn / Rtotal
Illustration 27: Voltage Divider
• Power source voltage will drop a little as the
current drawn increases, this is called voltage
sag. In a high quality power sources this sag V (Voltage)
is small. V=Vbatt-I*Rbatt
• Power supplies are often modeled with an Vbatt
ideal voltage source and a series resistor to
model the voltage sag.
• Electronic sources usually have a current limit
and may cut out if the current goes too high. I (Current)
Illustration 28: Battery Voltage Sag

2.4 Kirchoff's Laws

Ohm's laws are useful but not quite enough to help us calculate voltages and currents in
an electronic circuit. Kirchoff's laws fill that gap.
KIRCHOFF'S CURRENT LAW: i1 i2

at a given node the currents must i1+i2+i3+i4+i5 = 0
sum to zero. i3 i=n
Why? Imagine a node where there More generally : ∑ i n=0

was a steady net gain of electrons. i =1
i5 i4
There would be a huge build up of Illustration 29: Kirchoff's Current Law
negative charge that would repel
any electrons trying to come into the node.
KIRCHOFF'S VOLTAGE LAW: for any loop in a

circuit the net voltage must sum to zero.
r3
Why? If this were not true then an electron could do 9v r1
Loop 2
Loop 1
one circuit of the loop and pick up a net velocity. It
r4
could loop around and around the loop steadily
building up energy without limit and violate r2
conservation of energy laws. r5
When using Kirchoff's voltage law be careful as

regards the sign of the voltage drop. Vr3 + Vr4 + Vr5 -Vr2 – Vr1 = 0
In loop 2 opposite the voltages across r3 to r5 are
considered positive. When going around to r2 and r3 Vr1 +Vr2 -9v = 0
the voltage drops are negative given the direction of i=n
travel around the loop.
In loop 1 opposite a similar situation occurs. More generally : ∑ V n=0
i =1
Challenge: there is a third loop in this circuit can you
see it? Illustration 30: Kirchoff's Voltage Law
Example series resistance where r1=r2=r3. Kirchoff's

voltage law says that the voltage around the loop must be
zero thus Vr1 + Vr2 + Vr3 -12v = 0 10Ω r1
12v 12v
By symmetry Vr1=Vr2=Vr3 = 12/3 = 4v. Vx
10Ω 10Ω r2
Example resistor network: Kirchoff's current law says the r3
current at a node must sum to zero. Working at node Vx-
(12v -Vx)/10Ω = Vx/10Ω + Vx/10Ω
12v -Vx = 2*Vx thus Vx = 4v Illustration 31: Simple Kirchoff Examples
Top resistor has (12v-4v)/10Ω = 0.8 A, two bottom resistors
carry 4v/10Ω = 0.4A

Example: multiple voltage sources can complicate

matters. The circuit opposite can use Kirchoff's current Vx
law to work out Vx and hence the current in each resistor. 10v 8Ω 6Ω 15v
A common mistake is to get the sign of terms wrong. To 3Ω
try to avoid this make current into a node positive, and 0v
current out negative.
(10v – Vx)/8Ω – Vx/3Ω – (Vx + 15v)/6Ω = 0 Illustration 32: Kirchoff: Multiple Voltage
Sources
Solving for Vx gives Vx = -2 volts.
Put this back into the equation to be certain the result is correct.
Challenge: from the first equation above work out Vx yourself. Work out the current through
each resistor and confirm the sum is zero.
Example: the circuit opposite is a first attempt at a current sharing

circuit so each LED gets the same current. The circuit has a +5v
fundamental flaw which means Kirchoff's laws wont work! 220Ω
• At the node Vx Kirchoff's current law says the current must sum Vx
to zero and so-
(5v-Vx)/220Ω = (Vx-3.3v)/78Ω + (Vx-1.5v)/180Ω 78Ω 180Ω
• Multiplying out and collecting terms Vx=3.2v Blue Red
Current 220Ω = (5v-3.2v)/220Ω = 8.2ma down. 3.3v 1.5v
Current 180Ω = (3.2 – 1.5)/180 = 9.4ma down.
Current 78Ω = (3.2v – 3.3v)/78 = -1.2 ma up !!! 0v
• Oh no! The Blue LED cannot really act like a battery and Illustration 33: Current
Through LEDs
supply current, it is a passive component and just drops voltage.
Our models sometimes break down, especially if we assume
something which does not hold true. In this example we assumed the blue LED has 3.3v
across it under all conditions. It has 3.3v across it only when current is flowing through it
in forward bias mode. It cannot act like a battery and supply current!
• Solution: eliminate the 220Ω resistor (make it zero ohms) and recalculate the 78Ω and
180Ω to give the same current through each LED.
(Advanced: there is a problem if the same brightness is expected, the brightness per
milliamp varies a lot between colors. The LED efficiency and human eye characteristics
all come into play.)

2.5 The Multimeter

One piece of equipment you must have is a multimeter. They
range from a few dollars to a few hundred dollars though to start with
a cheap one for $10 is fine.
Most multimeters can measure AC and DC voltage and current,
resistance, and often other things.
USING A MULTIMETER: this simple exercise will help you get

started with your multimeter.
• Select the function and range. On the multimeter opposite DCV
at 20 volts maximum is a good start for battery powered devices.
• Connect the black lead to the COM socket and the red lead to the
V-ohm-mA socket. Illustration 34: Multimeter
• Place the black probe on the negative terminal of a battery, and
the red probe to the plus terminal of a battery. If you do not see the specified 9 or 1.5 volts
then the battery may be flat. Try swapping the leads.
• Get a resistor and try to read the color code.
Select the appropriate resistor range on the multimeter and place the probes on either side
of the resistor.
Read off the resistance and check it matches the color codes. Multimeter as Ammeter
• Get a 1.5 volt battery and a 1000 ohm resistor. A
Calculate the current that should flow in the resistor if it is
connected to the battery.
Select the appropriate DC current range on the multimeter. R
Place the meter in series with the resistor and add the battery.
Note the current on the meter.
• Remember to turn off your multimeter so the battery does not Illustration 35: MeasuringICurrent
go flat.
WHERE WILL YOU USE A MULTIMETER? Your electronic projects will seldom work
the first time. You will use the multimeter to work out what has gone wrong. The normal
approach is to start with the inputs and work towards the outputs. Connect the black lead to
zero volts and use the red lead to probe your circuit. First check batteries or power supply at
the point where it is connected to your circuit, then check other places. You will find common
problems such as-
• Misconnected and broken wires.
• Things connected the wrong way round, such as the battery.
• Wrong value component, for example you misread the resistor color code.

MULTIMETERS ARE NOT PERFECT: multimeters are

not perfect instruments. Here are a few simple tests to prove
that. R1
1.5v 2 x 10 Mohm
An ideal voltmeter has infinite resistance and in the figure
opposite you might expect the voltmeter to measure 0.75 volts. Voltmeter
The voltmeter mode has a finite resistance, normally 10 mega- R2
ohms ( 107 ohms ). Using the resistance formulas given V
earlier workout the resistance offered by the multimeter in
Illustration 36: Imperfect Voltmeter
parallel with R2, then the voltage the meter will read. Demo
An ideal ammeter has zero resistance and will have no

voltage drop across it. All real devices have a finite V Voltmeter
resistance. If you have access to two multimeters try the
previous circuit with a 1.5 volt battery and a 1000 ohm A Voltmeter
resistor. Use the second multimeter to measure the
voltage drop across the multimeter set as an ammeter. 1.5 volts V
Challenge: measure the voltage drop across the resistor 1000 ohm
and use the previously given resistance equations to
work out the resistance of the ammeter. I
Illustration 37: Ammeter Resistance
Measurement
Ammeter
Variable
Voltage A Voltmeter
VI CURVES: if you have two multimeters then
you can create a Voltage-Current (V-I) graph for
a component. It's best to use a laboratory power R V
supply where you can easily vary the voltage.
Note that voltage and current can go negative
I
(the power supply gets turned around). For
Illustration 38: Measuring VI Curve
resistors the graph is a straight line but this is not
so for many other devices.
V (Voltage)
X
X
X
X
X I (Current)
Illustration 39: VI Curve for a

Resistor

2.6 Time Varying (AC) Voltages

So far we have looked at voltages which are fixed in
value but there are many important voltages which vary with
time. The amplitude of the voltage (y-axis) can be plotted
against time (x-axis) and the result is called a voltage
waveform. A device called an oscilloscope can display this
waveform.
Oscilloscopes can often display several waveforms which is
very useful for comparing different points in a circuit.
Illustration 40: Dual Channel
Oscilloscope
MUSIC that plays on your phone, when still just

electricity, has an average value of zero volts but the
instantaneous voltage goes positive or negative. This
means the flow of electrons reverses for part of the
time.
Illustration 41: Music Voltage Waveform
MAINS ELECTRICITY is typically 240 volts or 110 volts

AC (Alternating Current). The shape is a sine-wave of
average zero volts, for 240 volts with a positive and negative
peak of 340 volts. The current reverses direction for half the
cycle.
Mains voltages are dangerous and can kill you. Do not work
with mains power until you have more experience and
always follow the safety guidelines.
Illustration 42: 240v Main Voltage

Waveform
DIGITAL CIRCUITRY generates outputs Voltage

which are logical zero ( close to zero volts) and
Rising Falling
logical ones ( close to the power supply, usually Edge Edge
5 volts or 3.3 volts). Time
Illustration 43: Digital Waveform

FREQUENCY: if the waveform has a repeating shape, such as the mains sine-wave, then it is
said to have a frequency.
Frequency in Hertz (Hz) = number of repeated cycles per second.
kHz = kilohertz = 1e3 =1000 Hz
MHz = megahertz = 1e6 = 1,000,000 Hz
GHz = gigahertz = 1e9 = 1,000,000,000 Hz
THz = terrahertz = 1e12 = 1,000,000,000,000 Hz
Frequency Typical examples

8 Hz Lowest frequency heard by elephants.
50 Hz, 60 Hz The frequency of European/Australian and American mains
power.
50 Hz-18 kHz Approximate hearing range of a human, less with age.
70 Hz- 100kHz Approximate hearing range of a bottlenose dolphin.
526.5 – 1605.5 kHz Australian AM radio band.
12 MHz Clock frequency of a small microprocessor.
27 MHz CB radio.
88-108MHz Australian FM radio band.
500 MHz Clock frequency of a medium power microprocessor.
1.575 GHz GPS receiver.
1.8 GHz Australian 4G
2.4 GHz Wifi and ISM range (microwave ovens ...)
3 GHz Clock frequency of a fast Pentium processor.
Light travels 100 mm (in a vacuum) during one clock cycle.
5 GHz Wifi.
400 THz Red light.

2.7 Diodes, LEDs, BJTs, & FETs
DIODES conduct electricity in one direction but not the other cathode
Electrical
direction. In water analogy terms they are a one way valve.
current.
Forward bias: if the voltage from anode to cathode is positive the
Water
diode will conduct and is said to be forward biased. anode
There will be a fixed forward voltage drop that depends on the
Illustration 44: Diode Analogue
material, typically 0.65 volts for silicon.
Reverse bias: if the voltage from anode to cathode is negative
the diode will not conduct and is said to be reverse biased.
There will be a leakage current back through the diode which
depends on the technology, typically nanoamps for silicon.
A diode must be inserted the right way, it is a polarized Illustration 45: Diode Images
device. Note the bar on the diode bodies which matches the
bar on the diode symbol cathode.
DIODE VI CURVES show how the device

behaves very differently in forward and reverse
bias. Note the scales on the voltage and current
axis are different. An ideal diode will have zero
voltage drop when forward biased, and infinite
resistance when reverse biased. Real devices have a
finite forward voltage drop and a finite reverse
leakage current.
Most diodes used today are silicon (Si) and as a rule
of thumb drop 0.65 v in the forward mode at low
currents, and from 0.7 to 1.2 volt at higher currents. Illustration 46: Diode VI Curve
Germanium diodes can be used for small currents and have a forwards drop of 0.3 volts.
Schottky diodes ( Si-metal) have a drop of 0.1 volts.
Light Emitting Diodes (LEDs) are diodes made of

Gallium Arsenide which is a clear semiconductor. When
forward biased the generate light, anything from infra-red
to ultraviolet depending on the technology.
Most indicator LEDs require between 5ma and 50ma,
though power LEDs can take much more current to
produce very bright lights.
LEDs usually drop about 1.5 volts for red going up to 2.3 Illustration 47: LED Connections
volts for yellow and green. UV LEDs can drop 3.3v and
high power LEDs at high currents may drop more voltage.
Note the anode is longer lead on a new LED.

BIPOLAR JUNCTION TRANSISTORS

(BJTS) are current amplifiers and may be NPN Transistor
used as on-off switches where a small Controlling collector Water Analogy
current into the base (perhaps from a current. Controlled
microprocessor) can switch a large current base current.
in the collector (perhaps a light bulb). emitter
Control
In water analogy terms a BJT is a water
valve where a small current is used to set PNP Transistor
the valve which controls a much larger Controlling collector
current. current.
Water
Controlled
Common bipolar transistors can switch base current.
currents ranging from microamps to 20 emitter
amps. The beta ( β) ranges from 20 to Illustration 48: BJT
around 300.
Ib Ic
c
b
0.65v
e drop
e.
Ic = β * Ib
Illustration 49: NPN BJT Model
Illustration 50: Bipolar Transistors
Example: in the BJT drive circuit

opposite the 555 timer outputs a
square wave that is between zero
volts and +5 volts. For zero volts
output no current flows through the
base, and so no current flows
through the collector.
For +5 volts output the current
through the base is-
(5v-0.65v)/220Ω = 0.02 amps
= 20 milliamps.
Illustration 51: BJT Drive Circuit
If the gain ( β) of the BJT was 100
then up to 2000 milliamps or 2 amps could flow through the speaker. The resistance of the
speaker acts as a current limit and the maximum current that may flow is 5volts/Rspeaker.
You will need to learn how to do these basic calculations.

FIELD EFFECT TRANSISTORS (FETS) are similar

N Channel MOSFET
to BJT except the control pin is sensitive to voltages not
currents. A FET is a voltage to current amplifier. drain
The gate voltage must move beyond the threshold voltage + gate Controlled
Controlling current.
Vt to get any current to flow. MOSFETs are more voltage.
complicated that the simple linear model shown below - source
but this is a good mental model to start with.
P Channel MOSFET
MOSFETs are better at handling high power and high
drain
frequencies than BJTs. BJTs tend to be cheaper than an
equivalent MOSFET. - gate Controlled
Controlling current.
voltage.
Packing for MOSFETs looks very similar to BJTs, only + source
the part number marking is different. Illustration 52: MOSFET Device
Many types: there are many types of FETs, and d g Id

some variation in how they are drawn. Later g
courses will explain these details. Vg Rds
s
.
Id = gm * (Vg – Vt) , Vg>Vt
Illustration 53: MOSFET Model
H Bridge: DC motors are often controlled with a MOSFET

based H bridge. In the diagram opposite the motor will turn
one direction with MOSFET A and D turned on, and the
opposite direction with MOSFET B and C turned on. In a
later course you will learn how to design the complete circuit
for an H bridge.
Question: what could go wrong and how could digital
electronics solve the problem?
Illustration 54: MOSFET H Bridge

2.8 Capacitors
A capacitor is a 2 terminal device that
Water tank Capacitor Symbol
stores electric charge, usually by having two analogy. construction.
conducting surfaces close to each other.
Using the water analogy a capacitor is like a Water
large water tank with an outlet at the bottom. Water
• The water pressure at the tank outlet is
Illustration 55: Capacitance
like the voltage across an electronic
capacitor.
Hydraulic Diaphragm
• If the outlet is opened then a lot of water (electricity) Model of Capacitance
can be supplied at the given water pressure (voltage).
If the the outlet is open a long time the water level and
water pressure fall.
• A tank can be emptied, or filled up via the outlet.
ELECTRONIC CAPACITORS have key properties-

A.C. current flow.
• Capacitors try to keep the voltage across themselves Illustration 56: Diaphragm
constant and will supply or absorb current to achieve Capacitor Model
that goal.
• Capacitors will not let DC current pass, only the AC component. This feature is often used
to block DC and pass AC.
• The defining equation of a capacitor is I = C dv/dt
I = current, C is capacitance measured in farads,
dv/dt is the rate of change of the voltage across the capacitor.
• The energy stored in a capacitor is E = 1/2.C.V2 C in farads, V in volts, E in joules.
MULTIPLE CAPACITORS: capacitors can be put in series or parallel, the resulting

capacitance is-
Total of Parallel Capacitors=C1C2C3 ...
1 1 1 1
=   ...
Total of Series Capacitances C1 C2 C3
In a similar manner to resistors, a complex network of capacitors can be reduced to one

capacitor value by using the equations above.

CAPACITOR TYPES: there is a huge variety of capacitors varying from picofarads (10-12 of a
farad) to thousands of farads. There are also many different construction methods which leads
to different properties. There are two types you will be dealing with-
• Ceramic capacitors may look like any of the seven left hand capacitors in the diagram
below. They can be inserted in either direction. Ceramics are usable at high and low
frequency.
Common values are between 10 picofarad (pf = 10-12 of a Farad) and 100 nanofarad ( nF =
10-9 of a Farad).
• Electrolytic capacitors are general of larger value but do not work well at higher
frequencies. The three right hand capacitors below are typical electrolytic capacitors.
*** Electrolytics are polarized, the + lead must be connected to a voltage more positive
than the other lead. Some capacitors label the negative lead (-) instead.
Common values range from 10 microfarad (uF = 10-6 Farad) to a Farad.
Illustration 57: Capacitor Types
VALUES: most capacitors have their value written on them, though working out what the
marking means can be difficult. A few have color bars and can be read as per the resistor color
code.
Capacitors often have a maximum rated voltage (note the red capacitor above). Exceeding this
voltage may cause damage.
RESISTOR CAPACITOR CIRCUITS can be used

to shape waveforms, create delays, and selectively
filter different frequencies. You will learn more about
this in other courses.
The circuit opposite is a Low Pass Filter (LPF). It will 0v
pass DC and low frequencies but block higher Illustration 58: RC Circuit
frequencies.

2.9 Inductors
An inductor is a two terminal device that
stores energy in its magnetic field. This field is Inductor water analogue.
created by electric current flowing through the
device.
Using the water analogue an inductor is like a
long pipe where the weight of water flowing
Water with weight and inertia.
down the pipe has a lot of inertia.
• If the water in the pipe is not flowing then it
takes some energy to get it up to speed. Inductor symbol
Illustration 59: Inductance
• If water is flowing, and the end of the pipe
is suddenly closed, then the water pressure
at the closure can rise dramatically, perhaps even bursting the outlet ( for an inductor
causing a spark or damaging a component).
ELECTRONIC INDUCTORS have key properties-

• Electronic inductors like to keep the electric current
through themselves a constant and will dramatically
change the voltage across themselves to achieve this.
• Inductors pass DC current but block high frequency
AC current.
• Inductor behavior is defined by the following
equation- Illustration 60: Typical Inductors
V = - L * di/dt
V = voltage across the inductor,
L= inductance in Henries,
di/dt = rate of change of current through the inductor. in amps/sec.
• The energy stored in an inductor is E = 1/2.L.I2 ( L in henry, I in amps, E in joules)
CONSTRUCTION: inductors are made from coils of wire and often have a ferrous core which
increases their inductance.
CAPACITORS VERSUS INDUCTORS: note they complement each other-

• Capacitors pass high frequency but inductors block high frequency.
• Capacitors try to keep the voltage across them constant, and supply or sink current to
achieve this.
Inductors try to keep the current through them constant, and will change the voltage across
themselves to achieve this (even reverse polarity!).

2.10 Switches and Relays

Switches are import input devices and have several options. Relays operate one or more
switches using an electromagnet that is activated by a current passing through a coil.
NO/NC: NO (Normally Open) switches are those that are an open circuit normally. When they
are pushed or activate the are closed to make a short circuit.
NC (Normally Closed) are the reverse way around, normally closed and open on activation or a
push.
BREAK/MAKE: a switch or contact which is open circuit is said to be in the “break” state.
A switch or contact which is a short circuit is said to be in the “make” state.
MOMENTARY SWITCHES keep their state only while

be activated. For example a NO Momentary switch will NO NC
be a short circuit while actively push, but go back to an Momentary Momentary
open circuit when a finger is removed. Illustration 61: NO & NC Momentary
Switch
LATCHED SWITCHES use the same physical action to cycle between their available states.
Some light switches are like a click biro, push to turn on, the same push a second time turns the
switch off.
NORMAL SWITCHES must be actively moved from one position to

another but will stay in that new state after the activation has been
removed.
NO NC
Illustration 62: NO
SPST … The switches shown above are SPST, Single Pole (source) & NC Switches
Single Throw (destination).
An individual switch may have more than one destination, and switches
may be ganged together and all operated together and so have multiple
sources. The SPDT (Single Pole Double Throw) and DPDT (Double
Pole double Throw) switches are shown opposite.
SPDT DPDT
The DPDT is useful particular with mains electricity as both the active Illustration 63: SPST
and neutral can be disconnect from a destination which enhances & DPDT
safety.

ROTARY SWITCHES are commonly used to have many throws

for each input pole.
Illustration 64: Rotary Switch

V & I LIMITS: switches all have voltage and current limits. If the voltage is too high there
may be electrical arcing. If the current is too high then the mechanical contacts will be
damaged by sparking or electrical heating.
Driving a large capacitive load is a problem as capacitors can supply a lot of current and
damage the contacts. A series resistor is often used to limit the current.
Driving a large inductive load is a problem as when the inductor is turned off it can generate a
spark and damage the contacts. Diodes are often used to allow a path for the inductor current.
MECHANICAL RELAYS activate switches by using a

small electromagnet. An electric current must pass
through the coil to activate the device.
Relays can be used for logic operations. From around
1900 to 1960 telephone exchanges were relay based.
There is high electrical isolation between coil and switch
so that a coil may trigger on 5 volts, and the switch 240v
AC.
Illustration 65: Relay Internals
REED RELAYS have two very thin and flexible contacts

inside a tube filled with an inert gas. Such relays cannot
carry much current but to not oxidize due to arcing. The
low inertial also means fast operation and a smaller
magnetic field to close the switch.
Reeds by themselves are often used to detect mechanical
movement, for example a magnet on a wheel may pass by
and so activate a reed element. Illustration 66: Reed Relay

2.11 Integrated Circuits

Integrated Circuits (ICs) are one of the key breakthroughs of modern electronics. In the
1950's it was discovered how to put multiple transistors onto one wafer of semiconductor.
See http://en.wikipedia.org/wiki/Integrated_circuit
MOORE'S LAW: in the early 1960's competitive pressures encouraged manufacturers to cram
more and ever smaller transistors onto a chip to get more complex functionality, lower costs,
and lower power drain. This led to Moore's law ( Moore was the joint founder of Intel); that
transistor density would double every two years. Moore's law has led to the most amazing
growth in digital IC complexity and decreased costs of manufacture.
Illustration 67: Moore's Law
THROUGH HOLE ICS: the first ICs used 0.1

inch pitch for their legs and this standard is still
used. The DIL package (Dual In Line) had two
rows of pins (see the large 8 pin packages
opposite). DIL packages sizes are commonly
8,14,16, 18, 20, 24, 28, 32, or 40 pins.
SURFACE MOUNT packages solder onto the

board and do not have pins going through the
board. They allow even greater densities and
reduce costs. The smallest components are 0.1mm
in size.
Illustration 68: IC Packages

HUGE DEVICES: devices such as the top

end microprocessor may have 1000 pins.
There are a variety of package types to cope
with huge pin-outs, the Ball Grid Array
(BGA) being one of the largest.
These packages cannot be soldered by hand
and require expensive and sophisticated
manufacturing equipment.
Illustration 69: BGA Package

2.12 HC Logic
The labs will use the HC logic family and this section will introduce you to the basics of
how these gates work. The later chapter on Digital Electronics will explain logic gates in detail.
THE IC: most of the

devices you will be
using are 14 pin DIL
(Dual In Line) packages,
two rows of 7 pins.
The logical diagram at
the right shows how the
notch denotes the head
of the IC with pin 1 to
the left of the notch.
This gate has four
independent NAND
gates. For example pins Illustration 70: HC00 IC
1 and 2 are inputs and
pin 3 is the resulting output.
POWER: the IC needs power to function properly. For the NAND gate above pin 7 must be
connected to zero volts, and pin 14 to +5 volts. This power can come from the clock board.
INPUTS AND OUTPUTS: +5 volt HC logic inputs must be Pin 1 Pin 2 Pin 3
driven either high ( > 3.5 volts) or low ( < 1.5 volts). The
0 0 1
output will be either high or low and depends on the inputs
as per the following truth table. 0 1 1
1 0 1
1 1 0
BASIC CONNECTIONS: the image below shows some
basic connections to get the power to the IC and drive the
inputs. The inputs and output can be observed with a multi-
meter, or a series resistor and LED.

EEET-2251 Digital Systems Design 1 : Digital Electronics
3 Digital Electronics
In digital electronics the state of any point
240v AC Mains Logic
can be considered to be a zero or a one. With most
logic implementations, the logical state corresponds A B
to a voltage range. Z
These ones and zeros may be manipulated by logic 240v Lamp 1 = 240 volts.
gates to achieve a given purpose. In the diagram mains 0 = 0 volts.
opposite the switches and the HC logic gate are
performing the same function; only when both
inputs A and B are active will the output Z be 5 volt HC (CMOS) Logic
active. A 1 > 3.85 volts.
B & Z 0 < 1.35 volts.
Illustration 71: Logic Voltages
LOGIC GATES can be built from switches,
diodes, or bought as semiconductor gates in integrated circuits.
COMBINATIONAL LOGIC outputs depend solely on the inputs and have no memory of past
events. There is no feedback path from an output back to the inputs.
SEQUENTIAL LOGIC outputs may depend on inputs plus the memory of past events. To
achieve this memory there will be some feedback of an output back to the inputs.
BINARY: digital logic uses the binary number system. If you have not been introduced to this
before please read the appendix section which talks about number systems.

3.1 Combinational Logic

The basic gate types of digital logic are shown below.
• Truth table shows the resulting output for every possible input combination.
• Symbols: the drawing symbol used for the gate in schematic diagrams.
• Boolean logic is a mathematical description of a logic function where all variables can only
take on the values 0 (false) or 1 (true).
Unfortunately there are several different ways to show the one logic function.
• Switch and diode circuits can be used for real implementation and also give a good feeling
for what the gate achieves.
SWITCH NOTATION: switches shown as open are called Normally Open and require a
logical one to close them. Switches shown as closed are called Normally Closed and require a
logical one to open them.
Gate Truth Symbol ( IEC / Boolean Logic Switch & Diode Equivalent
Table ANSI) Alternatives
AND A B
AB Z Z=A.B
Source Load
00 0 Z=A*B
01 0 Z = AB
A
10 0 Z=A&B +voltage
11 1 Z=A^B B
A&B
Z=1 if all Z = A AND B
inputs=1. 0v
OR Source
AB Z Z=A+B A
00 0 Z=A|B B Load
01 1 Z=AvB
10 1 Z = A OR B A
11 1 0v
B
Z=1 if any A or B
input=1. 0v

NOT
Z = NOT A
A Z Z=A Source Load
0 1 Z=!A .
1 0 Z = ⌐A
Z = A'
NAND
AB Z Z=A.B Source
00 1 Z=A*B
01 1 Z = !( A * B)
A
10 1 B
Load
11 0 .
Z=0 if all
input=1.
NOR
AB Z Z=A+B
00 1
A B
Z=!(A|B)
01 0
Source Load
10 0 .
11 0
Z=1 if all
input=0.
XOR
AB Z Z = A XOR B A B
00 0 Z=A^B
01 1 Z=AÅB Source Load
10 1
.
11 0
Z=1 if all
odd number
of inputs =1.

XNOR
AB Z Z = A XNOR B A B
00 1 Z = ! ( A ^ B)
01 0 Z=AÅB Source Load
10 0 Z=A≡B
.
11 1
Z=1 if all
even number
of inputs =1.
MUCH MORE: many more logic functions are available in ICs that can be purchased off the
shelf. Its worth scanning through data books / web listings of logic functions.
LOGIC FAMILIES: a logic family is a range of logic devices all built with the same
technology. There are many family types but there the two you will probably come across
include-
• TTL based families are older technologies that are seldom used but still found in legacy
systems. Note the LS00 data sheet for an example of this logic.
• CMOS based devices dominate the market now because of their low power drain, high
speed, high input resistance, and good noise immunity.
All microprocessors are now CMOS and most glue logic should be CMOS.
DATA SHEETS: every digital IC will have a data sheet produced by the manufacturer. We
will work through the data sheet to illustrate key properties of real devices.
We will look at the HC00 data sheet and note-
• Truth table and logic diagram.
• The pins used for power and where the gate inputs and outputs appear.
• Maximum ratings, which may only be reached in peculiar situations.
• Recommended conditions.
• Logic levels, especially the difference between output voltages and input voltages.
• Rise time and delay of the gate.

COMMON PROBLEMS when using gates, especially in labs-

• Floating inputs: for CMOS if an input is not connected then it's voltage can drift anywhere
between the power supply and zero volts. This means any corresponding output may glitch
high or low in a random way.
*** All unused inputs must be connected to either 0v or the power supply.
• Power: all gates require power, which must be connected the right way around.
• Shorted outputs to zero volts or the power supply can destroy a gate if the output is driving
the opposite way. Most will survive several seconds before failing.
EXERCISES: use a truth table to work out the output (Z) given the inputs (A,B,C …)
1 A 1 A B C Z Y X W
A Z Y
C & C ≥1 0 0 0
C C
B & =1 0 0 1
B
0 1 0
0 1 1
C C
A & X & 1 0 0
A W 1
A ≥1 & 0 1
& A &
B B 1 1 0
C & C 1 1 1
&
B B
Illustration 72: Combination Logic Exercise
EXERCISE: you can sometimes reduce the IC count in a design by reusing gates in a novel
manner.
• Your design needs an inverter gate and you could add an HC06 package. You have a
single 2 input NAND gate free. Show two ways in which it could be used as an inverter.
• As above but you have a single 2 input XOR gate, consider also a NOR gate.
• You need a 2 input NAND gate and have one 3 input NAND gate free. Show two ways
to wire up the NAND gate to server as a 2 input gate.
FURTHER READING which may be of interest-

• Putting switches in series and parallel is not the only possible configurations. See the
link below for some other interesting topologies.
http://mysite.du.edu/~etuttle/electron/elect49.htm

3.2 Boolean Algebra

The logical operation of gates, switches and diodes can be represented in a compact
mathematical way using Boolean algebra. The rules of this algebra can be used to modify and
minimize a Boolean expression. The previous table showed several forms of Boolean algebra
that represent ideal logic gates with no delays.
LAWS: there are a number of laws that will help you manipulate Boolean algebra expressions.
Many are similar to normal algebra where AND (.) is like multiplication, and OR (+) is like
addition. The variables in the table can only take on values 0 (low) or 1 (high).
Law Meaning Expression

Association The order of evaluation does not (A.B).C=A.(B.C)
matter in these circumstances (A+B)+C=A+(B+C)
Commutation Variables may be swapped around A . B = B . A
and the result will not change. A+B=B+A

Distribution How brackets can be expanded. A . ( B + C) = A . B + A . C

A + ( B . C ) = (A + B).( A + C)
Identity AND or OR with known values A.1=A A.0=0
can be simplified. A+1=1 A+0=A
A.A=A A+A=A
Negation Complement rules. 1=0 0=1
A.A=0 A+A=1 A=A
De Morgan Can change between AND and OR A + B = ( A . B) A + B = ( !A . !B)
gates (swap AND and OR, invert A . B = ( A + B) A . B = ( !A + !B)
all inputs and the output).
EXAMPLES: starting from the left in the diagram below, use the laws above to; simplify the
circuit to one gate, determine if the NAND-AND circuits are equivalent and determine if this is
a way to make a triple input NAND (useful for your labs?). Simplify the remaining circuits.
The tutorials will give you further practice at Boolean algebra.
1 A 0 B
B & & &
A A
& &
C >=1
1 0 A
A >=1 &
& A C
C
&
B
Illustration 73: Boolean Logic Simplifications

3.3 Combinational Logic Minimization

A key skill for digital designers is the ability to minimize logic, to use the minimum
number of gates, because this minimizes cost and power consumption. There are several well
known ways to minimize logic-
• Boolean logic as in the previous section can be used to minimize logic but it is hard to
simplify more than one or two variables.
• K-maps ( Karnaugh Maps) provide a neat graphical way to minimize logic using the
human brain's pattern matching ability.
K-maps work well for up to five input variables and will give at most 3 gate deep logic.
• Quine McClusky minimization is complex tabular method of minimizing logic.
This method can cope with more than five inputs and multiple outputs but can generate
implementations which are more than 3 gates deep (which cause extra delays).
Another issue is that the calculation difficulty-
For N inputs the calculation time upper boundary is 3N / N.
• Heuristic methods: the large execution time of Quine McClusky for large values of N can
be a problem. Heuristics can give a close to optimal result with far less time. See the
Espresso algorithm as an example of this approach.
K-MAP PRINCIPLE: these notes will use Karnaugh maps (K-maps) to design and simplify
logic.
K-maps are built on the premise that any truth table can be built from a layer of AND gates
followed by a summing OR gate.
In the truth table below each row which generates a 1 is represented by an AND gate. All the
AND gates are summed using an OR gate to produce the output.
De Morgan's theorem can be used to change both gate layers to NAND gates (change the OR
gate to an AND and invert inputs and outputs, the inversion bubbles on the inputs can be
moved to the outputs of the first row of AND gates).
A A A
Index A B C Z
0 0 0 0 0
B & B & B &
1 0 0 1 0
C C C
Z Z Z
2 0 1 0 0 A >=1 A & A &
3 0 1 1 0 B & B & B &
4 1 0 0 0 C C C
5 1 0 1 1
6 1 1 0 1 A A A
7 1 1 1 1 B & B & B &
C C C
Illustration 74: AND-OR Combinational Logic Implementation
Problem: while the implementation will work it is wasting gates.

Look at the last two rows, A=1,B=1, C does not matter; 0 or 1 Z stays at 1.
The bottom 2 gates could be replaced by one AND gate, A & B.

MERGING AND GATES: K-Maps show how AND gates can be merged to save gates and
reduce the number of inputs per gate. The K-Map below represents the circuit just given.
• A K-Map is a redrawing of the truth table in a special format.
• In the diagram below note cells ABC 101 represent one 3 input AND, and 111 another
such gate.
• The blue loop around these two cells in the K-Map below shows that in reality the value of
B does not matter, but A must be 1 and C must be 1. Two 3 input AND gates can be
replaced by one 2 input AND gate with inputs A and C.
• Similar reasoning on cells 111 and 110 merges in another gate.
BC B B
& &
00 01 11 10 A Z A Z
>=1 &
0 0 0 0 0 A A
A & &
1 0 1 1 1 C C
B has no effect C has no effect

A&C must be one. A&B must be one.
Illustration 75: K-Map Minimization of Truth Table
RULES FOR USING K-MAPS

• Truth table: the full truth table for the logic function must be determined.
Don't care cells, those that could be 0 or 1, and are shown with an X.
• Gray code: the index for each row or column in the K-Map must be gray coded. There are
only two possibilities; 0,1 or 00,01,11,10.
Gray codes only change one bit between adjacent values. This should also hold true when
looping back from the last item to the first item.
• Grouping: mapping rings can loop around groups of 2,4, 8, or 16 ones. The group must
form a square or rectangle.
Mapping rings can wrap around the edges and corners because of the gray coding.
The largest group possible should be selected to minimize the logic.
Overlapping of rings is good and will help minimize logic.
• Don't care: a don't care output is shown with an X and can be set to 0 or 1.
Set X to a 1 if it helps make a larger 1 group for existing ones, otherwise set to zero.
• Extra inverters: K-Maps in theory produce two gate deep logic, but at times an extra
inverter is required to produce the inverse of a variable, for example A.
• “.” for 0: you may use a dot “.” instead of a zero “0” to make it easier to see the pattern of
ones to put into a mapping ring.
• Each ring becomes one term in the Boolean equations for the output.

EXAMPLES of mapping rings are shown below for 2 inputs, 3 inputs and 4 inputs.
Note that mapping rings can wrap around edges and corners, exams nearly always check your
ability to spot this wrapping around.
B BC CD
0 1 00 01 11 10 00 01 11 10
0 0 0 0 1 0 0 1 00 1 1 1 1
A A
1 1 1 1 1 0 1 X 01 0 1 1 1
AB
11 0 0 0 0
Z=A Z = C + A.B 10 1 1 1 0
CD
00 01 11 10 Z = A.D + A.C + B.C + B.D
00 1 . 1 1
01 . . . .
AB
11 . . 1 . Z = B.D + A.B.C + A.B.C.D
10 1 . . 1
Illustration 76: K-Map Examples of Mapping Rings
MAXIMUM SIZE: always chose the mapping

W CD X CD
ring which is largest as this will reduce the
complexity of the Boolean logic, and the 00 01 11 10 00 01 11 10
eventual implementation in logic gates. A one 00 . 1 1 1 00 . 1 1 1
can be mapped any number of times. 01 1 1 1 1 01 1 1 1 1
In the diagram opposite W is mapped but the AB AB
11 1 1 1 1 11 1 1 1 1
ring size has not been optimized. X to the right
10 1 1 1 1 10 1 1 1 1
has it's mapping rings as large as possible and
this results in a simpler Boolean equation. Illustration 77: Non-mi9nimal and Minimal Mapping
Can you work out the Boolean equations for W
and X to verify this claim?

FIVE VARIABLES is possible by looking for echoes between two K-Maps.

• Draw K-Maps for each with a echo line between the two as shown below.
• Draw mapping rings for each individual K-Map.
• Look across the echo line to see if any mapping ring or individual one bit is matched across
the boundary.
If there is an echo then the value of E does not matter and E it can be removed from the
term.
• Do not try wrapping rings between the two K-Maps! This is not valid, only the echo is
valid.
Echo Line A 1
D &
E=0 E=1 C
CD CD A
C Z
00 01 11 10 00 01 11 10 Echoed & &
D
00 0 0 1 0 0 0 1 0 Group. B 1
A 01 0 0 1 0 0 0 1 0
A
B 11 0 0 0 0 0 0 0 0 Z = CDA + ABDE + CDAB &
D
10 0 0 1 0 0 1 1 0 E
Echoed one.
Illustration 78: Five Variable K-Map
Consider the mapping ring C.D./A in the figure above. The reasoning for this term is as
follows-
• Looking at the rows the value of A must be zero, the value of B does not matter, thus /A
must be in the term.
• Looking at the columns C and D must be one thus the term becomes C.D./A
• The ring is echoed between E=0 and E=1 K-maps so E does not matter and does not
need to be in the term.
ECHOING is not the same as wrapping around. The

E=0 E=1
mappings opposite are all wrong and result in wrong
CD CD
equations. 00 01 11 10 00 01 11 10
Wrapping around only works on K-Maps up to 4 00 1 . . . . . . 1
variables in size. In 5 variable K-Maps it can only be AB 01 1 . . . . . . 1
used within each individual 4 variable K-Map and not 11 . . . 1 1 . . .
between the two 4 variable K-Maps. 10 . . . . . . . .
Illustration 79: Erroneous Echoing

PRACTICE: K-Maps are best learned by practice. You will practice them in the labs and
tutorials. The worked problems at the end of these notes will help you a great deal and ensure
you learn key ideas. Try other sources of worked problems until you feel you have mastered
the technique.
K-MAP CHECK: this checking rule may seem a little complex

# K-Map 1 bit # inputs
at first. If so leave it, play more with K-Maps, and then come
Variables group to AND
back.
size gate.
The translation of K-Map to Boolean algebra is error prone so
5 16 1
it's worth taking care and making checks.
5 8 2
The idea of K-Maps is to find the biggest groups of ones that
you can. When doing this, count the number of each type of 5 4 3
group; the number of single ones, groups of two ones, groups of 5 2 4
4 ones, and 8 ones. Use the table opposite to work out the
5 1 5
number of inputs for the AND gate that implements each ring.
4 8 1
Consider the five variable k-Map on the last page. There were
two groups of two 1s, and one group of 4 ones. Using the table 4 4 2
opposite for a 5 variable K-Map, there should be two AND 4 2 3
terms with 4 variables, and one AND term of 3 variables.
4 1 4
3 4 1
3 2 2
3 1 3
2 2 1
2 1 2
TRUTH TABLE TO K-MAP: it is very easy to make a mistake when translating the truth
table to a K-Map. One way to reduce errors is shown in the work sheet below.
• Fill in the output(s) for each row in the truth table.
• Note the top K-Map shows the position of each truth table index in the K-Map. Use this as
a guide to translate each row of the truth table into the K-Map.
• Apply mapping rings as described and write the Boolean equations for each output.
If your problem does not need five variables then fill up the truth table as necessary and ignore
the unused cells in the K-Map.

Index Inputs Outputs

ABCDE X Y Z Cell Position Map
0 00000 Echo Line
1 00001
2 00010 E=0 E=1
3 00011 CD CD
------------------------- 00 01 11 10 00 01 11 10
4 00100 00 0 2 6 4 1 3 7 5
5 00101 01 8 10 14 12 9 11 15 13
6 00110 AB
11 24 26 30 28 25 27 31 29
7 00111 10 16 18 22 20 17 19 23 21
-------------------------
8 01000
9 01001 X E=0 E=1
10 01010 CD CD
11 01011 00 01 11 10 00 01 11 10
------------------------- 00
12 01100
01
13 01101 AB
11
14 01110
15 01111 10
-------------------------
16 10000
Y E=0 E=1
17 10001 CD CD
18 10010 00 01 11 10 00 01 11 10
19 10011 00
------------------------- 01
20 10100 AB
11
21 10101 10
22 10110
23 10111 Z
------------------------- E=0 E=1
24 11000 CD CD
25 11001 00 01 11 10 00 01 11 10
26 11010 00
27 11011 01
AB
------------------------- 11
28 11100 10
29 11101
30 11110 5 Variable Truth Table to K-Map Worksheet
31 11111 5 Variable Truth Table to K-Map Worksheet

44Variable
VariableTruth
TruthTable
TabletotoK-Map
K-MapWorksheet
Worksheet
Index Inputs Outputs Cell CD

Position 00 01 11 10
ABCD WXYZPQ Map 00 0 1 3 2
0 0000 01 4 5 7 6
1 0001 AB
11 12 13 15 14
2 0010
10 8 9 11 10
3 0011
----------------------
4 0100 W CD X CD
5 0101 00 01 11 10 00 01 11 10
6 0110 00 00
7 0111 01 01
---------------------- AB AB
11 11
8 1000 10 10
9 1001
10 1010
11 1011
Y CD Z CD
----------------------
00 01 11 10 00 01 11 10
12 1100
13 1101 00 00
14 1110 01 01
AB AB
15 1111 11 11
10 10
P CD Q CD
00 01 11 10 00 01 11 10
00 00
01 01
AB AB
11 11
10 10

3.4 Simulators
Consider you have designed and built a digital circuit. You power it up and ... it doesn't
work! Is the mistake in the design, or the construction? Where do your start to fix the
problem? Do you just rebuild it and hope?
When a problem is too big then find a way to reduce the size or scope of the problem. In this
case you can use a simulation tool check the design works, and if it does not then quickly
redesign the circuit until it does work. With full confidence that the design is right then any
problems with the real circuit are due to construction and you can use hardware debugging
methods to find the fault (see the section on Testing & Debugging).
LOGISIM is a simple
simulator with a small learning
curve that suits this course.
Quick start learning path-
• Use the live Linux USB
as this has all the tools
and examples set up.
• Double click on the
Extras folder and
navigate to EEET2251
and the More folder.
• Double click on any
*.circ files, start with the
simple_logic.circ file.
• Click on the hand (top Illustration 80: LogiSim Simulator
left) and then click inputs
(square boxes) and observe changes in the circuit.
• Click on the pointer (top left) and then on an input (box), output (circle), or gate and
change properties such as the label and position.
• Read the help file which is excellent.
• Try to build a few very simple circuits yourself.
REALITY MISMATCH: simulators never match reality exactly and you need to be aware of
their limitations and oddities.
In Logisim the D flip-flops have a preset and reset on the bottom edge but these are active high
not active low like your HC74 flip-flops. Your simulation must add an inverter to match the
real flip-flop.
FAILURE WARNING: the vast majority of students who fail this course do so because they
cannot get the labs working. The root cause is that they do not learn to use the simulator and
they do not learn how to debug their circuits with a multi-meter.
Don't let this fate befall you, take the time to learn the simulator and how to debug.
3.5 State Diagrams

Combination logic is limited by a lack of memory of past A STATE is a unique
events, so next we will examine logic that has memory. Before condition of a system
looking at such logic we need a method to express how a system
behaves in time. The ideal method is the state diagram which will be
described in this section.
A single
A STATE is simply a unique condition of a system. The system traffic
light has
output depends on the state, and may depend on external inputs as several
well. legitimate
states,
including
inactive.
A STATE DIAGRAM shows how the system moves between states
given some stimuli. This stimuli might be a clock edge for digital
electronics, or a call to a function for a software implementation.
State diagrams are also called "transition graphs" or "transition diagrams".
A FINITE STATE MACHINE (FSM) is a software or hardware implementation of a state

diagram where there is a finite number of memory elements.
WHEN TO USE : state diagram design is particularly appropriate whenever-

• Waiting conditions : a system has a distinct set of "waiting conditions" ( states), and
distinct transitions between these states. Operation is fixed in a given state until a
transition condition is satisfied and then a new state is entered.
• History is important : if the processing of an input is dependent on the history of what has
happened in the past then state machines are a possible solution. The state variable(s)
becomes the memory of the past.
• Minimum memory : state diagrams pack the maximum functionality into minimum
memory. Digital electronic design makes frequent use of state machines for exactly this
reason as the number of flipflops and gates can be minimized.
• Fast multi-tasking : a software state machine can be written such that it completes a single
state change (or no change) and then immediately returns. This is a very quick operation.
Several state machines can be called sequentially to achieve fast multi-tasking. This is
usually much quicker than using a Real Time Operating System RTOS, and uses far less
memory. Many microprocessor based systems use multiple state machines to achieve real
time control.
EXAMPLES of problems dominated by state machines include traffic lights, vending

machines, electronic door locks, alarm systems, lift controllers, turnstile controller, and
Internet protocols.
The control of most mechanical systems require some type of state machine.

MOORE STATE DIAGRAMS are State name or value.

the most common form of state Outputs.
diagrams. Input that
• Each box is a state, a unique allows transition
system condition. The system
must be in one only of the states Start Fill Tank (01)
Idle (00)
V, L=10
shown. V, L=00
Stop
• The first line in each box is the Stop Full Idle
state name and/or number.
Tank Full (11). Stop
• The second line in each box is the V,L=01 <½ Full
output which is purely a function Tank Refill (10)
Full
V,L=11
of the current state.
• Each vector lists a condition, V=Fill Valve, L= Indicator Light
based on external input/s, that must Start, Stop = buttons.
be true before the vector may be Full, <1/2 Full = level indicators.
followed to change the state. Basic plot: on start fill the tank, when empties
If a vector has no name ( no text to 1/2 full then fill to the top again.
label) then it is considered to be
true and always followed. Illustration 81: Moore State Diagram for Feeder Tank Filler
• Clock: for digital logic, when the
clock triggers (for example a rising
edge) then if a vector is true the state changes. The outputs change at the same time the
state changes.
If no vector from a state is true then there is no state change.
• State dictionary: in larger systems a state dictionary is needed to explain the meaning and
details of each state, output, and input condition.
There is a wide variation in drawing conventions, states may be circles or squares but they
always list a state identifier and usually the outputs. Vectors are always labeled with the
condition that must be true before the transition can be followed.
In general the state numbering and outputs should closely matched in order to reduce the logic
required to generate the outputs from the state. In the example above can you renumber the
states to exactly match the outputs?
Input2/Output2 Input3/Output3
MEALY STATE DIAGRAMS allow the output to be a

function of the state and the inputs. This can simplify a State name or value.
digital circuit and may reduce the numbers of states
required. Input1/Output1
In the diagram opposite the vector serves two purposes-
Illustration 82: Mealy State Diagram
• The transition which may occur on the next clock.
• The outputs for the current state given the current inputs.
The outputs can change as the inputs change and do not have to wait for a state change. This is
one of the main reasons for choosing a Mealy state diagram over a Moore state diagram.

EXTENDED STATE DIAGRAMS are

Syntax for Extended State Diagrams
intended for software and makes use of extra
features not available in digital hardware-
State_Name
Transition_Name
• Each state has a list of actions executed Repeated_Action_1()
Once_Only_Action_1()
Repeated_Action_2()
continuously while in that state. Repeated_Action_3()
• Each transition has a list of actions
executed only once as the transition is
triggered.
• There may be other variables including Start
counters that can simplify a state diagram. Once_Only_Start_Action_1()
...
A transition or action name may appear in Terminate_1
several places. State names must be unique. Once_Only_End_Action_1()
The brackets () show which labels are actions. ...
Control source : regular 100 ms call.

State variable name : variable_name_used_in_code
ACTIVATING A STATE DIAGRAM : a Illustration 83: Extended State Diagram
software state machine is started by initializing
the state variable (usually a simple integer) to a set value and then executing the functions on
the start vector. The following algorithm, usually referred to as a step, is continuously executed
until the state machine is terminated-
• All “repeated action” functions within the active state are called and the state variable is
unchanged.
• The transitions (functions which return true or false) out of the current state are executed
and the first to test true results in all its “once only” functions being called and the state
variable being changed to the new state value. If no transition is true no state transition
occurs.
A state machine implementation may choose to swap the order of these two sub-steps thus
repeated actions don't get called if there is a transition. Each state may also add the functions
do_on_entry() and do_on_exit().
ACTIVATION CAUSES : a software state machine can be driven by a variety of control

sources. Each time the control source calls the state machine, the algorithm above ( a state
step) is executed once. Control source types include-
• The regular call : higher level software will call the state diagram code at a regular fixed
periodic rate, for example every 100 ms.
• Irregular call : similar to the regular call but the period between calls is not fixed or
reliable.
• Event driven : higher level software has determined that an event has occurred and it calls
the state diagram with that event as a parameter.
• Combinations of the above are also feasible.
The source(s) of control are usually written as an annotation at the bottom of the state diagram
along with the state variable name.

SOFTWARE IMPLEMENTATION can be achieved using switch statements, or state tables.

The switch method is shown below.
enum state { INITIALIZE, STATE_1, STATE_2} ;

int current_state ;
void drive_state_one_step() //----------------------------

{ switch ( current_state)
{case INITIALIZE: // code to do any initialization.
current_state = STATE_1 ;
break ;
case STATE_1 : // code to cope with STATE_1
break ;
case STATE_2 : // code to cope with STATE_2
break ;
//more states
default : // cope with state being invalid.
} ;
}
void continuously_drive_state_machines() ; //------------

{ current_state = INITIALIZE ;
while ( 1) // a forever loop.
{ drive_state_one_step() ;
drive_state_machine_2() ; // can do many state machines
drive_state_machine_3() ;
}
}
FEATURES of this program fragment include-

• Control flow : each state's code segment does something and then finishes as quickly as
possible. Control will be returned very soon via the while loop and the switch statement.
• Simple : the concept is simple and easy to understand.
• Multi tasking is easy, the while loop calls several state machines one after the other. If all
state machines are written properly (do something and finish quickly) then it appears to a
slower observer that all state machines are operating simultaneously.
*** Multi tasking in this manner has the lowest computing overheads of any multi tasking
mechanism and is essential for many microprocessor programs.

SIGNAL POLARITY: the label on a vector names a condition that must be true before that
condition can be followed. For a software state machine the polarity is obvious, the vector
represents a function which must return TRUE in order for the vector to be followed.
Hardware state machines are less clear and it is easy to make mistakes. There are two useful
conventions to clarify a hardware state diagram-
• “-L”: Active low signals all have “-l” or “-L” on the end, for example RESET-L requires a
logic zero to cause the reset condition to be active.
Active high is assumed if there is no “-L” but “-H” or “-h” can clarify a name.
• Case: active low signals are lower case, or start with lower case, and active high signals are
upper case, or start in upper case. For example “Reset” or “RESET” is active high, “reset”
active low.
A term such as RESET is the logic inversion of RESET and RESET=0 indicates the reset
function is active.
This approach is useful in that signals can be reduced to one or two letter abbreviations
which can make diagrams and tables much simpler, for example “R” is active high reset
and “r” is active low reset.
*** When you draw hardware state diagrams it is strongly recommended that you use the
“case” method of showing polarity. This really will help you reduce mistakes.

3.6 Sequential Logic

Combinational logic is very useful but it lacks any memory of past events which is
essential for solving many problems. Sequential logic has memory elements which allows it to
generate outputs based on current inputs and memory of past events.
LEVEL MODE SEQUENTIAL LOGIC feeds the output +5v Set

of a gate back into an input of another gate. Level mode is Q
fast and uses a small number of gates but is difficult to &
design particularly for larger problems. Poorly designed
+5v Q
circuits may generate a different outputs due to variations Reset &
in gate delays (the timing race problem).
Level mode logic is also called asynchronous logic.
The SR flipflop opposite is a level mode circuit and is used S R Q Q
extensively in digital circuits. When S and R are high the 0 1 1 0
flipflop keeps its previous state. If S pulses low then the 1 0 0 1
Q goes high and stays there. If R pulses low Q goes to low 1 1 last value
and stays there. SR flipflops for the basic memory cell 0 0 1 1
used in other flipflops. They are also very useful for
capturing pulses from such things as momentary action Illustration 84: RS Flipflop
switches.
PULSE MODE SEQUENTIAL LOGIC: changes in inputs cause pulses which change the
state of memory elements. This form of sequential logic is seldom used.
CLOCK MODE
SEQUENTIAL
LOGIC uses
flipflop elements,
each of which can
store one bit of
information. The
only time an output Illustration 85: Rising Edge Triggered D Flipflop
can change is on
either the rising or falling edge of the clock input. Usually all the clock inputs are connected to
a master clock.
Clock mode logic is often called synchronous logic as usually all flipflop clocks are connected
together so all memory elements change at the same time. These circuits can be best modeled
by an FSM (Finite State Machine) for both analysis and design.
THESE NOTES will show how to design clock mode sequential logic (synchronous logic).
While not quite as fast as level mode it can be used to make much larger systems and is much
easier to design.

3.6.1 Synchronous Logic

Synchronous logic is a type of sequential logic that uses flipflops as memory elements.
Before looking further it is essential to understand these flipflops.
D FLIPFLOP: the D flipflop is a key memory element used in Next

synchronous logic. The function can be best explained by P
D Q D Q Q
looking at the HC74 data sheet. Note especially-
0 0 1
• The reset and clear pins as asynchronous, they operate Q 1 1 0
irrespective of the clock. R
• The input D is transferred to the output only on the rising
edge of the clock. Make sure you understand the waveforms Illustration 86: D Flipflop
in the data sheet.

• The output holds its value and only changes in response to the reset and preset pins, and
the value of D on the rising edge of the clock.
• The data must stay stable for a short period before the clock edge (a set up time) and a
short period after the clock edge (hold time).
If the setup or hold time is violated then the output may produce a glitch ( a short pulse).
T FLIPFLOPS are not commonly used and are not

available in standard logic ICs. The next state is an P Next
exclusive OR of the T input and the current state. T Q T Q Q
0 0 0
Q 0 1 1
R 1 0 1
1 1 0
Illustration 87: T Flipflop
JK FLIPFLOP: the JK flipflop is much like the D Next

flipflop except that there are two inputs, J and K, P
which can be used to simplify input logic. See the J Q J K Q Q
HC73 data sheet and note especially- 0 0 hold
K
• The clock is active on the falling edge not the Q 0 1 0 1
rising edge. R 1 0 1 0
• Note the setup and hold times on the waveforms. 1 1 toggle
• Look at the other times, for example the Illustration 88: JK Flipflop
minimum pulse width for reset.

SYNCHRONOUS
COUNTER: flipflops are often
used to make counters where
the outputs always change at
the same time.
The counter opposite is a 3 bit
binary counter using JK
Illustration 89: Synchronous Counter
flipflops.
ASYNCHRONOUS
FLIPFLOP CIRCUITS are
common and can provide a
simpler circuit but the outputs
do not change at the same
point in time. These counters Illustration 90: Ripple Counter
are often called ripple counters
as the outputs change one after the other up the chain of flipflops. The ripple counter above is
about to make the transition from 3 to 4 (least significant bit is on the left). Bit 0 will change
first, then bit 1 and finally bit 2 (on the right). The change from 110 (3) to 001 (4) will go
through several short intermediate states; first 010, then 000, and finally 100.
If it is not acceptable to have short periods where the state is wrong or changing then ripple
counters are not a suitable implementation.

Next State Table

+5v
+5v Current Input Next
FF0
FF1 P State State
P
≥1 D Q Q1 Q0 D1 D0 Q1 Q0
D Q
0 0 0 1 0 1
CLK Q 0 1 1 0 1 0
Q
R 1 0 0 1 0 1
R
1 1 0 0 0 0
+5v
+5v Q1 Q0
State Transition Diagram
Timing Diagram Q1Q0
CLK 00 01
Q0
Q1 11 10
Illustration 91: Basic Tools for Clock Mode Logic
KEY STEPS to analyze a synchronous circuit include-

• The circuit diagram must be clear including any resets and presets.
• The next state table lists all possible states (all combinations of the flipflop outputs), any
external inputs, the resulting flipflop inputs, and the next state when the clock edge
triggers the flipflops.
• A state diagram: for each current state draw a state box. For each state look at the possible
next states and draw vectors from each state to the next state.
Each vector shows the change that happens on the next clock edge. Vectors may be
labeled with the external input conditions that must be true before the vector can be
followed.
The diagram above shows a surprising result; state 11 is a lockup state, if the circuit
happens to get into this state, perhaps on power up, then it cannot escape.
• A timing diagram which shows the waveforms of key circuit nodes given an initial state
and any external inputs.
It may be necessary to use a number of timing diagrams to cover every possible state and
transition.

FORMAL MODEL of a Synchronous (Clock Mode) sequential circuit is shown below.

External Flipflop
Inputs Inputs Outputs
Input
Input Flip
Flip Output
Output
Logic
Logic Clock flops
flops Logic
Logic
State (Flipflop Outputs)
Illustration 92: Formal Model of Synchronous State Machine
A DESIGN METHOD for synchronous logic is as follows. (Use this in your labs.)
• Define the problem: consult your client, look at other systems, look at all operational
modes, think of all failure modes. Define all inputs and outputs.
• Draw a state diagram that represents the system. Try to number the states such that there is
a close match to the required outputs in order to minimize the output logic.
• Check feasibility: the number of state bits required ( and thus flipflops required) is-
# state bits = roundup( log2N) where N is the number of states.
For example 4 states requires two flipflops, but 5 to 8 states requires three flipflops.
Now check the number of input bits.
If ( #input bits + #state bits) > 5 then K-Map techniques cannot be used to design the
flipflop input logic. In this case see the topic below “Reducing State+Input Bits”.
• Draw a state table based on the state diagram as follows. If using D flipflops the required
flipflop input is the same as the next state so these two columns can be merged. Use the
don't care state X where possible to simplify the logic and compress several rows together.
See the synchronous logic example to see some very useful rules for creating a truth table.
Index Current State Outputs FF Inputs Comments

+Inputs =Next State
Q1 Q0,a b,C X,y,Z D1D0
0 00,00,0 00
1 ...
• Output Logic: the outputs depend purely on the state (unless a Mealy model is being used)
so for each output bit design combinational logic that converts the current state as inputs to
the desired output bit. Consider state renumbering to simplify this logic.
• Input logic: for each flipflop input bit design combinational logic which takes as inputs the
current state and the external inputs, and outputs the flipflop input bit as required.
• Draw a circuit for the complete state machine.
• Simulate, either by hand or by computer to ensure it works as intended.

REDUCING INPUT/STATE BITS is essential to simplify the hardware and to keep the input
logic design simple enough to design with K-Maps. Some useful techniques include-
• Reset and preset: your flipflops may have a reset and/or preset pin. Consider using this to
achieve a known, usually stop/idle state. This may eliminate one input from the state
diagram.
For the tank filling example the End switch might be connected to the reset pin of all
flipflops thus reducing the state+input bits from six to five.
• Combine inputs: find ways to combine inputs. In the tank filling example the End and
Begin switches are two momentary action switches. Consider this as one switch which has
two positions, start (1) and stop (0). This eliminates one more input bit. Given that End
forces the idle state via reset then the Begin input may not be necessary thus both the Begin
and End inputs have been eliminated from the state diagram.
• SR captures pulses: if the input is a pulse then the state machine must remember the pulse
has occurred and this takes extra states. A separate SR flipflop can capture the pulse, for
example a low pulse on the S input, and turn it into a constant level. At some point the SR
flipflop must be cleared by pulsing the R input.
• Merge states if possible. This may require small changes to the functionality.
• Mealy? Check each output to see if it is dependent on inputs. If so try to create output
logic that uses inputs and the current state and see if that produces less states and so less
flipflops.
• Separate Timer: consider a situation where a delay is required and this is achieved by
using several states in a row. This might be replaced with a separate timer which starts
when a given output becomes active, and supplies a timeout input to the state machine.
• Quine-McClusky and other minimization methods can be used.
REDUCING BITS FAILS: as problems get more complex it becomes impossible to reduce
the (#state bits + #input bits) to a reasonable value. Possible solutions include-
• Algorithmic State Machines (ASM) use addressable memory instead of flipflops and can
cope with more inputs while still being easy to design. A small 8 kilobyte memory
element has 13 inputs and eight outputs and costs about US$2.50.
An ASM can reduce or even eliminate input and output logic.
See a later section in these notes about ASMs.
• Microprocessor + Software: if the state machine does not have to operate too fast then a
single chip microprocessor may do the job and be far more flexible as changes to the
system become software changes rather than hardware changes.
A small microprocessor such as the 18 pin Atmel Tiny26 costs about US$2 and can
provide much more functionality than a K-Map designed state machine or an ASM.
See http://www.atmel.com/devices/attiny26.aspx.
You need to take courses on software and microprocessors to design with microprocessors.

3.6.2 Synchronous Logic Example 1
PROBLEM: the required circuit is a simple up-down counter with the sequence 00,01,10,11.
If the input Up is high then it counts up, otherwise it counts down. If the state is 00 and Up is
low then the state stays in 00, if the state is 11 and Up is high then the state stays in 11.
Use D flipflops for your implementation.
SOLUTION: use the design process described in the previous section; draw a state diagram,
then a state table, and then use K-Maps to create the logic required for the flipflop inputs and
any outputs. Finally simulate the design to prove it works.
Up Up Up Up Up
00 01 10 11
Up Up Up
D1 = Q0.Up + Q1.Up + Q1.Q0
Index Q1Q0Up D1D0 Q1Q0

0 0 0 0 0 0 00 01 11 10
1 0 0 1 0 1 0 0 0 1 0
2 0 1 0 0 0 Up
1 0 1 1 1
3 0 1 1 1 0
4 1 0 0 0 1
5 1 0 1 1 1 D0 = Q0.Up + Q1.Up + Q1.Q0
6 1 1 0 1 0
Q1Q0
7 1 1 1 1 1
00 01 11 10
Next State 0 0 0 0 1
Current State Up
1 1 0 1 1
Illustration 93: Up- Down Counter Design
Illustration 94: Up-Down Counter Simulation

3.6.3 Synchronous Logic Example 2

This example uses the design process just outlined and will go further to show many
important techniques and tips you will need for your lab work.
PROBLEM STATEMENT: a small logic system is required to ignite large fireworks. Very
high reliability is required so a microprocessor solution has been rejected as the software may
crash. The only alternative left is a digital hardware solution. The key requirements and
functionality is listed below-
• The output must drive an igniter coil that must glow for 1 second.
• There is a momentary action “fire” switch and a separate momentary action “abort” switch.
The fire switch starts the count down, abort stops it at any point.
• The count down must be for 10 seconds.
Discussion: the igniter period of one second suggest that the clock input should be 1 Hertz to
get a one second period. The count down could be achieved by using ten states. The state
diagram would then become as below. There are several issues-
• Clarification: the exact functionality should be checked with the client, walk them through
the state diagram if they are willing. This often raises questions, for example should the
one second ignition state Cnt10 be allowed to abort? Is the timeout liable to change or is it
always 10 seconds? Should the ignition be at the start of the tenth second (as in the
diagram) or at the end of the tenth second?
• Excess input+state bits: there are two buttons and four state bits thus 6 bits of input for the
input logic to handle. This is beyond K-Map design. See the “Reducing Bits” in a
previous section for a range of solutions.
Idle Idle Idle Idle
Abort Abort Abort Abort
Idle: 0000 Cnt1: 0001 Cnt2: 0010 Cnt3: 0011 Cnt4: 0100
F: 0 F: 0 F: 0 F: 0 F: 0
Fire
Idle Idle Idle Idle
Abort Abort Abort Abort
Cnt8: 1000 Cnt7: 0111 Cnt6: 0110 Cnt5: 0101
F: 0 F: 0 F: 0 F: 0
Idle Idle
Clock = 1Hz
Abort Abort
F=Fire.
Cnt9: 1001 Cnt10: 1010 Fire,Abort=momentary
F: 0 F:1 switches.
Illustration 95: Fireworks State Diagram Version 1

TIMER SOLUTION: in order to reduce the input+state bits a timer will be used to replace the
long string of delay states. Look at the data sheet for the HC193 counter. It has a preset-able
counter which has a carry overflow. The parallel load input pin, when low, causes the counter
to load a preset value, and the output pin carry goes high when the final count of 1111 binary
wraps around to 0000. The preset value should thus be (16-desired count).
THE STATE DIAGRAM shown below becomes much simpler with only 3 states requiring 2
state bits and three external inputs. The inputs to the combinational logic that drives the flipflop
inputs thus has 5 bits of input and can be designed with a K-Map. Several other things have
been done to get closer to the real system-
• High or low? It is important to remember if a signal has an effect when high or low. The
case method of indicating polarity will be used. For example the “fire” input is active low
and causes firing to start when it goes low. “Carry” indicates a timer overflow when it goes
high.
• The state numbering has been set to match the outputs to try to reduce the output logic.
Ignite
Circuit Block Diagram
fire pload
Timer & State Diagram
State
abort Machine Carry
Clock
abort
Cnt: 01 Carry Clock = 1 Hz
Idle: 00 Fire: 11
Ip: 00 Ip: 01 I=Ignite output. p=Timer Load.
Ip: 11
Carry=timer output.
fire abort,fire = momentary switches.
State=Q1Q0
Illustration 96: Simplified Fireworks Igniter System
MISSING STATE? The state 10 does not appear on the state diagram! It may be possible for
this state to exist, for example on power up. All unused states must have an acceptable output
(Ignite=0), and move immediately to an acceptable state (Idle).
VECTOR AMBIGUITY: consider the vector labeled fire, in order to follow this vector what
are the values of the other 2 inputs abort and Carry? The diagram does not make this clear.
Your understanding of the circuit and product function will help you decide. In this case if
abort and fire are both active (low) then abort takes precedence and stops the move to count.
Carry should have no effect, it should be impossible as the counter is held in a parallel load
state.
In general think about the state of all inputs when translating a vector to the truth table.

TRANSLATION from State Diagram to Truth Table and K-Maps can be very error prone.
The logic driving the flipflop inputs is particularly difficult. The truth table on the next page
and the resulting K-Maps have several features that help minimize errors-
• The truth table lists all possible input values to the combinational logic that creates the
flipflop inputs. This way nothing will get missed.
• The state bits are listed first in the inputs list thus exit vectors from an individual state are
all grouped together. Heavy lines in the table separate out the states.
• The state has commas between the groups of bits that make up the K-Map rows and
columns so that it is easier to relate a truth table row to a K-Map cell.
In this problem the grouping is
Q1 Q0, a f, C; Q1Q0 refers to the Y axis of the K-Map, a f the X axis, and C the echo
line.
• On the truth table, for each state fill in the next state initially to be the same as the current
state.
Fill in the outputs, which are all the same for a given state.
Look at each vector leaving a state and identify which row(s) that represents, and fill in the
appropriate next state.
• Draw a K-Map with the truth table index
number in each cell. There is a pattern to Echo Line
the numbering which makes the filling in
much quicker. This will guide you as to C=0 C=1
where to put each truth table row in the K-
af af
Maps.
• Draw an empty K-Map for each flipflop 00 01 11 10 00 01 11 10
input. Using the Index K-Map and the 00 0 2 6 4 1 3 7 5
truth table, start filling in the empty K- 01 8 10 14 12 9 11 15 13
Maps. Q1Q0
11 24 26 30 28 25 27 31 29
When each K-Map is filled in look for
mapping rings. 10 16 18 22 20 17 19 23 21
Create Boolean equations from the
mapped K-Map. Illustration 97: Index to K-Map Cell
• Simulate your circuit and fully test all

modes of operation.
• Construct your circuit and test.

The state table for the fireworks igniter is as below.
Index Current State Outputs FF Inputs Comments

+Inputs =Next State
Q1 Q0, a f, C I,p D1D0
0 00,00,0 00 00
1 00,00,1 00 00
2 00,01,0 00 00
3 00,01,1 00 00
4 00,10,0 00 01
5 00,10,1 00 01
6 00,11,0 00 00
7 00,11,1 00 00
8 01,00,0 01 00
9 01,00,1 01 00
10 01,01,0 01 00
11 01,01,1 01 00
12 01,10,0 01 01
13 01,10,1 01 11
14 01,11,0 01 01
15 01,11,1 01 11
16 10,00,0 0X 00 10 is an invalid state, next state is always 00.
17 10,00,1 0X 00 Ignite must be zero, pload doesn't matter.
18 10,01,0 0X 00
19 10,01,1 0X 00
20 10,10,0 0X 00
21 10,10,1 0X 00
22 10,11,0 0X 00
23 10,11,1 0X 00
24 11,00,0 1X 00 State 11 always moves to state 00 next.
25 11,00,1 1X 00 Ignite must be 1, pload doesn't not matter
26 11,01,0 1X 00
27 11,01,1 1X 00
28 11,10,0 1X 00
29 11,10,1 1X 00
30 11,11,0 1X 00
31 11,11,1 1X 00

K-MAPS and Boolean algebra for D1 and D0 are below.
Echo Line
C=0 C=1
af af
Index Map 00 01 11 10 00 01 11 10
00 0 2 6 4 1 3 7 5
01 8 10 14 12 9 11 15 13
Q1Q0
11 24 26 30 28 25 27 31 29
10 16 18 22 20 17 19 23 21
C=0 C=1 C=0 C=1

af af af af
D1 D0
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
00 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 1
01 0 0 0 0 0 0 1 1 01 0 0 1 1 0 0 1 1
Q1Q0 Q1Q0
11 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0
D1 = Q1.Q0.a.C D0 = Q1.Q0.a + Q1.Q0.a.f

Illustration 98: Firework Igniter K-Maps
OUTPUT LOGIC: the state diagram tried to use the state bits directly as outputs but the
unwanted 10 state has ruined that. The F output will require combinational logic (F = Q1 . Q0)
but the parallel load output p = Q0.

SIMULATION: with complex designs such as this it's so easy to make a mistake and then find
your construction does not work. It can be almost impossible to find out what has gone wrong;
your design, or your construction.
One solution is to simulate your design to eliminate design problems, and then build the system
only after the simulation works. Below is the simulation of the firework igniter problem using
Logisim, a simple and free package which you can use for your own projects.
Illustration 99: Fireworks Igniter Simulation

MORE THOUGHTS AND IMPROVEMENTS ….
FLIPFLOP PRESET AND RESET? Remember that the flipflops may have a preset and
reset inputs. It may be possible to connect an input to one of these pins and so eliminate that
input from the state machine. This was not useful for the fireworks problem.
SWITCH PULSES LOST? The momentary Fire Momentary Action Switch

mechanical switches will pulse low when pushed.
+5v Set
Given a 1 Hz clock, a short manual push may fall Q
between clock edges and be missed. &
One solution is to use an RS flipflop where the S Q
input is connected to the switch so the Q output Reset & fire
Q0
goes high, and stays high, for a short manual button Illustration 100: Catching Pulses
push. The flipflop must be cleared at some point
with a pulse to the R input. For this problem the Q0 output should work.
The abort switch might be captured in the same way but the R pin would be controlled by a
NAND gate with Q0 and Q1 as inputs.
POWER-UP STATE: when digital gates and flipflops power up their

initial state is not guaranteed. Reliable hardware circuits require a reset +5v 1N
controller that holds the flipflops in a known state, usually via their 4148
47k
reset input, for a short time after power is applied. reset
All microprocessor require a power up reset controller which may be 100
internal or external. nF
For HC logic with high input impedance a simple circuit as shown 0v
opposite can provide a power up reset and a manual reset. When power Illustration Reset
101: Power-up
is first applied the capacitor holds the reset output low for a while,
eventually charging up via the resistor to logic high and allowing the flipflops to operate. The
diode ensures the capacitor discharges quickly when power goes down. The switch provides a
manual reset option.
D FLIPFLOP SIMPLIFICATION: if the logic

required for a D flipflop input is of form- a P Treat as Q
D0 = a.b.c + a.e b & D Q
Then the standard two layers of NAND gates can be used c
for implementation. What happens if there is only one Q
AND term? D=a.b.c R Treat as Q
D0 = a.b.c Illustration 102: D Flipflop Simplification
Traditionally implementation would be an AND gate, or a
NAND gate and an inverter. For a number of reasons NAND gates are preferred, a single
NAND gate can be used by treating the resulting Q output as if it were Q.

3.6.4 Finite State Machine Using Memory

Previous sections have shown how
a state machine can be implemented Memory Device
using flipflops and combinational logic. Address input converted
This approach produces a low gate count Flipfops to data output.
design but it is very inflexible, if the

000 001
state diagram changes then all the Clock
Address Inputs
001 010
Data Outputs
combinational logic must be redesigned. (Current State)

010 011
(Next State)
D Q 0 1
Memory chips can be used to replace the D Q 1
011 100
0
combinational logic. D Q 1
100 101
0
The diagram opposite shows a modulo 101 000
110 000
five counter built using a memory chip Count Output
111 000
instead of combinational logic. The
memory chip has many data storage Illustration 103: Counter Using Memory
elements but only the storage element
selected by the address input appears on the output.
FLEXIBLE: oh dear, design change, the count has to have a gray code order. Using
combinational logic this means a complete redesign, for a memory based system just change
the data stored in the memory element.
SLOWER: memory elements are slower than 2 or 3 layers of combinational logic. A memory
element may take 150 nanoseconds (ns) to convert an address to data, but two layers of HC
gates will delay only 40 ns.
CORE OF A MICROPROCESSOR: the core of a microprocessor is a state machine that

performs the fetch-decode-execute cycle. First a binary code instruction is pulled into the
microprocessor from memory (fetch), then the instruction is turned into control signals for the
hardware elements like adders (decode), and are finally applied to those hardware elements
( execute).
EXAMPLE: the construction

opposite is a memory based state
machine similar to the circuit
given. From left the right there is
an EEPROM memory element
with 12 address lines and 8 data
outputs. These devices are erased
by UV light and programmed
electrically. Next there is a single
Illustration 104: State Machine based Signal Generator
20 pin package of 8 D flipflops
(HC374), finally some of the
outputs go to a digital to analogue converter made from resistors and a BJT. This unit was used
to generate high speed modem signaling.

3.6.5 Timing Calculations

Sequential logic systems clearly work well but how fast can they work? To answer this
question the crucial delays in each logic element need to be added up. One clock cycle must be
at least as long as the sum of these delays.
Flipflop hold time

(inputs must be stable).
Clock
Flipfop Inputs
(after input logic) valid Invalid values valid
Flipfop Outputs
(current state and
output)
Minimum Propogation Settling Time of Flipflop setup

Clock = Delay of + memory element, + time (inputs must
Period Flipflop. input logic & PCB be stable).
tracks.
Illustration 105: Timing Limits of a State Machine
Working through the diagram above-

• Flipflop propagation delay: when the rising clock edge causes the flipflop output to change
state there will be a delay until the new output appears on the flipflop output pin.
• Logic delays: the combinational logic must take the flipflop outputs and give a new input
to the flipflop inputs.
• Flipflop setup time: the flipflop inputs require the new values to be stable for a short while
before the new clock edge.
SETUP AND HOLD TIMES: the flipflop setup time has been introduced, additionally a
flipflop input has a hold time where the input must be held stable for a period after the clock
edge. All circuits must be checked to ensure a flipflop setup and hold time requirements are
satisfied.
EXERCISE: see the section titles “Synchronous Logic Example 1”. Use the HCT data sheets
to work out each of the three key delays and so work out the maximum clock speed allowed.

METASTABILITY: if a flipflop's setup or hold time is violated then the flipflop may not
change state cleanly, it may generate a small pulse or even a slow ramp, the output is said to be
metastable. The diagram illustrates the metastable output of a flipflop.
Metastability in Flipflops
Flipflops require the data input to be stable for a "setup time" before a clock edge and a
"hold time" after the clock edge. Failure to observe this limitation will result in
metastability. This "no change" period is called the metastability window period.
Setup time violated.

Resulting Output Waveforms.
Hold time violated.
D Q
Metastability window Setup time + Hold time
The output may glitch and then end up high or low,

or simply be delayed much longer than the normal
propogation delay of the flipflop.
Lingering in the transistion band
Random data changes : assuming a random (between the dotted lines) can
relationship between the clock and data- cause a following gate to glitch.
• Pr(clock edge has metastability) = (2*data frequency) * (metastability window period)

• Metastability rate = (clock frequency) * (2*data frequency) * (metastability window period)
• MTBF = 1 / (Metastability rate)
Illustration 106: Metastability Effects
EXTERNAL INPUTS
always run the risk of Double Buffering to Eliminate Metastability
causing metastable
behavior as they are not System Clock
Clock
f1 f2
synchronized with the
clock. One of the Ext. Input
simplest solutions is to D Q D Q
Single
double buffer external External
asynchronous
Single
bufered
Double
bufered
Bufered Setup f2
inputs as below. input. input. input. Double
Bufered.
Settled : the frst flipflop has snapped out of metastability by the time the second flipflop
samples the frst flipflops output. Following devices can safely sample the second
flipflop's output using the system clock
Minimum system clock period = (setup time of f2)

+ (metastability extended propagation delay of f2)
Illustration 107: Double Buffering

3.7 Digital Device Zoo

These notes have introduced simple gates and flipflops but there are many more logic
devices you can buy. The old 7400 LSTTL family of logic had the most impressive list, see
http://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits
In more recent times there has been more done with microprocessors and less done with logic
and so the commonly used HC family only implements a few of these gates.
The rest of this section describes a very small selection of th many devices available.
MULTIPLEXERS select one of several Illustration 108: HC151 Multiplexer

inputs to send to the output. They can be
used to replace combinational logic; the S
inputs are connected to the logic inputs and
the I inputs connect to the desired output
(high or low) selected by the S inputs.
The mechanical equivalent of the MUX is a
rotary switch with eight input terminals and
one output terminal. The position of the
knob dictates which input gets connected
through to the output.
See the HC151 data sheet for more details.
SCHMIDT TRIGGER
Fixed Threshold Schmidt Trigger Variable Threshold
INPUTS have a zero-
one threshold which Voltage Voltage Output
moves to eliminate Fixed
Output
Upper Threshold
noise. See the HC14 Threshold
Active
data sheets for more Upper
Threshold
details.
Lower
Threshold Lower Threshold
Active
Time Time
Input
Input
Illustration 109: Schmidt Trigger Inputs

A MONOSTABLE uses an external capacitor to

create a fixed width pulse when the inputs are
active. See the HC123 data sheet for an example.
FLIPFLOP BANKS: devices such as the 20 pin

HC374 provide a bank of eight D flipflops with a
common clock.
LATCHES: a D latch is much like a D flipflop

except that the “clock” becomes a level sensitive
enable.
if (enable==active) output=input
else output=frozen
See the HC373 data sheet for an example.
COUNTERS of many types are available up to 8

bits. For example see the HC193 and HC590.
Illustration 110: HC123 Monostable
TRISTATE DEVICES have
outputs that can drive high, Typical Microprocessor System
low, or go to a high
Address Bus
impedance state. A
microprocessor may have a Data Bus
data bus where any one CPU

device can output data to be ROM RAM I/O
received by another device. Device
In the diagram opposite the
address bus goes from the
CPU to all devices. The data
bus can be driven by any
Control Bus
device and so all connected Clock
devices must have tristate CPU = Manipulates buses to read and write data,
xtal
capability, and only one is Most can manipulate data internally.
ROM = Permanent read only store of code and data.
writing at any time. RAM = Read/Write of code/data. Erased on power down.
See the HC244 data sheet for I/O = Input/Output device to interact with outside.
an example of a buffer with Address Bus - determines what element of what device is being accessed.
tristate capability. Data Bus - Is used to transfer data between devices.
Control Bus - Determines type & timing of transfer (read/write).
Illustration 111: Microprocessor Bus

SHIFT REGISTERS can be used

to convert between serial data and
parallel data. A Serial In Parallel Out
(SIPO) register can have data bits
clocked into the single input until it
is filled, and the have those bits
output to a parallel latch, See the
HC594 block diagram opposite.
A microprocessor with only three
control lines can control 8 bits of
output. The shift registers may be
cascaded by using the last bit of one
shift register as the data input to the
next. In this way 3 control lines
could control a very large number of Illustration 112: HC594 SIPO Shift Register
parallel outputs.
A PISO SHIFT REGISTER captures parallel data, and then shifts it out one bit at a time. A
microprocessor can control a string of these devices using only 3 control lines to capture a large
number of inputs. See the HC165 data sheet.
Illustration 113: PISO Shift Register
MUCH MORE !! This section only lists a few of the many logic devices available. See the
reference at the start of this section to see a list of what is available.

3.8 Logic Families & Compatibility

These notes have used the HC logic family but there are many other families of logic.
LOGIC FAMILIES listed below include a number of ancient types that are no longer used in
new designs. CMOS variants dominate logic design today.
• RTL (Resistor-Transistor Logic) is an old slow logic used in the late 1950s.
RTL logic was used in the Apollo spacecraft which had the first computer built from
integrated circuits. http://en.wikipedia.org/wiki/Apollo_Guidance_Computer
• DTL (Diode-Transistor Logic) is another old family used in the early 1960s.
• TTL logic (Transistor-Transistor Logic) was the work horse of digital systems from the
early 1960s until the mid 1980s. The variants LSTTL (Low power Schottky TTL) and
STTL (Schottky TTL) improved power consumption or speed over the basic TTL form.
• ECL logic (Emitter Coupled Logic) is an extremely fast logic where the bipolar transistors
never turn fully on or off. Gate delays under 1 nanosecond are possible but power
consumption is very high compared to other logic families.
• CMOS logic (Complementary Metal Oxide Semiconductors) used Field Effect Transistors
(FETs) rather than BJTs of the earlier logic families. This dramatically reduced power
and reduced input currents. CMOS was first used in around 1970 and is now the dominant
logic family. It is the basis of most microprocessors, programmable logic, and logic gates.
HC logic is a form of CMOS logic.
4000 SERIES CMOS LOGIC can take use power supplies from 3 volts to 15 volts but is
slower than HC logic. The wide variation in power supply makes them very suited to battery
operation. For a list of the gates available see
http://en.wikipedia.org/wiki/List_of_4000_series_integrated_circuits
Each gate type can come in buffered (suffix B) or unbuffered form (no suffix). The buffered
form has a strong output drive but is a little slower than the unbuffered form. Most parts sold
today are the buffered form.

NOISE MARGINS: a gate input will have an

input high threshold voltage, above this voltage HC Output HC Input
will always be seen as a high. Similarly the input Voltage Voltage
will have a low threshold, an input below this Hi Voh=4.4v Hi
voltage will always be seen as a low voltage. Vih=3.5v
Input voltages between these two limits are not a ?
valid one or zero. Vil=1.5v
Vol=0.5v Lo
The difference between a gate's output voltage Lo
and the input threshold voltage is called the noise
margin. Any noise voltage must be bigger than
this value before it might cause the input to look High Noise Low Noise
like the wrong value. Margin 1.1v Margin 1.0v
Voh = guaranteed output high voltage.
Vih = guaranteed input high voltage.
High noise margin = Voh-Vih
Vol = guaranteed output high voltage. Illustration 114: 5 Volt HC Noise Margins
Vil = guaranteed input high voltage.
Low noise margin = Vil-Vol
Note Vol and Voh are measured at the maximum suggested output current. These voltages
improve if there is less current draw, and noise margins improve.
CAN FAMILIES TALK? Digital logic requires digital outputs to be recognized by digital
inputs. What can go wrong if the digital devices come from different families or are powered
from a different power supply?
• Input over-voltage: if the power supply voltage is different between two devices then an
input may be driven by a voltage higher than its own power supply. This may cause
problems including damaging the input.
Consider a 5 volt HC gate driving into a 3.3 volt powered Raspberry Pi. The 5 volt from
the HC gate will damage the 3.3v powered Raspberry Pi logic.
Some logic is tolerant of input over-voltage, and there are level shifter chips available.
A voltage divider made of two series resistors can also solve the problem.
• Noise margin: some families have poor output drive and the output voltage may not be
enough to be reliably recognized by the input of a different family.
Try calculating the noise margin for 5 volt TTL logic driving 5 volt HC logic.
You should find the noise margin on the high drive is negative indicating that TTL
cannot reliably drive high into an HC gate.
The solution here may be to use HCT logic (HC with TTL input thresholds). A pull up
resistor on th TTL output often works but is not a guaranteed solution.
See-
https://learn.sparkfun.com/tutorials/logic-levels
http://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf

CMOS LOGIC TYPES are shown below. The characteristics of TTL (which is not CMOS) is
shown for the purpose of comparison.
See http://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf
Illustration 115: Logic Outputs & Thresholds from TI
Voh/Vol = Output voltage when driving high/low.

Vih/Vil = input needed to guarantee switching.
Vt = point at which gate will most likely switch between high and low.
(This point could be anywhere between Vih and Vil.)
Margin = difference between drive voltage and input voltage needed.
Noise must exceed this figure to cause a glitch.
Ioh/Iol = current drive at high or low voltage.

POWER AND SPEED of key logic families Logic Propagation Power per
is shown opposite. delay (ns) gate
Family
CMOS power depends on voltage and @1MHz
operating frequency. Approximately- (mW)
Power = k.V2.f RTL 500 10
k=constant. DTL 25 10
V=power supply voltage.
f =frequency of operation. TTL 10 2
CMOS at low frequencies has very low power HC/HCT 9 0.5
dissipation. ECL 1 60
Other logic families have a rising power
Illustration 116: Logic Family Power
dissipation with frequency but the rise is much
less than *f.
CMOS can be made much more power efficient than HC/HCT as listed above.

3.9 Programmable Logic

By the 1960s manufacturers had two ways to
create logic solutions; get a semiconductor company
to make a custom IC, or use many discrete gate ICs to
make a solution. Custom ICs were expensive to create
and fix or adapt, discrete logic produced large, heavy,
and power hungry devices.
In 1969 Motorola delivered the first programmable
logic device; an IC with multiple gates on the one
chip, where the connections between those gates could
be set at the last stage of IC manufacture ( the final
layer of metal contacts). This last layer of contacts
could be defined by the customer to give a custom
logic function. This gave much higher circuit density
than using discrete logic ICs such as NAND gates.
In the 1970s programmable logic chips started to
become available and by the late 1970s Field Illustration 117: Memory Device Model
Programmable Gate Arrays (FPGA) were developed
whereby a developer with a small programmer could
program “fuses” on an FPGA chip to set the logic
function.
MEMORY: in the diagrams opposite a memory
device could be modeled as a fixed AND array, each
row is a 3 input AND gate and only one AND gate is
active for a given address input. On the right hand
side each column is an 8 input OR gate for a data bit
output. If the circle is an open circuit then the data bit
for a given address is zero, if the circle is a connection
then the data bit is one for the given address.
PROGRAMMABLE ARRAY LOGIC (PAL) makes

the AND array programmable and usually fixes the
OR array. This matches the K-Map style solutions for
Illustration 118: PAL Device Model
combinational logic.
The advantages of PAL devices for implementing combination
and even sequential logic was huge-
• PCB space was dramatically reduced.
• PALs could be programmed before assembly or on the
board.
• GAL devices could be electrically erased and reprogrammed.
• Changes were much easier to make as there was no hardware
rework. Illustration 119: PAL and GAL Chips
Hardware became as easy to change as software.
NAMES, NAMES, names: many companies that manufacture FPGAs have created their own
name for the device. The list you see below is only a few of them-
• PLA (Programmed Logic Array) where both the AND and OR array are programmable.
• PAL (Programmable Array Logic), as in the previous page the AND array is programmable
the OR array is fixed.
• PLD (Programmable Logic Device), a more generic name.
• CPLD (Complex Programmable Logic Device).
• GAL (Generic Array Logic), electrically erasable and re-programmable.
WHAT ROLE FOR DISCRETE LOGIC? Given the advantages of programmable logic
why use discrete logic any more? There are several good reasons-
• The methods used to design discrete logic can be used within FPGAs so it is important to
learn traditional combinational logic design.
• “Glue logic” are logic gates that sit between a microprocessor and the outside world or
other devices. This logic is usually simple and an FPGA would be an expensive and power
hungry solution.
Glue logic often requires high current or high voltage output drives, and inputs which can
handle electrical punishment. FPGA chips do not have this capability and so discrete logic
is still used for glue logic.
HOW BIG DO THEY GET? FPGA chips can be huge with well over 1 million logic
elements as well as embedded memory, and complete microprocessors. The biggest are worth
thousands of dollars.
See the Stratix family of FPGA from Altera as https://www.altera.com/products/fpga/stratix-
series/stratix-10/overview.html
HOW SMALL DO THEY GET? Small FPGAs may have eight outputs and can cost 50 cents
but they are are surface mount parts and cannot be bought as “pin-hole” components.
DEVELOPMENT TOOLS: FPGA development can be complex and difficult. Shop around
and ensure the development tools are easy to use and within your budget. Start by looking at
well known suppliers such as Xilinx, Lattice Semiconductor, and Altera. Many of their tools
are free and of very good quality.
For small tasks you can draw logic schematic diagrams using these tools and program the
FPGA chip. For larger tasks you should learn a hardware programming language such as
VHDL (later courses here at RMIT will teach VHDL).

EEET-2251 Digital Systems Design 1 : Testing and Debugging
4 Testing and Debugging

Testing of very small systems can be done in an ad-hoc manner; just
try things and see what happens. As systems get bigger this approach fails
and several ugly problems arise-
• Can't find it: the cause of the problem just cannot be found.
• Fault not detected: a lot of faults a plague the user, that you did not
find in your testing.
• Labor time to find and repair faults becomes excessive. Deliver time approaches and you
cannot fix the faults.
Special Break: management is very unhappy and want to talk to you, now …
UNIVERSITY EDUCATION MAY MAKE THINGS WORSE, because most problems

faced at university are trivial by industry standards, you “learn by accident” that the approaches
for small problems are the best ways to solve all problems. On a larger problem these
approaches fail, and so may your reputation and job prospects! For your employer the
consequences may be a loss of reputation, delivery delays, extra costs, high defect levels, and
high maintenance costs.
MATCH YOUR CONSEQUENCES: you need to plan your testing methods that suit the
scale of the activity, and the consequences of failure. Small systems with no consequences
may stay ad-hoc. Larger systems with huge consequences of failure (eg heart pacemaker)
require complex, well planned, and costly testing systems.
MANAGEMENT CALL: it is up to management to decide on just how much time, labor, and
money to allow for testing. If testing is not adequate then the fault lies with the resources
management allowed and almost never with the technical or engineering staff.
Caveat: management must have been properly informed of the likelihood of problems and the
consequences. This is a key responsibility for an engineer.
TESTING AS A CAREER: in many areas of engineering, testing is a separate career path.

The skill set required include technical design with a heavy dose of management and
organizational skills.
There is seldom enough time and money for proper testing. A good test engineer can create a
test plan which gives the best value for money in uncovering defects.

TERMINOLOGY to know includes-

• Testing seeks to confirm a system works as intended and has no faults.
• Debugging aims to work out why a fault has occurred.
• Repair seeks to fix a fault.
• Regression testing will retest the entire system to ensure the fault has been repaired and no
new faults have been accidentally added. All behavior must be checked not just the
problem behavior.
It is very common for repairs to add unexpected faults (particularly in software) and so
regression testing must test all features again.
WHAT IS A FAULT? There are two main views about what constitutes a fault-
• Specification violation: behavior or attributes violate the specification.
• Reasonable expectations: the system does not behave as the client could reasonably expect
it to.
There are many situations in which “reasonable expectations” are legally enforceable.
Case study: an Australian company provided a telephone system to China that had one
problem; it caught on fire if the temperature dropped blow about -15 degrees C. The
supplier replied that the temperature of operation was not specified. The court found that
the supplier knew the location of installations and should have been aware of the
temperature range required.
WHY DO ERRORS SLIP THROUGH? There are many causes of errors in hardware and
software-
• Mis-specification : customer needs and requirements are wrong or have been missed. This
is usually the most significant and costly cause of errors.
• Documentation or on-line help may not match the system behavior, or may be inadequate
to guide the user.
• Combinations & sequences : combinations of inputs and input sequence variations are not
tested. In most real systems the number of combinations can be huge and it is not possible
to test every combination.
• States not tested : each unique combination of data within a system defines a state. It is
totally impractical to test the vast number of states in a big system. Almost inevitably
some untested states will be entered by the user, and some of these may be faulty.
• Untested items : because of time, labor, or budget constraints testing may not manage to
test all hardware, and execute and test all the code that the user manages to invoke.
• Operational environment for the user may not match the testbed.
• Load problems : the timing, type, and size of the load on the real system may not match the
testing regime.
• Test code/hardware left active : test code and test hardware can be accidentally left in the
operational unit and so cause problems.
• No experience: testing is much improved by having experienced people on the team; those
who have tested previously and/or know the problem domain well.
FAULT CATEGORIES : faults are normally tracked according to three categories-

• Fatal faults seriously degrade system performance, a "crash" is the most serious example.
Case study : Ehrlich et al at AT&T (IEEE Software, March 1993, pg. 33-42) found that the
history of system crashes were the only defect report that had predictive value.
• Functional faults are where a particular function fails but other functions continue
unimpaired.
• Cosmetic faults have an annoyance value but do not stop a function from operating.
Each category can be split into faults with a work around and those with no work around.
FAULT TYPES include-

• Solid or Stuck Faults are always observable whatever the state of the system. They can
easily be found using step by step searching.
Examples include a broken wire or an "if test" that goes through the wrong way.
• Pattern Sensitive faults are observable only when system in a particular state. Once the
pattern is known the faults are reproducible and thus much easier to find. It can take a
great deal of time to discover the pattern.
Examples include pattern sensitive faults in dynamic RAM or faults related to the timing of
events.
• Intermittent Faults are faults that cannot be duplicated with >> DANGER <<
any degree of consistency. Given a piece of equipment, or
a system, the faults are sometimes present and sometimes Intermittent faults are a
not. It can take a huge amount of time and effort to find danger to your reputation.
such faults. They take too long to find
It's difficult to tell if a remedy has really worked or if your and the “fix” may not
equipment is going through a statistically insignificant good work thus making you
behavior period. A knowledge of statistics can be a great look incompetent!
help to check on the significance of a good behavior period.
Examples of intermittent faults include loose connections, software responding to
interrupts, and timing problem between random events.
INDEPENDENT TESTING: the human mind finds it difficult to serve two different goals.
The creator of a design will find it hard to strive to find weaknesses in that design.
An independent and experienced tester will have the drive and motivation to find faults and
may not be hampered with misunderstandings held by the designer.
Most larger projects will hire testers from a company other than the hardware or software
supplier in order to try and catch as many errors as possible.

4.1 Specific Testing/Debug Methods

This section lists a many different approaches to testing your hardware, and software.
Pick and choose which are most appropriate to you.
TEST BEFORE THE END: there are many ways in which a design can be tested before a
prototype has been created. The tests below are usually much more cost effective than testing a
completed prototype.
• Simulate the hardware or software to ensure the design is correct. In most cases it is easier
and quicker to run a simulation than test the real equipment.
• Peer review: get others to review the requirements analysis and design proposal before
implementation. Experienced designers will often pick up problems in a few minutes that
will save days of effort later.
In software this approach can eliminate up to 80% of errors if done carefully.
• Checklists: many companies develop checklists of good design practices, known problems,
and general guidelines. These can be very useful to new engineers and are still used even
by experienced engineers.
TEST PLAN: write down at least the equipment required, and what inputs to apply and what
outputs to expect. A well written test plan has many advantages-
• Check/approve: other professionals can check and approve the plan.
(Politically what does this imply?)
• Operation of the test plan can be by others, usually less skilled and less costly staff.
• Saves time especially if the test must be done several times.
• Next time: the plan is often a useful start for the next product to be tested.
CONTROLLABILITY AND OBSERVABILITY: it can be TP0 +5v

very difficult to control hardware or software so that it can be
moved into every state, and then observe how that state behaves. P
Normally the design phase must include test points to improve D Q
observability, and extra hardware or software to allow the system
to be forced into all states. Q
R
In digital electronics the set and preset pins of flipflops are often TP1 +5v
pulled inactive but are available for test purposes as test point (TP). Illustration 120: Test Points
AUTOMATE: regression testing will test all features of a system after even a small change
because it has been observed that repairs will often fix the obvious fault but accidentally
introduce new faults.
Regression testing is VERY important in real products but it is painful and labor intensive to
run the full battery of tests after every small change to the product. One approach is to create
test tools that can automatically apply stimuli and check for responses.

There are commercial test tools available though for digital systems it is easy to create one
yourself.
TRADITIONAL PROBLEM SOLVING theory offers a good checklist to help handle faults.
• Define the observations : ensure the observations are accurate and repeatable.
• Is there really a problem? The real problem may be a misunderstanding, failure to read
instructions, or ignorance. No problem may exist.
• Define the boundary : in all ways possible-
➢Define what is, and what isn't the problem.
➢Localize the problem to a small part of the system.
➢Timing and relationships to other events should be clarified.
➢Simplify the situation and eliminate extraneous factors.
• Impact analysis : analyze who is affected by the problem and any solution. Ensure all
affected parties are kept informed. Think about the response from all stakeholders.
• Quick fix : is there a quick fix that can be justified? Who needs it first?
• Fix what : what needs to be fixed, and what should be left as is?
Not all faults need to be fixed or are cost effective to fix.
• Monitor : when a repair is made check it really does work and has not affect other features
of the system.
• Long term fix : if a quick fix was made what is the long term fix?
CHECK THE QUICK AND OBVIOUS : a little experience will usually show that some
things are quick and easy to test and often the cause of a fault. It makes sense to check these
things first. Examples include-
• Has power got to the hardware and all ICs?
• Is this software routine even getting called?
• Are the inputs correct? Which outputs are wrong?
• Have any gate inputs been left floating?
STEP BY STEP testing is simple and obvious – yet many technocrats cannot do it!
Start testing at the external inputs.
• Change the inputs to all possible states to ensure the external inputs work.
• Test one step away from the external inputs, again check all input combinations have the
desired effect.
• Keep moving one step away from the inputs until all outputs are observed.
If a fault is found at any point then try repair methods such as disconnection, replacement, or
redesign.

BINARY SEARCH FOR FAULTS : many hardware or software systems progressively

modify an input to create an output. If the output is wrong which portion of the system is at
fault? A binary search progressively divides the remaining suspect portion of the system in half
until the faulty item is found.
Binary Search Faulty item.
( one fault) Start End
Input
( OK) Output
1/8 1/4 3/8 1/2 5/8 3/4 7/8
( faulty)
Measure @1/2 ( OK) OK ?
Measure @3/4 ( bad) OK ? OK
Measure @5/8 ( OK) OK ? OK
Measure @11/16 ( OK) OK OK
Illustration 121: Binary Searching
BASELINING : often during testing and development, the designer will get quite confused and
nothing will seem to work. To the designer the system seems to be out of control. A good
solution to this dilemma may be to "baseline" the system.
A baseline is a system which has known properties ( which may include known faults). When
an out of control system is "baselined" it may have sections removed or made inactive. This
will return it to a baselined state. Once the baseline operation has been verified then the
additional features can be turned on and checked one at a time.
INTERVENTION : there are many times when there is insufficient information available. The
usual solution is to intervene in the system in such a way as to gather more information.
Examples include-
• For hardware add indicator LEDs at crucial points.
For software add print or write statements that show code executed and variable changes.
• Add temperature, voltage, or vibration loggers to the system.
• Change some parameter or function in the system and analyze the change in performance.
Novice debuggers tend to be too slow and too conservative in the degree of intervention used to
isolate and characterize faults.

KNOW THY TOOLS: most areas of technology have a range of testing and debugging tools.
It's worthwhile spending a little extra time now to learn these tools as later on they can you a lot
of time. In your time at university you should learn at least the following-
• Digital hardware: multimeter, logic analyzer, logic probe, logic pulser.
• Analogue hardware: multimeter (volts, amps, ohms), oscilloscope, and signal generator.
• Software: single step debugger, test coverage analyzer, timing profile analyzer, memory
leak detector, stack and heap profiler.
If you do not know these terms then go an read about each.

4.2 Intermittent Faults

Intermittent faults have already been introduced; faults >> DANGER <<
with no apparent cause, cannot be reliably recreated, and when a
fix is applied it is hard to tell if that fix has worked. The warning Intermittent faults are a
opposite has already been given, but this is important and worth danger to your reputation.
stating again! They take too long to find
and the “fix” may not
This section has some ideas and methods that may help. work thus making you
look incompetent!
INTERMITTENT FAULT STATISTICS : intermittent faults are usually measured as

failures per unit time, or failures per manufactured unit, or failures per test run. How much
time, or how many manufactured units, should be examined before it can be concluded that
the fault has been rectified?
In some cases staff will say "I'm certain its fixed". Decision makers must then make a
subjective judgment on whether to believe this statement. If the repair staff are uncertain,
not trusted, or if the consequences of failure are large, then a more rigorous proof of repair
is needed.
If the initial fault rate was measured then mathematical predictions can be made. The following
methods are useful but if precision is needed then more rigorous statistical mathematics should
be used.
• Time measurement : the Poisson model from statistics can be used when faults occur
randomly and have a small probability of occurrence.
Probability( zero faults over time t ) = e -µ
µ = expected number of faults over the measured period t.
Eg. A computer network crashes randomly once a day. A software fix is introduced and
after 3 days there have been no crashes. What is the probability that the fault is not fixed
( it was just a lucky run) ?
µ = 3 Given one crash a day previously, over 3 days 3 crashes are expected.
Probability( 3 days fault free if problem not fixed) = e-3 = 5%.
• Unit based measurement : discrete items can be given a probability of having no faults (p).
The probability of "n" items in a row showing no faults is simply pn.
Eg. One telephone call in 1000 fails, a software fix is introduced and 2500 calls are made
without loss. What is the probability that the fault is not fixed ( it was just a lucky run and
the fault is not fixed) ?
pn = 0.999 2500 = 8.2%, there is a 1 in 12 chance it was just good luck.

GARBAGE COLLECTORS will scan for a known problem and then take steps to ameliorate
or solve the problem. This does not fix the problem but will reduce or eliminate the negative
effects of the problem.
SAFETY INTERLOCKS are a form of garbage collection where the aim is to ensure nothing
dangerous happens.
Example: electric clothes dryers, even complex software controlled units, have a thermal
cut-out in series with the heating element. This simple mechanical unit will turn off the
heating element if the dryer gets too hot.
CORRELATION ANALYSIS : consider the situation of an Event # #1 #2 #3

intermittent fault in a complex system. It can be a nightmare to Factor
locate the real cause of the problem.
Time of day.
Correlation analysis helps to find the pattern behind the
Shift #
problem by listing every factor that can be determined, every
time the fault occurred. The human mind can then scan the data Temperature
for patterns in order to detect causes. A lack of patterns can ...
also help to eliminate possible causes.
The determination of the "possible factors" column in the correlation table is a very important
activity. Brainstorming and asking all affected parties to provide possible causes can help
uncover new factors, as well as create a positive relationship between parties.

4.3 Digital Design Construction & Debugging

This section lists construction and debugging techniques, and common problems found,
when building small digital electronics projects on bread boards. A lot of this section is
arranged as a checklist so you can scan it quickly when you are having problems.
as a checklist so you can scan it quickly when you are having problems.
4.3.1 Time Management

The single biggest fault in most university labs and assignments is that students think "it
will be OK" or "I can do it in one night". Sometimes this works, usually it does not!
Always start as early as you can so you can overcome the inevitable problems you will face.
In the later labs of this course a late start almost guarantees you will not have the time to debug
your circuit and get it working.
4.3.2 Simulation
Consider you have designed and built a circuit and it does not work. Is it a design fault?
Is it a construction fault? What do you do to fix the problem? Where do you even start?
When problems are complex you must use the engineering principle of "divide and conqueror"
a big problem into smaller problems.
First simulate your design to be sure it fully works. There will be a small learning curve in
using the simulator but you will quickly be able to see if your design is correct. If there is a
problem you can redesign until it all works. If you constructed unit fails then you can now be
sure that any faults are construction faults and look for common construction faults.
An earlier section looked at the Logisim simulator which is adequate for this course.
4.3.3 Basic Soldering

Common problems include-
• Clean metal: ensure metal is clean, if not scrap or sandpaper till clean.
• Soldering video: soldering is not difficult but there is a technique to it. Learn this from
technique and practice it before working on your first board.
The most important hint is to hold the iron against both items for 2-3 seconds, then apply
solder the the solder to where the iron and one metal element meet.
• Component orientation and values: double check these things.

• Schematic and layout: learn how to identify a component on the schematic, then where it
is on the layout. This skill will be even more useful when debugging.

4.3.4 Devices & Wiring

• Have a schematic so you can build from it and debug against it.
Remember to include all power supply connections to the ICs.
• No floating: all IC inputs must be tied high or low for the gate to work properly.
A floating ( unconnected) input can drift high or low and cause odd operation.
• /reset and /preset on flip-flops must be tied high so the device can function normally.
• IC orientation: make sure you know where pin 1 starts. Look at the data sheet to be
certain.
• Misplaced wiring is very common so check carefully by eye.
4.3.5 Breadboards
• Power runs: most breadboards have two power run down both edges of the board.
Typically one is for +5v/+3.3v and the other 0v.
Some boards have a break in the middle that you must bridge with wire. If you fail to do
this then the bottom half of the power run wont be connected.
• Connections: wire need to be inserted 2-3 mm to make a good connection. Wires that
“just reach” probably do not, or give intermittent connections that do not survive
transport.
• Transport? Breadboards are notoriously unreliable and can fail if knocked or bumped.
Consider how to transport a breadboard to minimize such problems.
4.3.6 Debugging Techniques

Useful methods include-
• Simulation as mentioned should be your first step to ensure the design is correct.
Without simulation, when the circuit does not work, is it the design or construction
which is wrong?

• Add LEDs (with current limiting resistors) to key points of your circuit so you can see at
a glance what is happening. With state machines it can be useful to have LEDs on the
flip-flop outputs (current state ) and flip-flop inputs (next state).
• Multi-meter: this is your primary debugging tool. Use it to check all voltage points are
correct.
Setup: using a clip, connect the black zero volt lead to zero volts on the clock board. Set
the meter to DC volts and the 20 volt range. Ensure the black lead is in the common
socket, and the red lead in the voltage socket.
Start testing at the clock board where you should see the full power supply voltage.
Work from there to measure the power pins of the IC, then the input pins of the IC, then
the IC output pins.
• Compare circuit to simulation: ensure you have LEDs on flip-flop outputs (the current
state) and flip-flop inputs (the next state). Compare these to your simulation. If a next
state is wrong, work from the flip-flop input back through the gates to see where the
circuit differs from the simulations.
• Build-test-build-test … Try to build your circuit in stages and check each stage before
going further. For example wire up your switches and check with the multi-meter that
they work.
• Base-lining: if your complex circuit does not work then try simplifying the circuit,
perhaps on another board. In this simple version try to work out what is wrong.
Example: in a lab requiring a state machine a student had not realized that a flip-
flop required /reset and /preset to be held high to be inactive. They built a flip-
flop with a 0/1 input and looked for a 0/1 output. The observations allowed staff
to quickly work out what was wrong.

4.3.7 Beyond the Multi-Meter

So far you have used a multi-meter to debug your simple digital circuits but multi-meters
are only good for checking power supply voltages and very low speed digital circuits. In many
digital circuit short pulses are normal, or may be part of the problem. In these cases devices
such a logic probes and logic analyzers are required.
YOUR LEDs: as described having your own LEDs connected to key points is an excellent
debugging tool.
LOGIC PROBE: these are powered from the digital

circuit power rails and can check the status of a
single point. They can show-
• Valid high, usually a red LED.
• Valid low, usually a green LED. Illustration 122: Logic Probe
• Invalid voltage the volt is between valid high
and valid low. Often a yellow LED.
• Floating wire, often a yellow LED.
• Pulse stretcher: any sized pulse is made 200 ms long, usually shown by flashing the
LED. Even a very small pulse becomes visible this way.
• Memory: alternative to a pulse stretcher, an LED stays on when a pulse is detected.
• Logic levels: select between CMOS and TTL voltage levels for determining if a voltage
is a valid high or low, or invalid.
Logic probes can be quite cheap, typically under $10.
LOGIC PULSER: this device puts a pulse high or low on a circuit, overdriving an IC for a few
microseconds. You can see the effects using a logic probe with a pulse stretcher.
Illustration 123: Logic Pulser

LOGIC ANALYZER: logic probes are very

useful but they cannot show the history of a
test point, and cannot show multiple test
points. Logic analyzers have multiple inputs,
sampling rate control, and can trigger on a
combination of inputs allowing you to
capture events as you wish.
Logic analyzers can be found as USB plug-
ins for your PC for under $100 up to
thousands of dollars for very high speed stand
alone units that can capture digital and
analogue inputs at the same time.
Illustration 124: Logic Analyzer
Illustration 125: Bitscope Mixed Mode Display

EEET-2251 Digital Systems Design 1 : Interface Electronics
5 Interface Electronics
Electronic signals can be very easily corrupted by interference leading to noise in
analogue systems, data corruption in digital systems, and destruction of devices. This is a real
world problem that ruin “theoretically” good designs.
In this section we will look at the causes of these problems and some solutions. Only the very
basics will be covered and later courses will go into much more depth. You will find some
useful lecture notes that go a lot further on the Linux live-DVD, see
/home/extras/lecture_notes/Electronics_Digital/Electronic_Problems.pdf
5.1 Sources of Interference

There are whole variety of ways in which unwanted energy can be injected into an
electronic circuit.
CAPACITIVE COUPLING: any two conductors close to each other Stray Capacitive Coupling
will have a finite capacitance between them. For example two tracks on
a printed circuit board will have a small capacitance between them. Noise Victim
Source Circuit
Capacitors let high frequencies through and so a high frequency noise
source can capacitively couple noise into a victim.
Illustration 126: Noise
This can become a problem as clock frequencies get into the megahertz and Victim
region.
Parallel Wires
Radius r C =
π
a
cosh
-1
x = Ln (x + 2
x - 1 )
cosh
-1
( 2r
) Farad / m
"a"
between
centres.
L High Freq. =

π
cosh
-1
( a
2r
) Henry/m
Illustration 127: Capacitance Between Wires
ELECTRO-MAGNETIC INTERFERENCE (EMI) can result when an electromagnetic

signal such as radio waves is absorbed by a conductor. The sources of EMI include-
• Any high frequency electronic signal, and any digital signal with a fast rise or fall time.
• Sparks such as found in brushed motors or welders.
• Any transmitter such as a Wifi router or mobile phone.

INDUCTIVE COUPLING: any conductive loop can generate a magnetic field, which can be
received by another loop. Cables and wires form surprisingly large loops and can pick up
everything from mains hum to high frequency noise.
Loop Inductance
  2. b 2.a
L square = a.Ln + b.Ln
 d d
"b"
"a" "C"
"d"
"d" –7 8. C
L round = 6.14 x 10 xC x Ln -2
d
Illustration 128: Loop Inductance
ELECTROSTATIC DISCHARGE (ESD) is caused by a build up of

charge, usually on the human body, that discharges into the electronics.
If you have ever got a zap from touching a water tap or a car then you
have felt the power of ESD.
ESD can blow a small crater in the tiny inputs of an integrated circuit. ow!
EARTH NOISE: we often draw a “0v”

symbol on our circuit and expect it to be Motor Input
an exact zero volts but this is seldom the
case. In the circuit below the zero volt
Motor Power
wiring has a non-zero resistance or
Supply
impedance Z between circuits. As the
motor draws current each Z will cause a I Z Z Z Z
voltage drop and so each circuit in the 4IZ 3IZ 2IZ IZ 0v
middle will see zero volts to be a Illustration 129: Earth Noise
different value. Noise on zero volts adds
noise to any signal input.
In the diagram above the motor input to a circuit is contaminated by a voltage of 3*I*Z.
Power supply noise is electrical noise on the supply voltage, for example +5 volts and is
caused by the same problem.
ACCIDENTS AND ABUSE: the real world is full of accidents and deliberate abuse but well
designed electronic systems should be able to cope. The designer needs imagination and
experience to work out what could go wrong, and how to economically solve the problem.
Case Study: to disable a poorly designed burglar alarm smash the front keypad with a brick
and use an external mains power point to connect mains power to a variety of wires. The
mains power will blowup a poorly designed system and stop any alarm outputs.
Case Study: consider car electronics which is based on 12 volts, what happens when a 12
volt signal is accidentally input to your 5 volt HC logic? The logic is destroyed
immediately!

STORED ENERGY: capacitors and inductors can store energy and in some cases this
will cause problems.
Inductor Energy Storage Problems & Solutions

+V +V
Inductors try to keep the One solution is to
current going through them place a "catcher" or
at a constant value. When "flywheel" diode
the switch is opened the which allows the
inductor will generate a inductor current a
reverse voltage of several path when the
?
hundred volts to try and switch is opened.
keep the current constant.
0v 0v
Damage : the flyback voltage from an inductor will cause sparking and erosion on
mechanical contacts and may destroy semiconductor devices.
Speed : using only a diode the energy in the inductor takes some time to drain away. This
may mean that a relay takes too long to release. This period can be reduced by adding a
small resistor or zener in series with the diode or by replacing the diode with a spark
gap. Either approach gives some voltage transients which should be checked.
Capacitor Energy Storage Problems & Solutions
+V Capacitors try to keep the voltage across +V A current

themselves constant and will supply limiting resistor
large currents to try and achieve this. is one solution to
In this circuit the switch will be the problem. It
subjected to a very high current will also slow
transient. This transient may erode or down the
weld together mechanical contacts. It discharge of the
0v may destroy semiconductor devices. 0v capacitor.

Capacitor Energy Storage & ICs
Vcc=+12v Vcc=+12v
Capacitors try to keep The additional
the voltage across diode limits
Vi - -
themselves constant Vi to one diode
+ +
and will supply large drop above Vcc.
Vi
0v currents to try and 0v The resistor
achieve this. limits the
In this circuit the Vi is current flow
maintained by the into the IC.
capacitor while the Some ICs may
power supply turns Vcc need schottky
Vi
of. The IC appears to diodes with a
have its input raised Vi 0.2v drop for
Vcc
well above the power proper
supply voltage. This protection.
usually destroys the
IC.
BUILT IN DIODES: most digital integrated circuits have built in diodes which solve the
above problem and limit the effects of Electro-Static Discharge (ESD).

5.2 Interference Solutions

From the perspective of digital electronics there are several things that can be done to
eliminate or at least reduce interference. This section has just the basic methods.
SHIELDING with a conductive layer can eliminate Faraday Shield

capacitive and EMI coupling, this is called a Faraday Shield.
Using ferromagnetic material such as steel can also block Noise Victim
magnetic fields. Source Circuit
Many cables use a shield to enclose the signal wires. The

coaxial cable turns the signal return path into a shield.
Many computers and digital equipment are housed in a steel 0v
box both to stop interference coming in, and to stop
interference going out and causing problems with radios and
Guard Track
phones. Most countries have standards about EMC
(Electro-Magnetic Compatibility) which places strict limits
on the amount of EMI a product can emit. Coaxial Cable
Printed circuit boards will often have an internal layer that is
connected to zero volts. Such layers are the only reason that
PCBs can work above 10 MHz.
Illustration 130: Faraday Shields
DECOUPLING CAPACITORS: capacitors like to keep
the voltage across them constant and will supply or
absorb current to achieve that. Digital circuits use 100 nF
decoupling capacitors, and large electrolytic capacitors
to absorb power transients and stop power supply and
earth noise.
Your later courses will look at this in more detail. See
https://learn.sparkfun.com/tutorials/capacitors for an easy
to follow explanation. The diagram opposite is drawn
from that page. On the digital power side the 10uF
electrolytic reduces low frequency noise, the 100nF the Illustration 131: Decoupling Capacitors
high frequency noise.
*** Your 555 board has these components! Analogue Digital
Printer Motor
STAR POINT EARTHS (zero volts) ensure
that the high currents from noisy circuits do
Case EMI & ESD shield. Reference
not interfere with the sensitive analogue and 0v
digital circuitry. Never allow zero volt (earth)
or power supply loops. Mains Earth
Illustration 132: Star Point Earthing
This technique is very important and is used in
all well designed electrical systems. Even on a
PCB the digital and analogue zero volts are separated so the more sensitive analogue signals do
not receive digital interference.

PROTECTING INPUTS: there are many ways to protect inputs. The circuits below have
been used to interface to the parallel port of a PC, a 5 volt logic digital IO port. “PP input” is a
digital input to the computer, “PP output Hi” is a +5 volt source.
Trustful: assumes the input

is free of damaging
voltages.
Simple buffering protects

against negative voltages.
The resistor limits currents
that flow due to over or
under voltages.
Conservative buffering
offers more protection
against voltages outside the
0v to 5v range.
Optocouplers break the

electrical loop and can
provide 2000 volt isolation.
This also solves problems
with earth voltages and
inductive loops.
Note for better protection Illustration 133: Protecting Digital Inputs
the optocoupler LED should
have a diode across it to conduct negative currents.

Illustration 134: 4N25 Optocoupler

PROTECTING OUTPUTS can be done in a similar manner. The circuits below have been
used to buffer the PC parallel port output logic. “PP output” is a 5 volt logic output.
Trustful: if the target load is

too small it overheats the gate
drive output. Unexpected
voltages will destroy the
output driver.
Buffered: the BJT has higher

current capacity than a a gate
output. The Vcc may be
much higher than the logic
voltage. A 1.8 volt CMOS
output can control a 200 volt
load!
Conservative: many loads

have an inductive component
and when the current turns off
the inductor can generate a
large negative spike that will
destroy the driver. D1
provides a return path for the
current and avoid the
inductive spike.
Diodes D2 and D3 provide
better protection should Q1
fail and put a high voltage on
the base of Q1.
Optocouplers can break the

electrical loop and as before
protect against huge voltage Illustration 135: Protecting Outputs
differences, earth voltages
and inductive coupling.

EEET-2251 Digital Systems Design 1 : System Level Design
6 System Level Design

The is an incredible difference between designing a small system and designing a big
system. For a small system all you need is native cunning and the ability to communicate well
with a client. For a larger system such as a complete air traffic control system the complexity
becomes overwhelming and a whole range of formal methods and tools become essential to
cope with the complexity.
UNIVERSITY EDUCATION DOES NOT HELP: yes we said this before and it's worth
saying again. At university you only work on small projects and so small project methods get
ingrained into your mind. When these methods are applied to larger problems the result is a
disaster.
Case study : letters to the editor in IEEE Computer August 2002 page 8 reports bright
young PhDs who were convinced they could control a new pilot pharmaceutical plant from
their IBM-PC. Issues such as reliability, timing, and scalability were ignored, probably
due to lack of experience.
As a young engineer stay sensitive to the issue of complexity overload and watch carefully the
work practices of successful engineers and managers.
USEFUL TOOLS AND METHODS for handling complexity are listed below. You should
get practice with all of these somewhere in your university courses. Many of the tools manage
information, people and materials which is a key part of real engineering.
• Gantt charts can map time and resources for tasks to make a map of how the project should
proceed. Monitoring actual activity against initial plans can give early warning of
problems and delays.
• Issue tracking tools can keep track of all the small tasks that must be done and ensure
nothing gets missed or lost.
• Configuration management tools keep track of all the versions of hardware, software, and
documentation. Without this information it is impossible to support customer sites, or even
to extend an existing product.
• Requirements tracking tools that ensure that every part of the requirements document is
getting implemented and tested.
• High level modeling methods help to model the system at a high level of abstraction which
can simplify a system. Examples include state diagrams and UML (Universal Modeling
Language).
• Mind map tools that help improve your problem solving and help communicate your ideas
to others.
• Divide and conquer methods: ways to split a big complex system into subsystems. Block
diagrams and data flow diagrams are both very useful methods.

6.1 Functional Block Diagrams

Functional Block Input
Diagrams ( FBD), often Block = process or
called simply Block object that transforms Output
Diagrams, are an old but inputs to create one
or more outputs.
very powerful way of
Another Input
analyzing and designing Vectors always have
a system. They can be descriptive names.
used to model anything
Another process, Vector = flow of
that manipulates
with a meaningful energy, information,
materials, information, or Save/Retrieve of
or materials.
Energy/Information/ name.
energy.
Materials
Illustration 136: Basic Block diagram Elements
KEY RULES A block transforms energy, information or materials.

A vector must represent energy, information or materials and is named.
Decisions are hidden inside a block.
3D 3D Acceleration
User Brake
Accelerometer
Sensor
Vehicle
Steering Steering Angle Dynamics
Angle Sensor Estimator
Braking Desired
Wheel Speed 3D
Dynamics
Wheel Speed
Rotation Hydraulic Brake Brake Slip
Sensor Control Pressure Determination
Brake
Hydraulic On/Off/Pulse Hydraulic
Brake Hydraulic
Fluid
Brake Pump Hydraulic
Per Wheel Fluid Resevoir
Illustration 137: FBD For ABS Braking System

EASY TO UNDERSTAND : FBD models a system in a way that most people find very easy
to understand. Most stakeholders can easily understand FBD with no training; this alone may
make FBD worth using.
ANALYSIS MODE AND DESIGN MODE : FBD can be used in four steps-
• Model what exists as a block diagram (not needed for a new system).
• Analysis mode : propose a new system without making implementation choices except
where the client mandates a decision. Each box describes an abstract function.
This digram shows what the system must do but not how to do it.
• Implementation selection : each generic block in the analysis mode FBD is examined
and alternatives listed and considered. The best set of alternatives is selected.
• Design Mode : the analysis mode FBD is redrawn with all the selected alternatives and
the diagram is elaborated to define the system structure.
This diagram defines how the system will work be built.
At each stage non-technical stakeholders can be involved. The systematic consideration of
alternatives can often help develop new and novel solutions to problems.
WHEN TO USE? FBD are of most use when-

• Non-technical stakeholders need to be kept in the analysis and design loop.
• The system is dominated by the flow and transformation of materials, information, or
energy.
• Whenever there is a mixed solution, for example some mechanical hardware, electronic
hardware then software processing of signals.
WHEN NOT TO USE? FBD are of little use for-

• Systems where data or other structures dominate the system, for example modeling a
bridge or a database.
• Showing detail and structure of software.

EXAMPLES of block diagrams from the web are below-
Illustration 138: Block diagram: Aircraft Hydraulics
Illustration 139: Block diagram:

Amplifier
Illustration 140: Block diagram: Heat Pump
Illustration 141: Block Diagram: Solar PV Generator

KEY QUALITY INDICATORS: it's easy to tell if the block diagram is of good quality-
• Good naming: all naming of blocks and vectors is clear and obvious.
• Vectors named: block diagrams aimed at helping designers will also name the vectors.
• Minimal interface: the vectors between blocks should be as simply as possible and where
possible conform to industry standards, for example power is 12 volts not 16.5 volts.
This is a key attribute of a good design an can result in many benefits-
➢Each block can be made highly independent from other blocks. Each block can be
developed in parallel thus saving development time and shortening time to market.
➢A block where all inputs and outputs match industry standards might be something
which can be purchased.
• Data oriented: the vectors should represent information, energy, or materials and seldom
control information.
• No decisions are shown (no diamonds as from a flow chart). These are hidden inside a
block.
Decisions such as if-then-else keep on changing as your design evolves.
If you draw out these then your diagram quickly becomes overly complex, out of date and
useless.
The basic building blocks do stay the same so a block diagram continues to be useful.
MULTIPLE VECTOR FORMS: it is quite possible to mix different energy forms, for
example a red vector may be hydraulic, blue, electrical, and green a mechanical input.
EXTENDED FBD give more information and can be directly linked to a document, or a
chapter of a document.
DATABASES/FILE symbol should be used sparingly. It is intended to store data over time
where that data must be shared between processes.
DATA FLOW DIAGRAMS (DFD): FBD have a lot in common with an old software design
tool called Data Flow Diagrams. FBD extend beyond DFD and are much more useful in the
engineering context.

FITTING INTO A REPORT can be done as follows-
Hierarchical Functional Block Diagrams (FBD)
Master Level Diagram (System Description)
0.1 1.0 0.2
0.3
Child of 1.0 (Detail)

0.1
1.2 1.4 1.1 0.2 Detail of 1.1
Tex t, circuit diagrams,

1.3 or other material that
0.3
show s details of th e
selected box.
Fitting FBD into a Project Trace

1.0 I ntroduc tion and O ver view .
2.0 Customer Inter view s and Customer specification.
3.0 Fluid level controller : Master Block Diagram
3.1 Sensor Details : 1.0

3.1. 1 Sensor c ircuit : 1.1
FBD Material.
3.1.2 Signal conditioning and transmission : 1.2

3.1.3 Isolated Power Source : 1.3.
3.1.4 Mechanical mounting details.
3.1.5 Calibration and Ageing Calcula tions.
3.1.6 Reliability Calculations.
3.2 Sensor Signal Resception and Cond itioning : 4.0

•
•
3 . 3 F l u i d D y n a m i cs C a l c u l a t i o n s : 3 . 0
•
•
Illustration 142: FBD Within a Report

FBD EXAMPLE : consider a simple broadcast radio receiver design using the FBD method-
Analysis FBD for a Simple Radio

Full RF RF energy RF RF band Selected Demodulation Audio Audio
spectrum capture. energy selection. band to audio delivery.
Power to all blocks

Power source
Illustration 143: FBD in Analysis Mode
• Generic : in analysis mode all vectors and blocks are generic in nature and do not state
an implementation, unless the stakeholders have mandated a particular alternative.
• Clear naming is vital. For example “Full RF Spectrum” gives a hint that there are other
RF transmitters and RF interference to be considered.
• Extra text : The analysis specification will typically have a section called “System
Definition” that starts with the analysis mode FBD. Subsections for each block then
define key properties of the block and the vectors that connect to the block.
• Alternatives are considered after the blocks are all defined, and all system level
requirements are defined, for example operational temperature range and input signal
levels.
Design FBD for a Simple Radio

Full RF Whip Raw RF APT55 RF Amp. RF DSP-101
spectrum antenna. energy amplifier. energy Demodulation.
Analogue
audio.
Power to all blocks
Power source 10cm magnet Power LM386 Audio
coil speaker. audio. amplifier.
Child Diagram of DSP Demodulator
Amp. RF DSP A-D Digital DSP demod Digital DSP D-A Analogue
energy. conversion. RF software. audio conversion Audio
Illustration 144: FBD in Design Mode
• Choices have been made from the alternatives for each block on the analysis FBD.
• Changes : it is common to get blocks merged and split. In the example RF energy
capture has been split into antenna and RF amplifier. RF band selection and
demodulation have been merged into a DSP.
• Child diagrams : on any FBD a block can be shown in more detail on a child diagram.

Note the DSP block in the example above.

CONSULTING EXAMPLE: in this exercise you will draw three FBDs. The first will
represent the current description as drawn from the client's rambling description. The second
will be an analysis mode FBD which looks at a logical view of information and materials flow.
The third diagram will be a design mode diagram where you develop a solution and explain it
by using a FBD.
Client description: we are having a lot of trouble with our stationary ordering an need a
new system. Bill goes to each of our four departments and writes a list of everything
required and bring it back here. Carole then creates a consolidated list, costs each item (eg
50 pens) and adds up the cost of all items. She then sends the list to Mary for approval.
Bill now orders the approved list from the provider and when it is delivered unpacks the
box and sorts the stationary into four boxes, one for each department. Bill then delivers
the boxes to their respective departments.
Start work? No !!! It is incredibly uncommon for clients to give you the whole story. You
need to find ways to help them to tell you more to get the full picture. Here are some example
questions to ask-
• Have there been problems? If so was there a solution?
• What is the key thing you want to achieve as a result of any changes?
• Can I check some of the small details with the other people affected by the project.
What next: draw each diagram listed below and then consult back with your clients.
• FBD of what currently exists.
• FBD or logical system ( functionality but not how or who does what).
• FBD of new system (how it will now work).

Current Operation FBD
Department 1 Individual
Dept Needs All
Dept Needs
Department 2 Carole collates
Bill Collect Needs and costs.
Department 3 Collated,
costed needs.
Department 4
Mary approves.
Goods distributed
Approved needs.
Bill distributes goods.
Bill Orders.
Supplier Order to supplier.
Goods delivered.
Logical FBD
Individual Collated,
Dept Needs costed needs.
Department Collect, collate, cost.

Approve.
Goods distributed
Distribute Order.
Approved needs.
Order to supplier.
Illustration 145: Office Ordering Current and Analysis Mode FBD
NOW FOR THE MAGIC: the hallmark of a good engineer is that creative streak that
produces a clever new system. In this case there is a heavy usage of paper and people, which is
unusual today where personal computers and the Internet are everywhere. Some ideas which
may help include-
• Can the departments fill in a spreadsheet with their needs? Perhaps the approver Mary
could set this up. A spreadsheet can collated needs and even provide an order form from
the individual department spreadsheets. Online systems such as Google forms and
documents could be used.
• Can the supplier send a package per department. The higher delivery cost will be less than
the labor costs of unpacking and distributing.

THE PROPOSED SYSTEM is much simpler, quicker, and will cost less labor time-
Proposed System FBD

Collated,
Individual costed needs.
Dept Needs Spreadsheet to
collect needs, Mary approval,
Department collate and cost. Send order sheets
for each department
to supplier.
Supplier.
Individual department Order to supplier.
deliveries.
Illustration 146: Office Ordering Proposed FBD
IN YOUR FUTURE at university you will find FBD an excellent way to describe complex
systems so that reviewers and markers can quickly grasp what you are doing. Later in industry
you will find them just as useful.

6.2 Flow Charts

Flow charts are the traditional way to trace the fine
detail of control flow. Most people feel comfortable
with flowcharts as they match how we naturally solve Traditional Control
small problems in life; the “what happens next” style of Based Flowchart
problem solving.
The problem is that flowcharts don't scale up well to
help solve big problems. They also model the most Start
volatile part of the problem – the detail of the flow of
control. Even small changes in functionality require
large changes to the flowcharts thus wasting time and Task to Perform.
effort.
Task to Perform.
STANDARDS : there are several international
standards for flow charting, most achieved just as
control flowcharts were being considered obsolete.
The best known are ISO 1028 "Information Processing False
Test
- Flowchart Symbols" and the ANSI X3.5-1970
standard (now superseded by ISO 5807:1985).
True
STILL OF USE : flow charts can be a disaster when

used to model a system, use block diagrams or object
diagrams instead. Flowcharts can have a place in
modern design, usually when a small problem needs to
be solved- Stop
• Short code sections with complex if-then-else
Illustration 147: Traditional Flowchart
structure may be usefully modeled with a
flowchart.
• Tricky decision making can be described by a flow chart.
• Step by step instructions for people can be described well by a flow chart.
Business processes may be well described with a flowchart.
The maintenance instructions for Ericsson's AXE telephone exchanges are described by
flow charts.
LIKE A STATE DIAGRAM? A flow chart may seem to act like a state diagram in that an
arrow is followed if the condition is true. There are several big differences-
• Each square does not define the state of the system just a task to be completed.
• The system does not wait at a square until there is an activating signal (like a clock edge)
and a true condition on an arrow. Instead the task is competed and the exit arrow is
followed.

6.3 Activity Diagrams

Activity diagrams look suspiciously
like flowcharts with the symbols changed. Activity Diagrams
Activity charts also explain the flow of Start
control or “what happens next”.

Activity
[condition before
ELEMENTS of an activity chart include- transition allowed]
• Activity : a task or list of tasks to Start parallel

complete. An activity must be behaviour.
complete before it can be exited. *[the star shows

multiple triggers of
Activities are not objects. this type]
• Transitions : a trigger may stop Stop (

movement to the next activity. resynchronization)
Several triggers can exit any activity of parallel
behaviour.
thus providing an "exclusive or" End
function. This replaces the bulky

diamond shape in a traditional Make Tea
flowchart.
• Synchronization bars show when
parallel operation can start and when
it must end. Tea in Boil
Get cup.
pot. water.
[ask peoples
preferences]
WHEN TO USE : an activity diagrams is
just another form of flowchart and like Hot water in pot
Add sugar
and milk.
flowcharts they should not be used as a & allow to stand.
system design methodology but to help

with- KIDS
Pour tea into cups.
• Customer interaction : clarify with ME
the customer the sequence of events

that make up a complete task. Most Illustration 148: Activity Diagram
non-technical people can follow
activity diagrams and will help to iterative refine the activity (scenario) definition.
• Extract parallelism inherent parallelism of the problem. This can be important in
business modeling or when designing thread programming.
MORE: Activity charts have more features such as the ability to send a signal, and to block
until a signal is received. See http://cse.csusb.edu/dick/cs557/r1.html and
http://www.agilemodeling.com/artifacts/activityDiagram.htm

6.4 Resolving Flowcharts and Block Diagrams

Most engineers can read a block diagram very well but many cannot create one! This is
usually because the flowchart “what happens next” thinking is applied and so the result is a
flow chart.
>>> If you cannot create block diagrams you will be unlikely to get one
of the well paid system design or analyst jobs.
Example: consider a small system that aims to alert deaf people to the sound of a siren. A
microphone feeds into a threshold circuit that works out the background noise level. A separate
circuit extracts the frequencies found in the siren signal. Finally a detection algorithm looks at
the energy in the siren frequencies and the noise level, then decides if there is an alarm sound
present. If a siren is detected a light is flashed.
The flow chart and block diagram solutions are shown below.
Flow Chart Block Diagram
start
Microphone
Get siren
sample Frequency Frequency
analysis. spectrum.
Noise and
Update siren sound. Detection
threshold algorithm.
Adaptive
threshold
Siren
Filter input for setting.
threshold. Siren
siren sound.
status.
N Alarm light.
Siren Y
Light alarm.
Present?
Illustration 149: Flowchart versus Block Diagram Solution
Questions-
• Which solution is better at showing how the system works?
• Which solution is the best basis to start further design work?
• Which solution will help you split up the work so that the work can be done in parallel?
In each case the block diagram is the better solution BUT in most cases people end up drawing
a flow chart.

HOW TO STOP DRAWING FLOWCHARTS? This is easy for some people but quite
difficult for others. It depends on what skills you have learned so far more than native
intelligence. For example if you have worked a lot with procedural activities such as
programming then it's very hard to avoid drawing a flow chart.
Simple rules to help include-
• Every block must transform energy, information, or materials.
• Every vector must be named to describe the nature of this energy, information, or
materials.
• Decisions are always hidden inside a block.
(This can be hard for those who are good programmers!)
PRACTICE is needed to become good at drawing block diagrams. Make the most of tutorials
and the worked problems.

6.5 Mind Maps

Mind maps are a visual way to develop solutions and show information. A very good
example of a mind-map are the Why-Why and How-How diagrams that identify the root causes
of a problem and then help generate a range of solutions. These are extensively used in Quality
Assurance to find the source of problems and to plan improvements.
Why - Why Diagram : Poor Profit in a Software Company.
No formal estimating tools used.

No training in estimation.
Estimates wrong.
No analysis of previous projects.
No reward for good estimates.
No test specifcation written.

Reward mainly for quick coding.
Poor testing facilities
High bug fx
& service costs. Little labour time for testing.
No milestone reviews.
No full time testing staf.
No testing procedures defned.
Poor No quality plans.
Proft
Estimates wrong.
Competition not analysed.

Incompetent tenders.
Lose tenders. Customers not "softened up".
Poor customer interface.
Poor record.
Staf moral low.

Staf out of date.
Poor staf Poor tools.
productivity.
No reviews of work.
Lose good staf, wages.
No reward for achievement.
Procedures antiquated.
Problem General Cause Detailed Cause

Illustration 150: Why-Why Diagram

WHY-WHY PROCEDURE : there are several steps-

• A significant problem must be identified.
• The general causes of that problem are identified by asking "Why is this problem
happening". On a diagram link these causes to the problem.
If a detailed cause is identified think of a parent general cause and draw them in.
Do not get bogged down with detailed causes, try to develop general causes.
• Detailed causes : when there are no more general causes then for each general cause ask
"why does this general cause happen" and try to develop specific causes.
• Iterate and refine as discussed between detailed causes and general causes.
NATURAL PROBLEM SOLVING : the human mind tends to link from an initial problem
statement right down to a detailed cause. The intermediate steps are unconscious and usually
ignored. Why-why diagrams help the user to discover these intermediate causes and generate
more detailed causes.
HOW-HOW DIAGRAMS have a differently labeled three levels-
How-How Diagram : Poor Profit in a Software Company.
Use formal estimating tools.
Estimates made more Training staf in estimation.

accurately. Analyse previous projects.
Reward good estimates.
Write test specifcations.

Improve
Proft. Reward low bug rate.
Improve testing facilities.
Lower bug and
fault rates. More labour time for testing.
Start milestone reviews.
Have full time testing staf.
Goal. General Solutions. Specifc Solutions.

Illustration 151: How-How Diagram

COMMENTS
• Excellent communication mechanism : how-how and why-why diagrams are very good at
helping people understand a complex situation.
• Group discussion : the creation of why-why or how-how diagrams can be done by an
individual or by a group. In group discussions a large white-board is useful.
• Equivalence : the how-how and why-why diagrams are usually equivalent except one states
a problem and the other a solution. Only use one to the other.
• Staff attitude : the drawing of a why-why diagram can lead to a negative atmosphere. A
how-how diagram can be more positive.
• General causes must be considered first, interspersed with dives into detail and back up.
This stops tunnel vision, generates more ideas, and gives a better structure to the
problem/solution definition.
• Diagrams can get big, use a large page or put details on separate pages.
FREEMIND is an excellent free mind-map tool that can draw how-how and why-why
diagrams. It has problem that is annoying for 5 minutes, navigation and editing is based on
control key combinations. See Help->Key Documentation PDF to find essential hot keys to
move up and down and swap sides. This approach is actually better for regular use so it ceases
to be an annoyance quite quickly.
Illustration 152: Freemind is Documented Using Freemind!

EEET-2251 Digital Systems Design 1 : Project Life Cycles
7 Project Life Cycles

As projects get bigger so does the complexity and the chance of making a mistake that
costs money, reduces the effectiveness of the final product or service, or perhaps results in the
project being canceled. Fortunately most projects follow a similar path and so a “road map”
can be developed to help guide project managers.
UNIVERSITY EDUCATION DOES NOT HELP: yes we said this before and it's worth
saying again. At university you only work on small projects and so small project methods get
ingrained into your mind. When these methods are applied to larger problems the result is
usually a disaster.
Project life cycles will not be that useful at university but in real industry they are essential.
A PROJECT is a set of activities dedicated to the delivery of a product or service. Most

technical projects go through the same basic phases independent of the nature of the project.
Together these phases form a project life-cycle.
The basic life-cycle below can be used as a template for activities ranging from the quite small
to the very large. Each phase is described by a set of tasks, goals to seek, and problems to
avoid.
Basic Project Lifecycle
Project management : planning, monitoring, links to stake holders.
Labour, money, materials, schedule, external communications.

Concept
& deals. Product design and Operation, maintenance,
construction. extension.
Product spec. Faulty product.

Less faulty product.
Market & product analysis Test spec.

Product test.
& defnition phase. time
Illustration 153: Basic Project Lifecycle
• Concept and deals is where people start to understand what the project is, and make initial
checks and tentative deals with stake holders (those affected by the project).

• Analysis determines what the problem is, what a solution must achieve, risks, and so
generates specifications for the product and product test. It also helps to refine initial
planning estimates. Analysis looks at “what” must be built not “how” it will be built.
Many formal life-cycles ignore the vital market analysis or business case analysis.
Technology plans without purpose or market is a recipe for disaster.
• Product Design is the major concern of most technical staff. It determines “how” to build
and “how” to test the product.
• Product construction takes the design details and creates the real product.
• Product test covers the testing of the product against specifications, relevant operational
scenarios, and known problem areas.
• Operations, maintenance, and extension : covers the commissioning, operation in the field,
the rectification of errors, and modifications to help the product better serve the customer.
OVERLAP & TIME TO MARKET : most real world projects will overlap phases and
activities to get a quicker time to market ( a vital commercial goal).
The key risk is that work at one point will force a rework of work already done.
LIFE CYCLE ADVANTAGES include-

• Less chaos as people know what should happen now and in the future.
A good life-cycle is like a road map, it tells you where you are and where you can go next.
• Linkage between phases is smooth and current work is fit for the next phase.
• Work integration between workers on large projects becomes easier and has less mistakes.
• Resource allocation can be made to where it has most benefit.
• Scheduling can ensure things such as staff, information and tools are available when they
are needed. Project milestones predictions like final delivery will be more accurate if the
life-cycle is understood.
• Reviews can be positioned for maximum benefit, usually at the end of a phase.
• Measurement can be made of activities in terms of time taken, resources required, and
defects. Measurement can then guide continuous improvement.
• Generic risks and problems can be identified and resolved as early as possible. Ideally the
staff involved generate and update a checklist to guide themselves and others on later
projects.
• Good practices can be identified, and again a checklist generated.
• $ : real savings are made.

PROBLEMS : life-cycles can over systematize development and unintentionally-

• Hamper creativity by making it too onerous to change the product or development
methods.
• Waste labor : the burden of reviews and documentation can swallow large amounts of labor
time and divert people from the real job.
• Be boring : administration aspects can be boring.
• Create a bureaucracy : the administration layer becomes bloated, sapping money and
resources from the wealth creating part of the enterprise.
• Kill real goals : a process, such as a life-cycle, is only a means to an important goal.
A workplace with a heavy process orientation may cause staff to see following the process
as their first priority. Staff must keep the real goals in mind an alter processes if necessary.
DO PROCESSES MATTER? A life cycle approach is a process which directs work. How
important are processes compared to other aspects of a project such as good management?
Barry Boehm's COCOMO II software estimation method has looked at the contribution of
many factors to project success and failure. According to Connell (IEEE Software Nov/Dec
2000), statistical analysis shows that bad project processes or methodology will increase effort
by a factor of 1.43. It is notable that this factor, while important, is less than other influences
such as analyst capability ( 2.00), personnel continuity (1.59), and analyst experience (1.51).
While processes do matter, a company with high quality motivated people and poor processes
will outperform a company with lower quality people and good processes. It is even better to
have good people and good processes!
YOUR RESPONSIBILITY? A project will stand a much better chance of success if an

appropriate life-cycle is chosen very early in the project and then competently followed
through.
• If you have any management role you must ensure a life-cycle is chosen and used.
• If you have no management role then try talking politely about the issue to management,
always acknowledging their right to manage. Offer to develop a life-cycle “if you approve
the idea”.
• If all this fails consider moving jobs unless you enjoy frustration and chaos.

7.1 Waterfall Models & 2167A

The waterfall life-
cycle was developed around Waterfall Diagram
System
the concept of "specify then Feasability
build" as a linear sequence Validation
[Royce, 1970]
with very limited iteration

between adjacent phases.
Software Plans
& Requirements
Validation
ITERATION : the model
shows that work in any
phase normally causes Product
Design
changes to the design at the
previous stage. This comes Verifcation
about because both

designers and customer get Detailed
Design
a better understanding of
the problem as work Verifcation
progresses, and so wish to
alter the project to get a Code
better result.
Unit Test
Iteration is normal and to be
expected, especially for
software, so tools and Integration
methods must allow for Verifcation = Product

Are we building
iteration, but should help to the product right?
Verifcation
minimize the need for (Compared to the

iteration. specifcation.) Implementation
Note especially the Validation = System

Are we building Test
difference between the right product?
verification and validation (Does it fulfll a
Operations &
according to Royce. need in the real
Maintainance
world.)
Revalidation
Illustration 154: Waterfall Model
DOD-STD-2167A: in the
1970s the US military was beset by horrible cost overruns and project failures. They developed
a very detailed life-cycle based on the waterfall approach and this did help a great deal. The
foreword to 2167A indicates that "this standard will provide a basis for Government insight into
the contractor's development, testing, and evaluation efforts.".
The specifications are full of acronyms. The reader will need to make frequent reference to the
appendices which explain the acronyms.
The life-cycle is best explained by the following diagrams-

DOD-STD-2167A : Integrated Hardware & Software Lifecycle.
Hardware SRR : System Requirements Review.

Unit
Copyright © Pj Radcliffe 2018

SDR : System Design Review.
Tests. SSR : Software Specifcation Review.
Fabrication. PDR : Preliminary Design Review.
CDR : Critical Design Review.
Detailed TRR : Test Readiness Review.
Design. PCA : Physical Confguration Audit.
PCA FQR : Formal Qualifcation Review.
Preliminary
Design.
CDR * : May be multiple reviews and may
Hardware
Requirements be integrated with hardware reviews.
Analysis. PDR
System System System

Requirements SRR Design. SDR Integration PCA
Analysis. SSR & Testing.
*
PDR FQR
Software
Requirements *
Illustration 155: MIL STD 2167A

CDR
Analysis.
Preliminary
Design. Testing &
Detailed PCA Evaluation.
Design. TRR
Coding &
Unit Test. Software
Component
Source : Pg 10, DOD-STD-2167A 1988. Test. Software Product Use
Confguration & Deployment.
Item Test.
Page 135
Project Life Cycles
DOD-STD-2167A : Detailed Software Lifecycle.
System System Software Preliminary Detailed Coding & Component Confguration System
Requirements Design Requirements Design Design. Unit Integration Item Integration
Analysis. Test. & Testing. Testing. & Testing.
Phase
Analysis.
Preliminary System • Software ° Software ° Source ° Operational & Same as

System Specifcation. Design Design. Code
Copyright © Pj Radcliffe 2018

Support confguration
Specifcation. Docs (prelim). Listings.
Documents. testing but
System
this time for
Segment
the full
Design Software
Software Software Tests Software Test, product.
Document. Test Description, Descriptions, Test
Reports. • = Part of baseline.
Plan. Cases. Procedures.
Preliminary Software • ° = Part of
Software Requirements Development
Source Updated
Requirements Specifcation. Confguration.
Specifcation. Code. Source Code.
* = May be deferred
to after system
Preliminary Preliminary Version * integration &
Interface • Interface
Interface Interface Description testing.
Requirements Design
Requirements Design Documents.
Specifcation. Document.
Specifcation. Document.
Software Software •
Delivered Products &Documents

Development Product *
Plan. Specifcations.
*
System System Software Preliminary Critical Test Functional &
Requirements Design Specifcation Design Design Readiness Physical
Review. Review. Review. Review. Review. Review. Confg Audits.
Reviews
Product
DOD-STD-2167A
Functional Allocated
Baseline Development Confguration.
Baseline. Baseline. Baseline.
Source : Pg 12 & 13, DOD-STD-2167A 1988.

Key lessons from 2167A include-
• Get interfaces defined early.
Suggested Activity : obtain a copy of • Get test plans defined early.
2167A (see PjR) and make a cut down • Reviewing early stages is worthwhile, code review isn't.
version to suit your own enterprise. • Traceability from initial specification to all resulting activities is vital.
Page 136
Project Life Cycles
BILLION $ DIAGRAMS: the 2167A life-cycle diagrams have been called “billion dollar
diagrams” because they seek to avoid billions of dollars of money lost in wasted development
by the US military. Note especially the 4 lessons noted in the diagrams.
ROLL YOUR OWN: Unlike many life-cycle standards, 2167A mandates particular documents
be generated, reviews be done at particular times, and good practices are followed. There are
useful lists of good practices especially for management of a project. The standard must be
tailored to suit each application by using the tailoring guide MIL-HDBK-287.
COST : Martin has studied many military projects that use 2167A based and concludes that
satisfying 2167A adds between 30% and 50% to the cost of a project [COAD91, pg 207].
This cost is seen as worthwhile because the 2167A approach dramatically increased the amount
of software delivered that is actually useful, and reduced defects.
Costs can be dramatically lowered if the documentation requirements are reduced. This is
especially applicable to smaller projects.
SUPERSEDED : 2167A was superseded by MIL-STD-498 which was in turn superseded by

IEEE 12207. 2167A still stands out as a tremendous example of a waterfall life-cycle.
THE BIG PROBLEM …. The waterfall life-cycle was a great improvement on the previous
approaches to managing projects, especially software projects, but it was discovered there was
one killer problem-
The specifications are not tested until the customer uses the product!
If the specification was wrong then the project will have to be abandoned
or an expensive rework cycle started.
In reality most specifications are wrong or miss key items and so a likely outcome is a defective
product that must be reworked. This rework represents a great deal of lost prestige, time, and
money.
The Breakdown-Buildup model that follows illustrates this problem in more detail.

BREAKDOWN - BUILD-UP DIAGRAM offers some important philosophical views on the

nature of the waterfall life-cycle.
Breakdown - Buildup Lifecycle

Problem Product
Business case. Customer use.
Business needs. Delivered product.
Analysis Phase. Acceptance test.
Specifcation. Working system.
Design Phase. System Test
Procedure Working
defnitions. units.
Coding Phase. Unit test.
Compilable code. Code

Hardware Design/Compilable
Link between where errors are caused and the usual places they are discovered.
Illustration 156: Buildup-Breakdown Life-cycle
KEY IDEAS from the breakdown-buildup diagram include-

• Breakdown : the phases from analysis to coding represent a breakdown of a problem into
its component parts and its eventual solution, for example compilable code or an electronic
circuit design. These phases represent the design side of the process.
• Build-up : the phases from unit test to customer use represent the progressive integration of
units to form a full, working system. These phases represent the testing and debugging
phase of the process.
• Dangerous errors: errors may be missed in say the business case, and not be discovered
until customer use. This style of error is very dangerous and can ruin a project, and even a
whole organization as the project is useless and the client may refuse to pay.
• Consultation : in order to avoid future problems, staff at the end of a gray arrow should
have input into the phase at the start of the arrow.

GET IT RIGHT EARLY : the cost of fixing faults varies tremendously. Barry Boehm
[BOEH81] collected data from several software and engineering organizations which suggested
that on average fault costs are-
Specification fault Relative Error Source & Point of Detection

found & fixed at- cost to fix. Work Flow
Error Flow
Specification. 1 Requirements
Analysis
Detailed Design. 3
Errors
Coding Stage. 7 made in System
these Design
In-house Debug. 20 stages-
Customer premises. 100 Unit Design
Current projects report the same type of

figures. Unit Test
are not
detected
*** These figures should act a tremendous until
stimulus to find ways to detect and eliminate these System Test
errors as early as possible in the project. This stages.
should be an very important goal for all
engineers and managers. Customer
Use
Illustration 157: Error Source and Discovery
VARIATION : there is considerable variation between projects, the figure of 100:1 varies
from 5:1 for small non-critical programs up to astronomical figures for failed NASA space
probes
(Boehm & Basili, IEEE Computer, Jan 2001, p 135-137).

7.2 Spiral Life-cycle Model

In 1988 Barry Boehm was working for TRW, a company with many military contracts.
He found the waterfall life-cycle model was not adequate as time and cost control issues
became more significant. Boehm wanted a life-cycle model that would-
• force early testing of specifications against real needs,
• force developers to discover and evaluate alternatives and risks,
• force developers to choose a development process that suits the project.
The result was the now famous Spiral Lifecycle [BOEH88] that is built around consideration of
alternatives, risk analysis and risk resolution. It is particularly suited to projects with
uncertainties, vague specifications, or new projects which are different to previous projects.
Spiral Model 1. Determine 2. Evaluate

objectives,
• The distance from the origin (•) alternatives,
alternatives,
identify &
to the spiral represents constraints. resolve risks.
cumulative development effort.
• The angle relative to the start
represents time.
• Each loop represents a proof of
concept, prototype or version of start
the product.
• All loops follow steps 1 to 4.
• The last quadrant starts when all 4. Plan
risks are removed. This last section next 3. Develop,
is the equivalent of a waterfall life phase.
verify,
cycle. this phase.
• Planning considers resources, labour, time plans,

stake holders, and key goals.
Illustration 158: Spiral Life-cycle
Spiral management summary : Boehm suggests that each loop should be planned and reported
in summarized point form. His generic headings include-
* Objectives. * Constraints. * Alternatives
* Risks. * Risk resolution. * Risk resolution results.
* Plans for next phase. * Commitment (resources for next phases)
* Validation or verification results.
STARTS AT STEP 1? Some workers suggest the spiral loop sequence should be really steps
4,1,2,3. In other words the first phase is the planning phase.

WIN-WIN SPIRAL MODEL [IEEE Software, July 1996, pg 78] [IEEE Computer, July 1998,
pg 33-44]. Software lifecycles are often criticized for being too introverted and technology
oriented as they ignore customers and marketing considerations. In response to this Boehm has
modified his Spiral Model to create the Win-Win Spiral model. The phases for each iterative
loop now become-
1. Identify next level stake holders.
2. Identify stake holders win conditions ( interviews, specifications, ...)
3. Reconcile win conditions, establish objectives, constraints, risks and alternatives.
4. Evaluate product and process alternatives. Resolve risks.
5. Define next level of product and process including partitions (subsystems).
6. Validate product and processes definitions ( initially specifications, later on prototypes
and finally the code).
7. Review and commit : check feasibility, decision to continue, make resource and time
commitments for the next cycle.
Reviews : in order to meet review needs Boehm suggests three reviews-

• LCO : life cycle objectives, suspiciously like a specification.
• LCA : life cycle architecture, suspiciously like a Design Report.
• IOC : initial operational capacity, a check on all activities and resources required to get
the initial operational system up and going.
ADVANTAGES & DISADVANTAGES of the spiral style life-cycles compared to the

waterfall style include-
+ Estimation experience superior : each of the several cycles is estimated, as distinct from
the one estimation of the waterfall model. Estimators get much more experience as
feedback comes to them much more frequently and quickly.
+ Risk and customer orientation are key aspects to good management.
+ Alternative consideration encourages innovation.
? Less natural milestones, reports, aborts, or agreement points exist. These must be added in
as appropriate.

7.3 Prototyping Life-cycle

While Barry Boehm was working on engineering projects the software community had
developed their own version of the spiral model called simply the Prototyping Life-cycle. In
many projects the final form of the deliverable product cannot be determined from talking,
paper and pencil analysis, and a written specification. The prototyping life-cycle creates a
series of prototypes that are shown to the stakeholders, especially the users. The aim is to
engage the stakeholders, and by mutual agreement, change the prototype until it specifies an
acceptable product.
The prototype becomes a specification often aided by a small written specification. The
prototype need not operate as per the final product, just have the right look and feel. It may
also use different hardware to the final target.
Prototyping Lifecycle
Changes required.
Gather Quick Quickly build Customer

requirements. (re)design. prototype. evaluation.
Post Prototyping Activity
OK : evolve from prototype.

OK : throw away prototype.
Traditional Traditional Coding and System Delivery.

systems design. detailed design. unit test. test.
Illustration 159: Prototyping Lifecycle
ADVANTAGES of prototype development compared to waterfall development include-

• Fast : the cycle of prototype design-build-evaluate can be done very quickly if good tools
are available and the client is willing to be involved.
• Right features : close customer contact is an essential part of the prototyping approach and
this usually results in a product the customers find useful without annoying or missing
features.
• Priority items first : high priority features can be implemented first, followed by less
important features.

• No specification : helps cope with those clients who just wont write or read a complete
specification.
DISADVANTAGES of prototype development compared to waterfall development include-

• Prototypes normally require considerable re-engineering to turn them into the final product.
• Messy unmaintainable structures can result because the focus is on inputs and outputs, and
the structure gets ignored.
• Large or distributed projects do not work well with an iterative style development.
Iterative development tends to make many changes to code and hardware. In large projects
the cost of integrating and testing these changes can be very high.
• Non-user related specifications and needs can be forgotten as prototyping focuses on
immediate user needs. Examples of such needs include execution time limits and
portability requirements.
WHEN TO USE PROTOTYPING-

• When requirements are uncertain.
• When there are complex GUI screens.
• When clients wont/can't/never get around to writing or reading a specification.
WHEN NOT TO USE prototyping-

• When there is a clear specification that defines the detail of the solution.
(In such a case the waterfall life-cycle tends to be faster and cheaper.)
• When the structure of software code is very important, a requirement for most larger
programs that must be maintained and extended in the future.
The solution here is to design the system as a whole using say UML (Unified Modeling
Language) or even just block diagrams, and then use prototyping on the GUI or other
uncertain components.
• When the each prototype loop takes a long time or is too costly, which can be the case
with hardware.

WHAT IS EACH LOOP? Each loop should be short and result in something the client can
evaluate. If possible get clients to evaluate the prototype on a regular basis. Loops may be-
• Development of a basic written specification, try to keep these short and leave GUI
specifics to later prototypes.
• Simulations of the final product using paper, a quick screen painter, even a word
processor. Consider using hardware and software that the final product lacks to speed
development.
The aim is to show look and feel of the final product not create the final product.
This approach is useful if the final product development process is slower and more costly
than the use of simulation tools such as Matlab or a word processor.
• Some element of functionality using the real system.
• An incremental change or new item of functionality.
• The final loop creates the delivered product.
KEY ADVANTAGES of prototyping include-

• Becomes specification : the prototype or simulated system, as modified by customer
requests, can be used to replace a large part of the traditional written specification. The
written material which is still required is much reduced in both volume and complexity.
High performance aircraft are often sold on the basis of a flight simulator. The aircraft is
reworked until it meets the simulator developed specifications.
Simulation has become the preferred method of specification when there are uncertain
requirements, or if changes are likely.
• Greater customer involvement can occur when there is a prototype to check. Only a few
masochists are willing to check a long written specification but almost anyone is willing to
have a try on a prototype. The increased communication sorts out potential problems early
in the project.
• Better customer satisfaction : specifications are difficult to read in detail and small but
important factors are often overlooked. Such factors are evident with a prototype and don't
get to annoy the customer in the real system.
• Second order effects are side effects of the original design that become evident in a
prototype. Prototyping allows them to be discovered and eliminated early in the project.
• Real and imaginary problems are quickly sorted out. This is useful when an "idea hit man"
is trying to block your ideas. A cheap prototype can usually show that the idea is viable.
• Maintainability, validation and verification are all much easier.
• Sales can be made before the real product has been finished. Prospective clients can be
shown a prototype and be told "It will work just like this.".

THROW AWAY & EVOLUTIONARY : throw away prototypes are those where the code or
hardware will not be used in the next phase, only the look and feel is kept. Evolutionary
prototypes are where the code or design will be used after the demonstration.
Characteristic Conventional Evolutionary Prototype Throwaway Prototype

Development
What is known at Detailed, correct Basic operation clear. Very little, great
project start. specification. uncertainty.
Development Rigorous. Rigorous. Quick & dirty
approach.
What is built Entire system. Well understood parts Poorly understood parts.
first.
Key goals. Depends on project. Easy modification. Minimum development
time.
Purpose. Satisfy all Uncover unknown Clarify poorly
requirements. requirements then understood
evolve. requirements then throw
away.
Main problems. Specifications not Not maintainable, Messy code/hardware
tested till late in the changes require much put into an evolutionary
project. effort. prototype.
THROW AWAY TO EVOLUTIONARY ? Attempting to turn a throw away simulation into

an evolutionary prototype is usually a recipe for disaster. The quick and dirty architecture and
shortcuts make extension difficult, expensive, and slow. It is quite acceptable to first develop
throw away prototype(s) then an evolutionary prototype.
AGILE DEVELOPMENT life cycles are basically a prototyping life cycle with extra rules
and processes added. Most software is written using an agile life cycle, typically SCRUM or
XP (Extreme Programming).
Most agile approaches write test cases before the hardware or software is created. This has
been found to dramatically reduce defects.
SOME CASE STUDIES of simulation include-

• Ericsson, a producer of large Automatic Call Distributors (for operator answered telephone
systems) sold their first three systems purely on the basis of a simulation run by an IBM-
PC and a prototype panel. These sales represented about $1 million in 1987.
• Xerox prototype many of their photocopier controls using a prototyping tool called
Trillium.

EEET-2251 Digital Systems Design 1 : Worked Problems
8 Worked Problems
This section contains worked problems to help you consolidate your understanding of
each area. If you feel your understanding of a topic is good then you can leave these problems
until closer to exam. If you feel less certain then try them directly after the lecture covers the
material, and then again later just before the exam.
The problems here focus on processes and procedures you must be able to use. Straight
memory based questions can be seen in the exam hints guide.
Consider looking on the web for examples and worked problems. There is a lot out there.
DON'T PEEK! If you just peek at the answers you may as well throw away these worked
problems as you will ruin any educational value. Have a solid try your self first, look at the
lecture notes, look at your lab work, and only when finished or stuck look at the answers.
8.1 Problems Without Answers
8.1.1 Number Systems
CONVERSION BETWEEN BINARY AND DECIMAL is a key skill and will no doubt get
practiced in any exam. In most of this course the numbers were limited to 5 binary bits (0-31
decimal) because that is the limit of K-Maps. In later work you will normally work with 8 bit
binary (0-255 decimal) as that is what most low end microprocessors use. See the appendix for
the notes on binary to decimal conversion.
Convert to decimal (easy): 00110, 01001, 11100, 10101, 01010, 11001, 00011, 00000
Convert to decimal (harder): 01011100, 11001101, 00111100, 10101010, 01010101
Convert to binary (easy): 23,14, 31, 3, 19, 30, 7, 8, 16, 4
Convert to binary (harder): 123, 80, 128, 200, 250, 99, 100
GRAY CODE has one particular feature, state that feature and where Gray codes can be
useful.
Create a Gray code for three binary bits (ensure the wrap around from last to first also works).

8.1.2 Boolean logic
Simplify: C + BC
Simplify: AB(A + B)(B + B)
Simplify: (A + C)(AD + AD) + AC + C
Simplify: A(A + B) + (B + AA)(A + B)
Simplify: AB + BC(B + C)
8.1.3 Basic Logic
SWITCH LOGIC: using SPDT switches design a circuit intended for mains power. There are
two switches driving one light bulb, from either switch it must be possible to turn the light on
and off. What logic function best describes the operation of these switches?
DRAW THE GATES for the following Boolean expressions.
Draw a logic circuit for (A + B)C.
Draw a logic circuit for A + BC + D.
Draw a logic circuit for AB + AC.
Draw a logic circuit for (A + B)(C + D)C.

TRUTH TABLE: the following problem was posed in the lecture notes. If you have not tried
to do it please try now.
1 A 1 A B C Z Y X W
A Z Y
C & C ≥1 0 0 0
C C
B & =1 0 0 1
B
0 1 0
C 0 1 1
C 1 0 0
A & X A &
≥1 W 1 0 1
A A &
& & 1 1 0
B B
C & C 1 1 1
&
B B
Illustration 160: Combination Logic Exercise

8.1.4 Simple K-Maps

The web has many examples of simple K-Map solutions which you can find and practice.
Here are a few more.
Cropper Printer Interlock: the old printing presses had no safety interlocks and so it was
possible to have it squash or chop of the fingers of an unwary printer. Imagine two large metal
plates which carry an engraving of what is to be printed. These are coated with ink, a piece of
paper inserted and the plates squashed together. When the plate are separated the paper has the
ink imprinted on it's surface.
This small logic circuit aims to add an interlock to stop the
motor if there is a problem. +5v
• There is a foot switch to make the printer press the
plates against the paper. This input is F and is active
high, a logic one indicates the switch has been a
pressed. Z
b Logic
• There are two safety switches which check if the Gates
safety guard screen has been pulled down so the f
printers hands cannot be between the plates. These
inputs are A and B and are also active high.
• For the printer to start a run the foot switch must be
active and one or both of the guard switches. This 0v
output is Z and is active high. Illustration 161: : Printer Safety Interlock
Your Task: draw a truth table for the logic function, draw a K-Map and minimize the logic,
draw the gates for an AND-OR implementation and an all NAND
implementation. Z AB
BC
00 01 11 10
Hints: to make sure your answers look the same as the ones in the 0 1 . . 1
A
F
answer section label your truth table with the headings "Index F A B 1 . 1 1 .
Z Comments " where the comments list what is happening with the
circuit. Your K-Map should have the layout as opposite. Illustration 162: : Suggested
Layout
Extension: create the logic using switches between a 240v power source and the start print
power input. Can you simplify it to 3 switches?
MANY ONES: draw a K-Map where the only cell which is 0 is A=1,B=1,C=1 and D=1.
Using K-Maps create a minimal Boolean equation.
Now invert the K-Map so the only cell with a 1 is A,B,C,D=1.
Verify that the first solution is an inversion of the second solution.

8.1.5 K-Maps and Motor Control

The circuit opposite
shows a simple motor
controller. The case of +5v
the logic points indicate
if they are active high +5v
w
or active low. For f fwd
example the lower case x
input f (forward) is b Logic M
active low, when the Gates Y
g
button is pressed to rev
make the motor go
Z 0v
forward the logic value
is zero (0v), when the
button is not pressed 0v
and forward is not Illustration 163: : Motor Control via Logic
desired the logic value
is one (+5v). The upper case output Z is active high, when Z is high the FET connected to it
passes current, when Z is low the FET conducts no current.
There are three input switches forward (f), reverse (r) and go (g). The buttons can be pressed
independently. For the motor to move g must be pressed and either f or b. Any other input
combination must result in all FETs being off so the motor cannot move.
The motor is shown as an M in a circle and is driven by four FETs. The P channel FETs
connected to w and x will pass current if their input is low (0v), the N channel FETs will pass
current when Y and Z are high. To send the motor forward x is low, Z high, w high, and Y low
thus passing current through the motor in the direction of the small arrow. To reverse the
current and send the motor backwards w is low, Y is high, x is high, and Z is low. Under no
conditions can x be low and Y high, or w low and Z high, because there will then be a direct
short from +5v to zero volts through two FETs.
Your task: create a truth table with inputs f,b,and g, and outputs w, BC
fb
Output
x, Y and Z. Draw a truth table, draw a K-map for each of the four
00 01 11 10
outputs, derive Boolean logic for each output, draw a NAND
implementation, and simulate the result. 0 1 . . 1
A
g
Hint: to ensure your work match the solutions use truth table 1 . 1 1 .
headings "Index f b g w x Y Z comments" and the K-Map format Illustration 164: : Motor K-
Map
opposite. The comments field should explain what is happening, for
example fwd, bwd, or off. There are two solutions, one with a
solution just for w, and a second solution at the end of the solutions section for all of the
outputs. If you can't do the problem reread the notes and look at the examples again, if that
fails look at the first solution.
*** Just peeking will make life easier but you wont learn as much as trying hard yourself first.
Question: why would you be reluctant to entrust this task to software in a microprocessor or a
PC?

8.1.6 Five Input K-Maps

Draw K-Maps for the following truth tables and echoed Not echoed
create the minimized Boolean logic for the four outputs.
Index ABCDE Z Y X W
0 00000 1 . 1 1
1 00001 1 . 1 1
2 00010 1 . . .
3 00011 1 . 1 .
4 00100 . . . 1
5 00101 . . 1 .
6 00110 1 . 1 .
7 00111 1 . . .
8 01000 X . X .
9 01001 X . X .
10 01010 1 1 X .
11 01011 1 1 X .
12 01100 . . X .
13 01101 . . X .
14 01110 X . X .
15 01111 . . X .
16 10000 . . X 1
17 10001 1 . X 1
18 10010 . . X .
19 10011 1 . X .
20 10100 X . X 1
21 10101 . . X .
22 10110 1 . X .
23 10111 1 . X .
24 11000 . 1 X .
25 11001 1 1 X .
26 11010 . . X .
27 11011 1 . X .
28 11100 1 . X .
29 11101 X . X .
30 11110 . . X .
31 11111 1 . X .

8.1.7 Synchronous Circuit Analysis
COUNTER ANALYSIS: the

circuit opposite purports to be a
counter. Form a truth table for
the combinational logic that
feeds the three D flipflop inputs
and from that draw a state
diagram for the counter.
Comment on the count
sequence and the nature of the
counter. Comment on any
weaknesses in the design.

8.1.8 Synchronous Circuit Design 1

You have been commissioned to design a dead-man pedal system for a light rail engine
carriage. The dead man pedal has two switches, one which is closed if the driver holds the
pedal down too far, and a second switch which becomes closed if the pedal is left too far up. If
the driver does not hold the pedal in the middle then the pedal is moved up by a spring to the
upper limit and causes the upper switch to close. Only if the pedal is held in the middle will
both switches be open.
A 12 volt power source is switched by these switches and is input to the logic system.
If the dead-man pedal is activated then a counter starts counting from zero and increments by
one every second. After 4 seconds the output Warn goes high to indicate a warning and this
stays on while P is still high. After 7 seconds an output brake goes low to indicate that the train
should automatically brake, while P remains high Warn stays high and brake stays low. If at
any point the dead man pedal is returned to the middle position the counter returns to zero,
brake to high and Warn to low.
Your task is to design a Moore style synchronous circuit to implement this system. You must
use HC logic and D flipflops.
A) Draw a schematic of the switches so that there is one input to the combinational logic of the
synchronous circuit, an active high input called Problem which is high if the dead man pedal is
not in the middle position. Draw the truth table for the two switches and the one output and
state which logic function you have created with this configuration.
B) Using the single input from the switches, P, as an input to the combinational logic design a
synchronous circuit using D flipflops that will implement the specification above. Use “W” for
the warning output and “b” for the braking output. Assume you have a one second square wave
available.
C) Outline any weaknesses you see in the proposal, practical design considerations, and any
ways in which the design might be simplified.


Design a sequential logic circuit to implement a simple count sequence that will be used
to drive a three stator electric motor.
The input A controls the count direction.
The states are held on two D flipflops with outputs Q1 and Q0.
The outputs are X,Y and Z.
Q1Q0=3 gives XYZ=011, Q1Q0=2 gives XYZ=101, Q1Q0=1 gives XYZ=110,
Q1Q0=0 gives XYZ=111.
The count sequence for Q1Q0 given A=0 is 3,2,1,3 ... and when A=1 is 3,1,2,3 …
When Q1Q0=0 the next state is 0.
Your solution should proceed as follows-

 Draw the state diagram for the system.
 Draw the next state table for a D flip flops.
 Draw the K-Map to create the combinational logic to drive D1 and D0 and so derive
minimized Boolean algebra equation for D1 and D0.
 If necessary draw K-Maps to convert Q1Q0 to X, Y and Z and so derive the Boolean
equations for creating X, Y and Z from Q1 and Q0.
 Finally comment on the advisability of the design of state Q1Q0=0.
8.1.10 River Height Indicator for Third World Countries

The number and intensity of cyclones and typhoons has definitely increased in recent
years due to climate change. This means that sudden torrential rain may cause very large rises
in river levels that are a great danger to down stream communities. This project aims to
produce a cheap river level indicator that can be placed in remote areas and report river levels
to central authorities who can then alert people by national radio stations.
Your tasks are as follows-
• Briefly discuss constraints and risks you can see in this project.
• Who would you talk to before going further with this project?
• Draw an analysis mode FBD.
• List and select alternatives for each block.
• Draw your implementation FBD for your selected alternatives.
• Comment on new risks and problems you have uncovered or old ones removed.

8.1.11 FBD for Hospital Ward Automation

This application of FBDs is slightly different. In this problem you are given a solution as
a rambling verbal narrative but with many mandated ( compulsory) items of equipment. As part
of the standard "divide and conquer" design process you must form a FBD and identify risks.
The FBD should have the specific solutions demanded by the customer but keep non-mandated
blocks as generic.
The system you are to implement will control a hospital ward using web technology.
• The system is built around IBM-PCs running a Windows operating system.
• Communications is via local Ethernet and the Internet protocols.
• All sensors will be Internet nodes.
• Speed of response shall be 10ms from a reading becoming available from a sensor, to the
application program receiving it on the appropriate PC.
• Reliability shall be one crash per 10 years.
• All power supplies shall be battery backed up so if mains fails all equipment can continue
operating for 3 hours.
• All controllers (such as oxygen valves) will also be Internet nodes, controlled from a PC.
• Speed of response shall be 10ms from control data being sent by a control program, and
that data being received on the appropriate PC.
• All sensors, databases, and controllers will be accessible world wide to enable "distance
doctoring".
Draw a Functional Block Diagram of the system. Be careful to label the boxes and vectors
with meaningful names. Include mandated solutions but keep other blocks generic.
Create a risk analysis table. Experienced and successful project managers always track risks
and actively seek to eliminate those risks. Create a table where column one lists risks to the
proper operation of the system, and column two what action might be taken to eliminate that
risk.
After finishing your risk table state whether the project looks feasible, or should be abandoned.

8.2 Problems with Answers
8.2.1 Number Systems
CONVERSION BETWEEN BINARY AND DECIMAL is a key skill and will no doubt get
practiced in any exam. In most of this course the numbers were limited to 5 binary bits (0-31
decimal) because that is the limit of K-Maps. In later work you will normally work with 8 bit
binary (0-255 decimal) as that is what most low end microprocessors use.
Convert to decimal (easy): 00110, 01001, 11100, 10101, 01010, 11001, 00011, 00000
Answers: 6, 9, 28, 21, 18, 25, 3, 0
Convert to decimal (harder): 01011100, 11001101, 00111100, 10101010, 01010101

Answers: 92, 205, 60, 170, 85
Convert to binary (easy): 23,14, 31, 3, 19, 30, 7, 8, 16, 4

Answers: 10111, 01110, 11111, 000111, 10011, 11110, 00111, 01000, 10000, 00100
Convert to binary (harder): 123, 80, 128, 200, 250, 99, 100
Answers: 1111011, 01010000, 10000000, 11001000, 11111010, 01100011, 01100100
GRAY CODE has one particular feature, state that feature and where Gray codes can be
useful.
Create a Gray code for three binary bits (ensure the wrap around from last to first also works).
Answer: Gray coded numbers only have one bit change between adjacent numbers. This can be
very useful for mechanical shaft encoders to avoid false states.
It helps to write out the number of 1's to use for each number. The pattern used here was-
0, 1, 2, 1, 2, 3, 2, 1
There are several possible gray codes for 3 bits, here are two-
000, 001, 011, 010, 110, 111, 101, 100
000, 100, 110, 010, 011, 111, 101, 001

8.2.2 Boolean logic

Thanks to http://sandbox.mc.edu/~bennet/cs110/boolalg/simple.html
Note T=1=true.
Simplify: C + BC:
Expression Rule(s) Used
C + BC Original Expression
C + (B + C) DeMorgan's Law.
(C + C) + B Commutative, Associative Laws.
T+B Complement Law.
T Identity Law.
Simplify: AB(A + B)(B + B)

AB(A + B)(B + B) Original Expression
AB(A + B) Complement law, Identity law.

(A + B)(A + B) DeMorgan's Law
Distributive law. This step uses the fact that or distributes over
A + BB and. It can look a bit strange since addition does not distribute over
multiplication.
A Complement, Identity.
Simplify: (A + C)(AD + AD) + AC + C

(A + C)(AD + AD) + AC + C Original Expression
(A + C)A(D + D) + AC + C Distributive.
(A + C)A + AC + C Complement, Identity.
A((A + C) + C) + C Commutative, Distributive.
A(A + C) + C Associative, Idempotent.
AA + AC + C Distributive.
A + (A + T)C Idempotent, Identity, Distributive.
A+C Identity, twice.
You can also use distribution of or over and starting from A(A+C)+C to reach the same result
by another route.

Simplify: A(A + B) + (B + AA)(A + B)

A(A + B) + (B + AA)(A + B) Original Expression
Idempotent (AA to A), then Distributive, used

AA + AB + (B + A)A + (B + A)B
twice.
Complement, then Identity. (Strictly speaking, we
AB + (B + A)A + (B + A)B also used the Commutative Law for each of these
applications.)
AB + BA + AA + BB + AB Distributive, two places.
Idempotent (for the A's), then Complement and
AB + BA + A + AB
Identity to remove BB.
AB + AB + AT + AB Commutative, Identity; setting up for the next step.
AB + A(B + T + B) Distributive.
AB + A Identity, twice (depending how you count it).
A + AB Commutative.
(A + A)(A + B) Distributive.
A+B Complement, Identity.
Simplify: AB + BC(B + C):

AB + BC(B + C) Original Expression
AB + BBC + BCC Distributing terms.
AB + BC + BC Apply identity XX=X.
AB + BC Apply X+X=X
B(A+C) Factor out B.

8.2.3 Basic Logic
SWITCH LOGIC: using SPDT switches design a circuit

intended for mains power. There are two switches driving A B
one light bulb, from either switch it must be possible to
turn the light on and off. What logic function best
describes the operation of these switches? Source Load
.
Answers: logic function is most related to XOR/XNOR.
DRAW THE GATES for the following Boolean expressions.

Thanks to http://sandbox.mc.edu/~bennet/cs110/boolalg/gate.html
Draw a logic circuit for (A + B)C.
Draw a logic circuit for A + BC + D.
Draw a logic circuit for AB + AC.
Draw a logic circuit for (A + B)(C + D)C.

TRUTH TABLE: the following problem was posed in the lecture notes. Here is the solution.
1 A 1 A B C Z Y X W
A Z Y
C & C ≥1 0 0 0 1 0 0 0
C C
B & =1 0 0 1 0 0 0 0
B
0 1 0 1 0 1 1
0 1 1 1 0 1 1
C C
A & X & 1 0 0 1 0 0 0
A W 1
A ≥1 & 0 1 1 0 1 1
& A &
B B 1 1 0 1 1 0 0
C & C 1 1 1 1 0 1 1
&
B B
Illustration 165: : Truth Table Solutions

8.2.4 Simple K-Maps

The web has many examples of simple K-Map solutions which you can find and practice.
Here are a few more.
Cropper Printer Interlock: the old printing presses had no safety interlocks and so it was
possible to have it squash or chop of the fingers of an unwary printer. Imagine two large metal
plates which carry an engraving of what is to be printed. These are coated with ink, a piece of
paper inserted and the plates squashed together. When the plate are separated the paper has the
ink imprinted on it's surface.
This small logic circuit aims to add an interlock to stop the
motor if there is a problem. +5v
• There is a foot switch to make the printer press the
plates against the paper. This input is F and is active
high, a logic one indicates the switch has been a
pressed. Z
b Logic
• There are two safety switches which check if the Gates
safety guard screen has been pulled down so the f
printers hands cannot be between the plates. These
inputs are A and B and are also active high.
• For the printer to start a run the foot switch must be
active and one or both of the guard switches. This 0v
output is Z and is active high. Illustration 166: : Printer Safety Interlock
Your Task: draw a truth table for the logic function, draw a K-Map and minimize the logic,
draw the gates for an AND-OR implementation and an all NAND
implementation. Z AB
BC
00 01 11 10
Hints: to make sure your answers look the same as the ones in the 0 1 . . 1
A
F
answer section label your truth table with the headings "Index F A B 1 . 1 1 .
Z Comments " where the comments list what is happening with the
circuit. Your K-Map should have the layout as opposite. Illustration 167: : Suggested
Layout
Extension: create the logic using switches between a 240v power source and the start print
power input. Can you simplify it to 3 switches?

+5v Index F A B Z Comments

0 0 0 0 . Foot off
1 0 0 1 . Foot off
2 0 1 0 . Foot off
a 3 0 1 1 . Foot off
b Logic Z 4 1 0 0 . Guards off
Gates 5 1 0 1 1 B guard on
f 6 1 1 0 1 A guard on
7 1 1 1 1 Both guards on
0v
Z AB
BC F F
& A & Z
00 01 11 10 A Z
>=1 &
0 1. . . 1. F F
A
F & &
1 . 1 1 1. B B
Z = F.B + F.A = F. (A + B) A
F
Start Print
240v power B
Illustration 168: : Cropper Printer Solution
MANY ONES: draw a K-Map where the P CD Q CD

only cell which is 0 is A=1,B=1,C=1 and
00 01 11 10 00 01 11 10
D=1.
00 1 1 1 1 00
Using K-Maps create a minimal Boolean
equation. 01 1 1 1 1 01
AB AB
Now invert the K-Map so the only cell 11 1 1 . 1 11 1
with a 1 is A,B,C,D=1. 10 1 1 1 1 10
Verify that the first solution is an
inversion of the second solution.
P=D+C+A+B Q=D.C.B.A
via DeMorgan Q=P
P=D.C.B.A
Illustration 169: K-Map for Single 0

8.2.5 K-Maps and Motor Control Part 1

The circuit opposite
shows a simple motor
controller. The case of +5v
the logic points
(f,b,g,w,x,Y,Z) +5v
w
indicates if they are f fwd
active high or active x
low. For example the b Logic M
lower case input f Gates Y
g
(forward) is active low, rev
when the button is
Z 0v
pressed to make the
motor go forward the
logic value is zero (0v), 0v
when the button is not Illustration 170: : Motor Control via Logic
pressed and forward is
not desired the logic value is one (+5v). The upper case output Z is active high, when Z is high
the FET connected to it passes current, when Z is low the FET conducts no current.
There are three input switches forward (f), reverse (r) and go (g). The buttons can be pressed
independently. For the motor to move g must be pressed and either f or b. Any other input
combination must result in all FETs being off so the motor cannot move.
The motor is shown as an M in a circle and is driven by four FETs. The P channel FETs
connected to w and x will pass current if their input is low (0v), the N channel FETs will pass
current when Y and Z are high. To send the motor forward x is low, Z high, w high, and Y low
thus passing current through the motor in the direction of the small arrow. To reverse the
current and send the motor backwards w is low, Y is high, x is high, and Z is low. Under no
conditions can x be low and Y high, or w low and Z high, because there will then be a direct
short from +5v to zero volts through two FETs.
Your task: create a truth table with inputs f,b,and g, and outputs w, BC
fb
Output
x, Y and Z. Draw a truth table, draw a K-map for each of the four
00 01 11 10
outputs, derive Boolean logic for each output, draw a NAND
implementation, and simulate the result. 0 1 . . 1
A
g
Hint: to ensure your work match the solutions use truth table 1 . 1 1 .
headings "Index f b g w x Y Z comments" and the K-Map format Illustration 171: : Motor K-
Map
opposite. The comments field should explain what is happening, for
example fwd, bwd, or off. There are two solutions, one with a
solution just for w, and a second solution at the end of the solutions section for all of the
outputs. If you can't do the problem reread the notes and look at the examples again, if that
fails look at the first solution.
*** Just peeking will make life easier but you wont learn as much as trying hard yourself first.
Question: why would you be reluctant to entrust this task to software in a microprocessor or a
PC?

Index f b g w comments
w BC
fb
0 0 0 0 1 all pushed, stop
1 0 0 1 1 go inactive, stop 00 01 11 10
2 0 1 0 1 legitimate forward, w off 0 1 1. 1. 1.
A
g
3 0 1 1 1 go inactive, stop 1 1. 1 1 1.
4 1 0 0 . legitimate bwd, w on.
5 1 0 1 1 go inactive, stop w=g+b+f
6 1 1 0 1 go active, no fwd or bwd w = /g . f . /b
7 1 1 1 1 go inactive, stop
b b 1
w w
f 1 >=1 f &
g g 1
AND - OR Implementation All NAND Implementation
Illustration 172: : Motor Solution Pt 1
Note that /a is an inversion of a.
Illustration 173: : Motor Solution Pt1 Simulation

8.2.6 Five Input K-Maps

Draw K-Maps for the following truth tables. Dotted rings denote an echoed mapping
thus E can be ignored when creating the Boolean term.
echoed Not echoed

Z = A.C + A.D.E + B.C.D + A.C.D + C.E
Index ABCDE Z Y X W E=0 E=1
0 00000 1 . 1 1 CD CD
1 00001 1 . 1 1 00 01 11 10 00 01 11 10
2 00010 1 . . . 00 1 1 1 . 1 1 1 .
3 00011 1 . 1 . AB 01 X 1 X . X 1 . .
4 00100 . . . 1 11 . . . 1 1 1 1 X
5 00101 . . 1 . 10 . . 1 X 1 1 1 .
6 00110 1 . 1 .
7 00111 1 . . . Y = A.B.C.D + A.B.C.D = ( A.D).B.C + ( A.D).B.C = (A ^ D).B.C
8 01000 X . X . E=0 E=1
9 01001 X . X . CD CD
10 01010 1 1 X . 00 01 11 10 00 01 11 10
11 01011 1 1 X . 00 . . . . . . . .
12 01100 . . X . AB 01 . 1 . . . 1 . .
13 01101 . . X . 11 1 . . . 1 . . .
14 01110 X . X . 10 . . . . . . . .
15 01111 . . X .
16 10000 . . X 1 X =C.D + C.D.E + C.E + D.E
17 10001 1 . X 1 E=0 E=1
18 10010 . . X . CD CD
19 10011 1 . X . 00 01 11 10 00 01 11 10
20 10100 X . X 1 00 1 . 1 . 1 1 . 1
21 10101 . . X . AB 01 X X X X X X X X
22 10110 1 . X . 11 X X X X X X X X
23 10111 1 . X . 10 X X X X X X X X
24 11000 . 1 X .
25 11001 1 1 X . W = B.D.E + B.C.D
26 11010 . . X . E=0 E=1
27 11011 1 . X . CD CD
28 11100 1 . X . 00 01 11 10 00 01 11 10
29 11101 X . X . 00 1 . . 1 1 . . .
30 11110 . . X . AB 01 . . . . . . . .
31 11111 1 . X . 11 . . . . . . . .
10 1 . . 1 1 . . .
• Z: the bigger the group of 1's the simpler the logic. If a 1 is mapped multiple times that is
good.
• Y: diagonal patterns can sometimes be simplified using XOR gates.
• X: this really should be done on an 8 cell K-Map!
• W: remember to look for mapping that wraps around the ends and corners.

8.2.7 Synchronous Logic Analysis
COUNTER ANALYSIS: the

circuit opposite purports to be a
counter. Form a truth table for
the combinational logic that
feeds the three D flipflop inputs
and from that draw a state
diagram for the counter.
Comment on the count
sequence and the nature of the
counter. Comment on any
weaknesses in the design.
See the next page for the

answers.

R=1 R=1
0 1 2 3 4
Index Key
5 6 7
0 1 3 2
4 5 7 6
Index q2q1q0 d2d1d0
0 0 0 0 0 0 1 q1q0
1 0 0 1 0 1 0 d2
00 01 11 10
2 0 1 0 0 1 1
3 0 1 1 1 0 0 0 . . 1 .
q2
4 1 0 0 1 0 0 1 1 1 1 1
5 1 0 1 1 0 1
6 1 1 0 1 1 0 q1q0
d1
7 1 1 1 1 1 1 00 01 11 10
0 . 1 . 1
d2 = q2 + q1.q0 q2
1 . . 1 1
d1 = q2.q1 + q1.q0 + q2.q1.q0
d0 = q2.q0 + q2.q0 q1q0
d0
00 01 11 10
0 1 . . 1
q2
1 . 1 1 .
Note that for analysis the K-Maps are not needed, it is easier to take the Boolean logic equation
for each flipflop input, apply the 8 possible values of q2q1q0, and write the result directly into
the truth table. Assume a cell is zero unless an AND term gives a one.
The counter is a synchronous modulo 5 counter that counts from 0 to 4 and stops at 4. An
asynchronous active high reset sets the state back to zero and any stage. States 5, 6, and 7 are a
problem as they lockup in that state. Given the operation of the reset pin this may or may not
be a problem on power up when the device could power up in one of these lock-up states.


You have been commissioned to design a dead-man pedal system for a light rail engine
carriage. The dead man pedal has two switches, one which is closed if the driver holds the
pedal down too far, and a second switch which becomes closed if the pedal is left too far up. If
the driver does not hold the pedal in the middle then the pedal is moved up by a spring to the
upper limit and causes the upper switch to close. Only if the pedal is held in the middle will
both switches be open.
A 12 volt power source is switched by these switches and is input to the logic system.
If the dead-man pedal is activated then a counter starts counting from zero and increments by
one every second. After 4 seconds the output Warn goes high to indicate a warning and this
stays on while P is still high. After 7 seconds an output brake goes low to indicate that the train
should automatically brake, while P remains high Warn stays high and brake stays low. If at
any point the dead man pedal is returned to the middle position the counter returns to zero,
brake to high and Warn to low.
Your task is to design a Moore style synchronous circuit to implement this system. You must
use HC logic and D flipflops.
A) Draw a schematic of the switches so that there is one input to the combinational logic of the
synchronous circuit, an active high input called Problem which is high if the dead man pedal is
not in the middle position. Draw the truth table for the two switches and the one output and
state which logic function you have created with this configuration.
B) Using the single input from the switches, P, as an input to the combinational logic design a
synchronous circuit using D flipflops that will implement the specification above. Use “W” for
the warning output and “b” for the braking output. Assume you have a one second square wave
available.
C) Outline any weaknesses you see in the proposal, practical design considerations, and any
ways in which the design might be simplified.
A. Solution: the switches need to be arranged as 1=switch

follows which corresponds to a logic OR gate. +12v U closed.
The resistor is required to pull Z to zero volts U L Z
when no switch is closed. With the resistor Z is Z
0 0 0
floating and could take on any logic value. L 0 1 1
Better students may draw an opto-coupler or 1 1 1
voltage divider to drop +12v to +5v. 0v 1 0 1

B. Logic Solution
The state diagram is a string of eight states counting out the 7 seconds, this requires 3 flipflops.
If P is low the state always goes to zero, if P is one the states count up to 7 and stay there if P
is high. The outputs W and b become active as per the problem description.
Dead
DeadMan
ManPedal
PedalSolution
Solution
Index Inputs Outputs
QQQ DDD
210P 210Wb Cell Q0P
0 0000 00001 Position 00 01 11 10
1 0001 00101 Map 00 0 1 3 2
2 0010 00001
QQ 01 4 5 7 6
3 0011 01001 21 11 12 13 15 14
----------------------
10 8 9 11 10
4 0100 00001
5 0101 01101
6 0110 00001 D2 Q0P D1 Q0P
7 0111 10001 00 01 11 10 00 01 11 10
---------------------- 00 . . . . 00 . . 1 .
8 1000 00011 QQ 01 . . 1 . QQ 01 . 1 . .
9 1001 10111 21 11 . 1 1 . 21 11 . 1 1 .
10 1010 00011 10 . 1 1 . 10 . . 1 .
11 1011 11011
----------------------
12 1100 00011
D0 Q0P W Q0P
13 1101 11111
00 01 11 10 00 01 11 10
14 1110 00010
15 1111 11110 00 . 1 . . 00 . . . .
QQ 01 . 1 . . QQ 01 . . . .
21 11 . 1 1 . 21 11 1 1 1 1
D2 = Q2.P + Q1.Q0.P
D1 = Q1.Q0.P + Q2.Q0.P + Q1.Q0.P 10 . 1 . . 10 1 1 1 1
D0 = Q0.P + Q2.Q1.P
W = Q2 Q0P
b = Q0 + Q2 + Q1
b
00 01 11 10
00 1 1 1 1
QQ 01 1 1 1 1
21 11 1 1 . .
10 1 1 1 1

C. Weaknesses and Improvements

• The 12 volt input will destroy the 5 volt HC logic. There must be a voltage shifter, best an
opto-coupler.
• The P input might drive the reset of the flipflops and so simplify the logic.
• In practice there would be a lot of problems with electro-magnetic interference and
unreliable power supplies.

8.2.9 Synchronous Circuit Design: Motor Control

Design a sequential logic circuit to implement a simple count sequence that will be used
to drive a three stator electric motor.
• The input A controls the count direction.
• The states are held on two D flipflops with outputs Q1 and Q0.
• The outputs are X,Y and Z.
• Q1Q0=3 gives XYZ=011, Q1Q0=2 gives XYZ=101, Q1Q0=1 gives XYZ=110,
Q1Q0=0 gives XYZ=111.
• The count sequence for Q1Q0 given A=0 is 3,2,1,3 ... and when A=1 is 3,1,2,3 …
When Q1Q0=0 the next state is 0.
Your solution should proceed as follows-

• Draw the state diagram for the system.
• Draw the next state table for a D flip flops.
• Draw the K-Map to create the combinational logic to drive D1 and D0 and so derive
minimized Boolean algebra equation for D1 and D0.
• If necessary draw K-Maps to convert Q1Q0 to X, Y and Z and so derive the Boolean
equations for creating X, Y and Z from Q1 and Q0.
• Finally comment on the advisability of the design of state Q1Q0=0.

State 00 could be a problem as once in state 00 there is no way to get out, it is a lockup state.
It is possible the circuit will power up in this state and never move out thus preventing normal
operation.

8.2.10 River Height Indicator for Third World Countries

The number and intensity of cyclones and typhoons has definitely increased in recent
years due to climate change. This means that sudden torrential rain may cause very large rises
in river levels that are a great danger to down stream communities. This project aims to
produce a cheap river level indicator that can be placed in remote areas and report river levels
to central authorities who can then alert people by national radio stations.
Your tasks are as follows-
• Briefly discuss constraints and risks you can see in this project.
• Who would you talk to before going further with this project?
• Draw an analysis mode FBD.
• List and select alternatives for each block.
• Draw your implementation FBD for your selected alternatives.
• Comment on new risks and problems you have uncovered or old ones removed.
Constraints & Risks

Good management will always identify risks and constraints, undertake work to eliminate risks
quickly, and ensure all work is within constraints. This will increase the probability that the
work is fit for purpose and will not have an expensive rework process late in the project.
Key risks and constraints might include-
• What is the available communications infrastructure? Third world and remote may mean
no mobile phone network.
• Theft is possible so how can this danger be minimized?
• Will the communications system work in heavy rain?
• How can the units be transported and installed in remote locations in an inexpensive
manner?
• Can these remote, unattended units work reliably?
• What power is available?
• Can the unit be economically serviced?
• Tropical environment; temperature, humidity, rain, and wind. Consider also plant, fungal,
and animal growth, and abuse of the system.
• Extreme flooding may damage the system.
• There are a lot more ….

Who should you talk to?

In all projects it is vital to talk to as many stakeholders as possible. You will nearly always
learn vital things from doing this activity and save a lot of pain later. In this case-
• Who is the funding body and what are their goals, rules, and constraints?
• Talk to those who will take the output and inform the radio stations of river dangers.
• Talk to local people in the communications industry to see the real state of the
communications system.
• Talk to people who have done aid projects in the area previously.
• There are more …
Analysis mode FBD This expresses what must be achieved not how to do it.
water_level_alarm
Signal heart_beat
Water level water_level Communications
conditioning
measurement. link.
& analysis
signals_to_central
power_to_all_blocks
Energy source.
Alternatives This task is usually done by experienced engineers who have a life time of
experience and reading which helps them generate novel and workable solutions.
Water Level Indicator: water turbine, camera and level post, thermisters (thermal contact with
water changes resistance), DC conductivity probes, capacitive (AC) conductivity probes, float
switches (several at key heights).
Signal conditioning: has two parts, sanitizing electrical signals (getting rid of interference) and
deciding if there is an alarm state. This depends a lot on the water level indicators used.
Most likely this will require a small microprocessor which can also drive the communications
link and drive the hear beat signal which shows the system is alive and active.
Communications link: HF radio, satellite phone, 4G phone.
Energy source: water turbine, battery, solar panel.
Alternative Selection
All the water level indicators are susceptible the tropical environment and flooding so choose a
camera set well above the river. Single images can be analyzed for river height, and then
compressed and sent as required. The camera is pointed to a post that has heights written on it.
A small microprocessor can handle the image processing and driving the communications link.
The communications link is very dependent on the local communications infrastructure. In
order the preference would be 4G phone, HF radio, then satellite phone. Any units would need
a low power mode. In this example we will use an HF radio.
The energy source is probably best as solar with a storage battery. This can be made fully
sealed which is robust and has no moving parts.
Implementation FBD
A FBD does not show everything, just the main energy, information, and materials flows.
Control and decisions are usually omitted, for example the FBD has not shown power control to
the radio and CCD camera, or deciding if to sending an image via the radio. This can be
described in the text description that should be developed for each block when using the FBD
approach.
The microprocessor software deserves to be designed at a system level. FBD can be useful
when the database and program structural requires are low which is true in this case.
HF_radio
compressed_image_data
line_of_sight heart_beat
River height
CCD camera.
post. post_image
Microprocessor
charge_management
power battery_charge
Solar cell Charge
Energy source.
controller
power_to_all_blocks
Is there a flaw?
Actually there is a bad flaw in the system which means this design is not suitable for the
intended purpose. Can you work out what it is?
• What is the best way to ensure such flaws are found early in the project?
• Why is it important to find such defects early in the project?
• Can project life cycles help uncover such flaws?
Are there solutions to this flaw? Have a think about it ...

8.2.11 FBD for Hospital Ward Automation

This application of FBDs is slightly different. In this problem you are given a solution as
a rambling verbal narrative but with many mandated ( compulsory) items of equipment. As part
of the standard "divide and conquer" design process you must form a FBD and identify risks.
The FBD should have the specific solutions demanded by the customer but keep non-mandated
blocks as generic.
The system you are to implement will control a hospital ward using web technology.
• The system is built around IBM-PCs running a Windows operating system.
• Communications is via local Ethernet and the Internet protocols.
• All sensors will be Internet nodes.
• Speed of response shall be 10ms from a reading becoming available from a sensor, to the
application program receiving it on the appropriate PC.
• Reliability shall be one crash per 10 years.
• All power supplies shall be battery backed up so if mains fails all equipment can continue
operating for 3 hours.
• All controllers (such as oxygen valves) will also be Internet nodes, controlled from a PC.
• Speed of response shall be 10ms from control data being sent by a control program, and
that data being received on the appropriate PC.
• All sensors, databases, and controllers will be accessible world wide to enable "distance
doctoring".
Draw a Functional Block Diagram of the system. Be careful to label the boxes and vectors
with meaningful names. Include mandated solutions but keep other blocks generic.
Create a risk analysis table. Experienced and successful project managers always track risks
and actively seek to eliminate those risks. Create a table where column one lists risks to the
proper operation of the system, and column two what action might be taken to eliminate that
risk.
After finishing your risk table state whether the project looks feasible, or should be abandoned.

Web Based Hospital Ward FBD

3.0
IBM-PC with ethernet card.
1.0 5.0
Application software. 3 hr battery
back up for
2.1 web_commands 5.1 PC_ PC.
2.0 power
Windows OS
+ web server. 7.2 mains
9.1 local_
ethernet 6.0 7.0
sensor 3 hr battery
_node 7.2 mains
7.1 node back up.
_power
8.0 7.0
controller 3 hr battery 7.2 mains
_node 7.1 node back up.
_power
9.0 10.0
gateway remote_doctor
9.2 www
Note : there are multiple PCs and nodes of the ethernet, and multiple remote doctors.
Comments
• Two node types? The distinction between sensor and controller nodes is probably not
warranted. Either type of node will probably have reads and writes so the term
equipment_node may be better, and replace both type of nodes on the FBD.
• Abstract? The diagram captures the clients mandatory requirements but keeps the other
items generic (eg. the web server is not defined as a specific product).
• Ward focus weak : the diagram doesn't directly show local doctors, nurses, ward equipment
and ward beds. If the diagram is to be shown to customers or clients it may be wise to add
these things in.

Web Based Hospital Ward : Risk Analysis

Experience has clearly shown that competent risk analysis and elimination is one of the
keys to project success. Risk analysis requires a whole range of skills and experience beyond
the pure technical. The task is best carried out with a team that consists old a few older and
experienced engineers, and a couple of young ones.
Risk Elimination Tasks

Windows operating system not • Consider standby and reboot architectures.
stable for 10 years. • Get Windows rewritten ( joke).
• Consider other operating systems.
NT, the web server and the local • Look at real time extensions to Windows.
ethernet may not met the 10ms • Consider other operating systems.
data exchange requirement.
Hackers break into the system via • Look at high security options in software, PCs,
the internet. physical access, gateways, and people.
• Limit remote doctoring options.
Reliability of network. • Only allow specific applications on PCs.
• Limit use of PCs.
• Use only one specific configuration on PCs.
Battery life of 3 hours inadequate • Make the time longer, thus larger batteries.
if mains disappears from more • Have backup power like diesel generators.
than 3 hours.
Battery aging lowers capacity. • Choose appropriate battery types.
• Follow a preventative maintenance program.
Legal liabilities on the • Have thorough and independent testing of the
manufacturer. product.
• Find ways to shift any blame to the operators.
Computer viruses. • As per hacker solutions.
Software and hardware reliability. • Use rigorous development methods.
EMC compliance. • Specify EMC compliance in all contracts.
• Test for EMC compliance.
Ward resources inadequate. • Check all resources such as number of power
points, heat removal ability.
Environment a problem. • Consider issues like temperature range, needs to
be slash proof, mechanical shock limits.

8.2.12 K-Maps and Motor Control Part 2
Index f b g w x Y Z comments
w BC
fb
0 0 0 0 1 1 . . all pushed, stop
1 0 0 1 1 1 . . go inactive, stop 00 01 11 10
2 0 1 0 1 . . 1 legitimate forward 0 1 1. 1. 1.
A
g
3 0 1 1 1 1 . . go inactive, stop 1 1. 1 1 1.
4 1 0 0 . 1 1 . legitimate bwd
5 1 0 1 1 1 . . go inactive, stop w=g+b+f
6 1 1 0 1 1 . . no fwd or bwd, stop w = /g . f . /b
7 1 1 1 1 1 . . go inactive, stop
x BC
fb Y BC
fb Z BC
fb
00 01 11 10 00 01 11 10 00 01 11 10
0 1 . 1. 1 0 1. . . 1 0 1. 1. . 1.
A
g A
g A
g
1 1. 1 1 1. 1 . 1. 1. . 1 . 1. 1. .
x=g+f+b Y= g.f.b Z= g.f.b

x = /g . /f . b
Illustration 174: : KMotor Solutions Part 2
Note /a is an inversion of a.
Illustration 175: : Motor Solutions Part 2 Simulation
Answer: a microprocessor or PC running software cannot be trusted to run this circuit. Any
crash or glitch may cause the wrong two FETs to turn on, form a short from 0v to +5v, and
blow the FETs.

EEET-2251 Digital Systems Design 1 : Appendix 1
9 Appendix 1
This section contains useful notes which are not part of the main lecture notes.
9.1 Number Systems

A Digital Engineer must be proficient in at least three different number systems! These
are usually decimal, binary and hexadecimal. Some computers also require octal. A clear
understanding of number systems must be attained in order to convert between and operate
these different number bases.
The Hindu-Arabic number system that we use today evolved in India sometime before the 9th
century. It had two key concepts that are common to all our number systems-
• A digits value or weighting depends which column it is in.
• The digit zero represents a nil value.
For example 5308 =8 x 1 + 0 x 10 + 3 x 100 + 5 x 1000
Each column has a WEIGHTING , from right to left these are 1, 10, 100, 1000. Note
factor of ten between each column and the fact there are 10 number symbols (0 to 9). This
leads to the Hindu-Arabic numeral system being called decimal (deci meaning 10 based). The
system is said to have BASE or RADIX ten. It is quite possible to have bases other other than
ten as we shall see.
A radix containing R possible digits (including 0) with C columns can represent the
numbers from 0 to (RC -1). For example a 3 digit decimal number can represent the numbers 0
to (103 -1) = 999.
The column weighting principle is the reason for the simple methods we have for adding,
subtracting, multiplying and dividing. Operations we consider trivial (such as 1234 x 6789)
would be a major problem using most other number systems such as Roman numerals.
The basic Hindu-Arabic system has been embellished by the addition of a DECIMAL
POINT Numbers to the right of the decimal point are fractions. The column weighting left to
right is 1/10, 1/100, 1/1000 etcetera.
A further embellishment is the use of the minus sign which indicates an "owing" or
negative value.

9.1.1 The Binary Number System

In digital electronics the number system used is tied intimately to the hardware. The
most successful logic families have two states - Off or On, Low voltage or High voltage, 0 or 1.
These naturally produce a number system based on binary (base 2). Each binary digit is
commonly called a “bit”. The bit with the lowest column weighting (on the right) is called the
Least Significant Bit - LSB. The column with the highest weighting is called the Most
Significant Bit - MSB.
Example 101100 = 0 x 1 + 0 x 2 + 1 x 4 + 1 x 8 + 0 x 16 + 1 x 32
Note the column weighting (going right to left) is 1,2,4,8,16,32 ... . The binary number
system works by exactly the same rules as the decimal system does. The only difference is that
only digits 0 and 1 are used.
9.1.2 Negative Binary Numbers

While on paper it is possible add a minus sign to a binary number this becomes rather
more difficult within a computer which can only contain 0s and 1s. This problem has lead to
various solutions.
UNSIGNED binary numbers do not represent negative binary numbers only positive ones.
A binary number with N binary digits can represent the numbers from 0 to (2N -1).
SIGN MAGNITUDE is simply adding an extra bit to indicate whether the number is
positive or negative. Unfortunately there is no simple algorithm or rule to do the addition of
a positive to a negative number. There are two representations of 0 !! For a 5 bit number
both 10000 and 00000 mean zero. Sign magnitude is seldom used because of the these
limitations.
The number range that can be represented is +(2N-1 -1) to -(2N-1 -1).
Sign Magnitude representation for +13 = 01101

and -13 = 11101
ONE'S COMPLEMENT representation of a negative number is achieved by inverting all

bits, all 1s go to 0's and visa-versa. The number range that can be represented is +(2N-1 -1)
to -(2N-1 -1). Unfortunately there are two representations of 0. For a 5 bit number both
11111 and 00000 mean zero. One's complement is seldom used for this reason.

One's complement for +13 = 01101

and -13 = 10010
TWO'S COMPLEMENT is used in nearly all computing and digital electronics. It

represents negative numbers by the following transformation-
-X = 2N - X where N = Number of bits in binary word.
This transformation is equivalent to inverting all bits then adding 1. The number
range that can be represented is +(2N-1 -1) to -(2N-1). Two's complement suffers from none
of the disadvantages that the other number systems do. There is only one version of 0 and
the subtraction procedure is simply applying 2's complement to the numbers to be made
negative then adding. 2's complement is the way nearly all microprocessors handle negative
numbers. Note that all negative numbers will have their top bit set to 1.
Two's complement for +13 = 01101

and -13 = 10011
+13 + -13 = 00000 (note 1 bit overflows top)
9.1.3 Binary Number Problems

All real systems must have a finite number of bits in their binary word. This not only
limits the number range that can be represented but may introduce new errors when arithmetic
operations occur.
OVERFLOW may occur when carry tries to extend into a column that has no hardware to
service it. Consider the following 4 bit binary adder.
Example 1101 13
+0011 + 3
(1)0000 = 0 ??? (overflow error)
SIGN ERROR may occur when adding two large numbers. The result has the wrong sign
due to the finite number of columns. The following example shows a two's complement
addition misbehaving, the carry overflows into the sign bit to cause an error.

Example 10010 -13

+ 10010 + -13
(1)00100 = +4 ??? (sign error)
RIPPLE CARRY occurs when the addition is done one bit at a time with carry "rippling"
from one bit to the next. The carry operation may propagate from the Least Significant Bit
(LSB) to the Most Significant Bit (MSB). In many machines the longest ripple carry time
limits how fast the arithmetic operations can be performed.
Several number systems have been invented to avoid this problem. They use extra
redundant bits so the carry cannot propagate more than a few bits. These systems all suffer
from NUMBER ALIASES whereby a number can have two or more binary representations.
The logic circuitry to perform arithmetic operations becomes quite complicated but such
systems have been built.
Digital circuits can be designed such that the entire arithmetic add operation occurs at one
time. The number of gates required to do this increases exponentially for the number of bits
in the digital word so this approach is only practical for a small number of bits. Several of
these instantaneous carry arithmetic blocks may be placed in series to increase the size of
the word but a ripple carry is required between blocks. This block by block ripple carry is
much faster than bit by bit ripple carry.
Ripple Carry Between Blocks for C = A + B
A B A B
4 bit adder 4 bit adder

0
Carry Out Carry in Carry Out Carry in
Within block Within block

Ripple carry
no ripple carry no ripple carry
between blocks
C C
CARRY LOOKAHEAD can help speed up the ripple carry associated with 2's complement
arithmetic. Each adder needs an additional output called "propagate carry" which is true if the
output is all ones thus a carry in would propagate to create a carry out. Given this information a
lookahead generator can determine how to set the carry in inputs to each adder. This is shown
in the following diagram-

Lookahead Carry Between Blocks for C = A + B
A B C A B C A B C
4 bit adder (MSB) 4 bit adder 4 bit adder (LSB)
Carry Propogate Carry Carry Propogate Carry Carry Propogate Carry

Out Carry in Out Carry in Out Carry in
Carry
Lookahead Carry Generator
Within each adder block there is no ripple carry. Given the carry out and propagate
carry out from each adder the lookahead generator can determine if a carry in is
required for each adder block.
The total timing cost is one ripple carry delay plus one lookahead generator delay.
The same circuit using ripple carry would take 3 ripple carry delays to settle to a
valid output.
9.1.4 Octal and Hexadecimal

Binary representation is very close to what the hardware does but can become
cumbersome with 16 and 32 bit numbers Alternative representations are-
OCTAL is a base 8 number using digits 0 to 7. An octal digit can represent three binary
bits. This reduces the digits you must write by a factor of three. DEC computers (Digital
Equipment Corporation) are based around octal numbering.
123octal = 3 x 1 + 2 x 8 + 1 x 64 = 83 decimal
HEXADECIMAL represents 4 binary bits and thus needs 16 digits, these are 0 to 9 then
A,B,C,D,E,F. Hexadecimal or just "hex" is used more commonly than octal and is almost
universally used for microprocessors.
123hex = 3 x 1 + 2 x 16 + 1 x 256 = 291 decimal

9.1.5 Converting Between Bases

A very frequent requirement is the conversion between binary, decimal and hexadecimal.
To be honest the quickest and most error free technique is to buy a calculator with decimal,
hexadecimal, binary and perhaps octal. A calculator is not always available however.
Conversion to decimal has been performed above. The original number has each of its
digits multiplied by the column weighting. -
123.31 base 7 = 1 x 49 + 2 x 7 + 3 x 1 + 3 x 1/7 + 1 x 1/49 = 66.16 decimal
Converting from decimal to other bases or conversion between other bases can be more
difficult. The method of remainders is best shown by example -
The Method of Remainders - 791.73 base 10 to base 6
6 791 791/6 = 131 with a 6 x 0.73 = 4.38 The fractional part

remainder of 5. Note of the result carries
6 131 5 6 x 0.38 = 2.28
the remainder is put down to the next line.
6 21 5 next to the quotient. 6 x 0.28 = 1.68
The integer part on
6 3 3 The remainders form 6 x 0.68 = 4.08 each line forms the
6 0 3 the answer. 6 x 0.08 = 0.48 answer.
791 = 3355 0.73 = 0.4214 ...

base 10 base 6 base 10 base 6
791.7310 3355.4214 6
As with all engineering endeavors it is best to check the result by another means - in this
case conversion back to the previous base.
HEXADECIMAL & OCTAL TO & FROM BINARY conversion is particularly easy. Each
group of 3 binary bits is one octal digit. Each group of four binary bits is one hexadecimal
digit. The example below shows how easy this is.
Hexadecimal to/from Binary Octal to/from Binary

1110 0101 0100 1100 1 110 010 101 001 100
E 5 4 C 1 6 2 5 1 4

9.1.6 Non-Column Weighted Codes

Some quite useful number codes completely lack the column weighting we have seen.
GRAY CODE has a unique property that Binary Code Gray Code
only one digit alters for each count 0: 000 000
increment. Even the overflow back to zero 1: 001 001
only alters one bit. There are always 2: 010 011
several ways of creating a gray code for a 3: 011 010
given number of bits. 4: 100 110
5: 101 111
6: 110 101
7: 111 100
Gray code is used for shaft encoders for position sensors. Consider a binary coded shaft
where the sensors are slightly misaligned. The transition from 111 to 000 should occur cleanly
but due to misalignment there might be a false intermediate state , say 111 to 100 then to 000.
This false state would send any control system wild. Gray coded position sensors have none of
this difficulty as only one bit changes at a time.

EEET-2251 Digital Systems Design 1 : References
10 References
The references here will make useful reading if you are having trouble with the notes or
want extension material.
ELECTRONIC COMPONENTS
• http://www.mikroe.com/old/books/keu/00.htm is an excellent on-line book that explains
basic electronic components.

EEET-2251 Digital Systems Design 1 : Index
11 Index
4000 Series..................................................85 GRAY CODE............................................186
A monostable...............................................83 Group IQ effect.............................................9
AC...............................................................31 Hands-on.......................................................8
Accidents and abuse..................................106 HEXADECIMAL......................................184
Activity diagrams......................................125 Hold time.....................................................80
Algorithmic State Machines........................70 How-How..................................................128
Alternating Current......................................31 Inductive coupling.....................................106
ASM............................................................70 Inductor.......................................................38
Asynchronous logic.....................................65 Intermittent faults..................................93, 98
Baselining....................................................96 Latches........................................................83
Binary..........................................................45 Level mode..................................................65
Binary search...............................................96 Life-cycle...................................................131
Boolean algebra...........................................50 Light Emitting Diodes.................................33
Boolean logic...............................................46 Logic families..............................................48
Breakdown - Build-up...............................138 Logisim........................................................77
Business case.............................................132 Mains electricity..........................................31
Capacitive coupling...................................105 Market analysis.........................................132
Capacitor.....................................................36 Matrix board................................................20
Checklists....................................................94 Metastability................................................81
Clock mode.................................................65 Momentary..................................................39
Color codes..................................................26 Moore's Law................................................42
Combinational logic....................................45 Multimeter...................................................29
Continuous improvement............................10 Observability...............................................94
Controllability.............................................94 Occupational Health and Safety..................12
Copying.........................................................8 OCTAL......................................................184
Correlation analysis.....................................99 OH&S..........................................................12
De Morgan...................................................52 Optocouplers.............................................110
Decoupling capacitors...............................109 PAL.............................................................89
Delayed Gratification....................................9 Peer review..................................................94
Diodes..........................................................33 Plagiarism......................................................8
Electro-magnetic Interference...................105 Power supply noise....................................106
Electrostatic Discharge..............................106 Power-up state.............................................78
EMC..........................................................109 Problem solving...........................................95
Evolutionary prototypes............................145 Programmable Array logic..........................89
Extended State Diagrams............................62 Programmable logic....................................89
Fault.............................................................92 Project life cycles......................................131
Fault costs..................................................139 Prototyping life-cycle................................142
Floating........................................................49 Pulse............................................................78
Flow charts................................................124 Pulse Mode..................................................65
Flux..............................................................20 Reducing input/state bits.............................70
Frequency....................................................32 Regression testing.......................................92
Garbage collectors.......................................99 Remembering................................................8
Glue logic....................................................90 Resilience....................................................10

EEET-2251 Digital Systems Design 1 : Index
Risks..................................................132, 140 Synchronous logic.......................................65

Road map...................................................132 T flipflops....................................................66
SAFETY INTERLOCKS............................99 Throw away prototypes.............................145
Schematic diagram......................................14 Tools............................................................97
Schmidt Trigger inputs................................82 Transition diagrams.....................................60
Sequential logic.....................................45, 65 Transition graphs.........................................60
Setup time....................................................80 Tristate.........................................................83
Shielding....................................................109 Validation..................................................134
Signal Polarity.............................................64 Verification................................................134
Simulate.......................................................94 VHDL..........................................................90
Spiral Lifecycle.........................................140 VI Curves....................................................30
SR flipflop...................................................65 Voltage divider............................................26
Star point earths.........................................109 Waterfall life-cycle............................134, 143
State diagrams.............................................60 Why-Why..................................................128
Step by step.................................................95 Win-win spiral...........................................141
Stored Energy............................................107 Functional Block Diagrams......................114
Switches......................................................39

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RMIT University

School Electrical & Computer Engineering

Digital Systems Design 1

Design is the ability to take a client

What will you learn?

4.3.6 Debugging Techniques....................................................101

9.1.1 The Binary Number System............................................181

Copyright © Pj Radcliffe 2018 Page 4

QUESTION: why are engineers paid

A CAREER ! In short engineering is a wonderful career if you take it seriously.

Copyright © Pj Radcliffe 2018 Page 5

LECTURE NOTE FORMAT: these notes differ from traditional overheads-

Copyright © Pj Radcliffe 2018 Page 6

1.1 Example Digital Systems

FAILSAFE CIRCUITS must always work in all circumstances.

SENSOR SYSTEMS need the inputs to be captured and

CONTROL SYSTEMS use digital logic to drive

GLUE LOGIC is digital logic that sits between a

SMALL SYSTEMS that are very reliable and

YOU CAN BUILD impressive systems if you understand

Copyright © Pj Radcliffe 2018 Page 7

1.2 Basic Educational Theory

REMEMBERING: you will find the

HANDS-ON: there is no substitute for hands on work or Performance predictor: we

COPYING: this is a quote from my first boss-

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NEVER COPY OR GET HELP? No no no … the

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CONTINUOUS IMPROVEMENT: a successful professional must live a life of continual self

RESILIENCE is your ability to (sensibly) keep on trying

guide, blame the tutor, this is stupid, I have better things

Copyright © Pj Radcliffe 2018 Page 10

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1.3 Occupational Health & Safety

All RMIT employees and contractors must:

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2.1 Components, Schematics and Wiring Diagrams

SCHEMATIC DIAGRAM: to describe a circuit you could draw a

STANDARDS: there are two circuit symbol standards in common

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DRAWING CONVENTIONS: schematic circuits have a variety of

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2.2 Construction Techniques

CLIPS AND WIRES: very

BREAD BOARDS are a matrix of holes

INTERNAL CONNECTIONS on a breadboard are

Some east-west power lines have a break in the middle

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BREADBOARD JUMPERS are wire links

• Staples can be used to cover small distances.

• Stripping wires yourself is the traditional way to make connections.

• Connection kits are cheap and save you the

Illustration 13: Breadboard Connection Kit

Illustration 14: U Jumper Kit

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Illustration 15: Matrix Board

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PRINTED CIRCUIT BOARD (PCB) is the the

SURFACE MOUNT allows the use of tiny components that

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