NUST-SEECS

PowerPc and Embedded System Design

Assignment # 4
WASEEM ANWAR 2007-NUST-BEE-306
AHMER TAJAMMUL 2007-NUST-BEE-241
WASIF ALI 2007-NUST-BEE-307
DILLSHAD KHAN 2007-NUST-BEE----
SAAD ALI 2007-NUST-BEE----

10/11/2010
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Table of Contents
Introduction .................................................................................................................................................................. 2
History ........................................................................................................................................................................... 2
Architecture .................................................................................................................................................................. 3
Different Modes of Operations ................................................................................................................................ 5
Categories ................................................................................................................................................................ 5

Books ........................................................................................................................................................................ 6

Key Characteristics ........................................................................................................................................................ 6

Why PowerPC for Embedded Systems ......................................................................................................................... 7
Real-Time Applications ................................................................................................................................................. 8
a) Game consoles ..................................................................................................................................................8
b) TV Set Top Boxes/Digital Recorder.................................................................................................................8
c) Printers/Graphics ..............................................................................................................................................9
d) Network/USB Devices .....................................................................................................................................9
e) Automotive .......................................................................................................................................................9
f) Medical Equipments .........................................................................................................................................9
g) Military and Aerospace ....................................................................................................................................9
h) Point of Sales ....................................................................................................................................................9
List of Embedded PowerPC Processors ........................................................................................................................ 9
a) Xilinx ...........................................................................................................................................................9
c) Broad Reach Engineering .......................................................................................................................... 10
d) BAE Systems ............................................................................................................................................. 10
e) Culturecom ................................................................................................................................................. 10
f) Cray ............................................................................................................................................................ 10
g) Freescale (former Motorola) ...................................................................................................................... 10
h) IBM (now from AMCC): ........................................................................................................................... 11
i) Microsoft .................................................................................................................................................... 11
j) Nintendo ..................................................................................................................................................... 11
k) P.A. Semi ................................................................................................................................................... 11
l) Rapport ....................................................................................................................................................... 11
References ................................................................................................................................................................... 12
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Introduction:
PowerPC (Performance Optimization With Enhanced RISC – Performance Computing,
sometimes abbreviated as PPC) is a RISC (reduced instruction-set computing architecture) that
was developed jointly by AIM (Apple, IBM, and Motorola alliance). The three developing
companies have made the PowerPC architecture an open standard, inviting other companies to
build on it. PowerPC, as an evolving instruction set, has since 2006 been renamed Power ISA but
lives on as a legacy trademark for some implementations of Power Architecture based
processors.

Developed at IBM, reduced instruction-set computing (RISC) is based on studies showing that
the simplest computer instructions are the ones most frequently performed. Traditionally,
processors have been designed to accommodate the more complex instructions as well. RISC
performs the more complex instructions using combinations of simple instructions. The timing
for the processor can then be based on simpler and faster operations, enabling the microprocessor
to perform more instructions for a given clock speed.

The “PC” in “PowerPC” originally stood for “Performance Computing”; despite the coincidence
of IBM’s involvement in the development of the PowerPC architecture, it is not in any way
related to the IBM PC.

History:
Originally intended for personal computers, PowerPC CPUs have since become popular
embedded and high-performance processors. PowerPC was the cornerstone of AIM's PReP and
Common Hardware Reference Platform initiatives in the 1990s and while the architecture is well
known for being used by Apple's Macintosh lines from 1994 to 2006 (before Apple's transition to
Intel), its use in video game consoles and embedded applications far exceeded Apple's use.

The original POWER microprocessor, one of the first superscalar RISC implementations, was a
high performance, multi-chip design. IBM soon realized that they would need a single-chip
microprocessor to scale their RS/6000 line from lower-end to high-end machines. Work on a
single-chip POWER microprocessor, called the RSC (RISC Single Chip) began. In early 1991
IBM realized that their design could potentially become a high-volume microprocessor used
across the industry.

IBM approached Apple with the goal of collaborating on the development of a family of single-
chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's
largest customers of desktop-class microprocessors, asked Motorola to join the discussions
because of their long relationship, their more extensive experience with manufacturing high-
volume microprocessors than IBM and to serve as a second source for the microprocessors. This
three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola.
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In 1991, the PowerPC was just one facet of a larger alliance among these three companies. On
the other side was the growing dominance of Microsoft and Windows in personal computing,
and of Intel processors. At the time, most of the personal computer industry was shipping
systems based on the Intel 80386 and 80486 chips, which had a CISC architecture, and
development of the Pentium processor was well underway. The PowerPC chip was one of
several joint ventures involving the three, in their efforts to counter the growing Microsoft-Intel
dominance of personal computing.

When the first PowerPC products reached the market, they were met with enthusiasm. In
addition to Apple, both IBM and the Motorola Computer Group offered systems built around the
processors. Microsoft released Windows NT 3.51 for the architecture, which was used in
Motorola's PowerPC servers, and Sun Microsystems offered a version of its Solaris OS. IBM
ported its AIX Unix and planned a release of OS/2. Throughout the mid-1990s, PowerPC
processors achieved benchmark test scores that matched or exceeded those of the fastest x86
CPUs.

Figure 1: A schematic showing the evolution of the different POWER, PowerPC and Power ISAs.

IBM continues to develop PowerPC microprocessor cores for use in their ASIC offerings. Many
high volume applications embed PowerPC cores.

The PowerPC specification is now handled by Power.org where IBM, Freescale, and AMCC are
members. PowerPC, Cell and POWER processors are now jointly marketed as the Power
Architecture. Power.org released a unified ISA, combining POWER and PowerPC ISAs into the
new Power ISA v.2.03 specification and a new reference platform for servers called PAPR
(Power Architecture Platform Reference).

Architecture:
PowerPC is largely based on IBM's earlier POWER architecture, and retains a high level of
compatibility with it; the architectures have remained close enough that the same programs and
operating systems will run on both if some care is taken in preparation; newer chips in the
POWER series implement the full PowerPC instruction set.

The PowerPC architecture provides an alternative to the popular processor architectures from
Intel, including the Pentium. (Microsoft builds its Windows operating system offerings to run on
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Intel processors, and this widely-sold combination is sometimes called "Wintel".) The PowerPC
was first used in IBM's RS/6000 workstation with its Unix-based operating system, AIX, and in
Apple Computer's Macintosh personal computers. Today, PowerPC chips are also used in
diverse applications including internetworking equipment, routers, telecom switches, interactive
multimedia, automotive control, and industrial robotics.

The PowerPC ISA (instruction set architecture) is divided into several Categories and every
component is defined as a part of a category. And each category resides within a certain Book.
Processors implement a set of these categories. Different classes of processors are required to
implement certain Categories, for example a server class processor use categories Server, Base,
Floating Point, 64-bit, etc. All processors implement the Base category.

Power is a RISC load/store architecture. It has multiple sets of registers:

 thirty-two 32-bit or 64-bit General Purpose Registers (GPRs) for integer operations.
 sixty-four 128-bit Vector Scalar registers (VSRs) for vector operations and floating point
operations.
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 Thirty-two 64-bit Floating Point Registers (FPRs) as part of the VSRs for floating point
operations.
 Thirty-two 128-bit Vector registers (VRs) as part of the VSRs for vector operations.

 Eight 4-bit Condition register fields (CRs) for comparison and flow control.
 Special registers:
 Counter Register (CTR)
 Link Register (LR)
 Time Base (TBU, TBL)
 Alternate Time Base (ATBU, ATBL)
 Accumulator (ACC)
 Status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding)
subset that provides for higher code density for low-end embedded applications. Most
instructions are triadic, i.e. have two source operands and one destination. Single and double
precision IEEE-754 compliant floating point operations are supported, including additional fused
multiply add (FMA) and decimal floating-point instructions. There are provisions for SIMD
operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified
caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support
for both big and little-endian addressing with separate categories for moded and per-page
endianess. Support for both 32-bit and 64-bit addressing.

a) Different modes of operation:

 User:
Restricted modes are usually referred to as user modes. In this mode, only permitted instructions
are executed.

 Super-visor :
Supervisor mode is “An execution mode on some processors which enables execution of all
instructions, including privileged instructions. It may also give access to a different address
space, to memory management hardware and to other peripherals. This is the mode in which the
operating system usually runs.”

 Hyper-visor:
Hypervisor mode allows for a secure mode of operation that is required for various system
functions where logical partition integrity and security are required. The Hypervisor validates
that the partition has ownership of the resources it is attempting to access, such as processor,
memory, and I/O, then completes the function. This mechanism allows for complete isolation of
partition resources.
b) Categories:

 Base – Most of Book I and Book II

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 Server – Book III-S

 Embedded – Book III-E
 Misc – Floating Point, Vector, Signal Processing, Cache Locking, Decimal Floating-point, etc.

c) Books:

The Power Architecture specification is divided into five parts, called "books":

 Book I – User Instruction Set Architecture covers the base instruction set available to the
application programmer. Memory reference, flow control, Integer, floating point, numeric
acceleration, application-level programming. It includes chapters regarding auxiliary processing
units like DSPs and the AltiVec extension.
 Book II – Virtual Environment Architecture defines the storage model available to the
application programmer, including timing, synchronization, cache management, storage features,
byte ordering.
 Book III – Operating Environment Architecture includes exceptions, interrupts, memory
management, debug facilities and special control functions. It's divided into two parts.
o Book III-S – Defines the supervisor instructions used for general purpose/server
implementations. It's mainly the contents of the Book III of the former PowerPC ISA.
o Book III-E – Defines the supervisor instructions used for embedded applications. It is
derived from the former PowerPC Book E.
 Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions
and definitions from Book I-III, intended for higher instruction density and very low end
applications. They use 16-bit instructions and big endian byte ordering.

Key Characteristics:
The PowerPC is designed along RISC principles, and allows for a superscalar implementation.
Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic
POWER specification, the PowerPC added:

 Support for operation in both big-endian and little-endian modes; the PowerPC can
switch from one mode to the other at run-time (see below). This feature is not supported
in the PowerPC 970. This was the reason Virtual PC took so long to be made functional
on 970-based Macintosh computers.
 Single-precision forms of some floating point instructions, in addition to double-precision
forms
 Additional floating point instructions at the behest of Apple
 A complete 64-bit specification that is backward compatible with the 32-bit mode
 A fused multiply-add
 A paged memory management architecture which is used extensively in server and PC
systems.
 Addition of a new memory management architecture called Book-E, replacing the
conventional paged memory management architecture for embedded applications. Book-
E is application software compatible with existing PowerPC implementations, but
requires minor changes to the operating system.
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Some instructions present in the POWER instruction set were deemed too complex and were
removed in the PowerPC architecture. Some of the removed instructions could be emulated by
the operating system if necessary. The removed instructions are:

 Conditional moves
 Load and store instructions for the quad-precision floating-point data type
 String instructions.

Endian modes:

Most PowerPC chips switch endianness via a bit in the MSR (Machine State Register), with a
second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted
page table" (a hash table that functions as a TLB with off-chip storage) are always done in big-
endian mode. The processor starts in big-endian mode.

In little-endian mode, the three lowest-order bits of the effective address are exclusive-ORed
with a three bit value selected by the length of the operand. This is enough to appear fully little-
endian to normal software. An operating system will see a warped view of the world when it
accesses external chips such as video and network hardware. Fixing this warped view of the
world requires that the motherboard perform an unconditional 64-bit byte swap on all data
entering or leaving the processor. Endianness thus becomes a property of the motherboard. An
OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and
undo the exclusive-OR when accessing little-endian chips.

AltiVec operations, despite being 128-bit, are treated as if they were 64-bit. This allows for
compatibility with little-endian motherboards that were designed prior to AltiVec.

An interesting side effect of this implementation is that a program can store a 64-bit value (the
longest operand format) to memory while in one endian mode, switch modes, and read back the
same 64-bit value without seeing a change of byte order. This will not be the case if the
motherboard is switched at the same time.

Mercury Computer Systems and Matrox ran the PowerPC in little-endian mode. This was done
so that PowerPC devices serving as co-processors on PCI boards could share data structures with
host computers based on x86. Both PCI and x86 are little-endian. Solaris and Windows NT for
PowerPC also ran the processor in little-endian mode.

Some of IBM's embedded PowerPC chips use a per-page endianness bit. None of the previous
applies to them.

Why Power PC for Embedded Systems:

PowerPC is a highly integrated RISC architecture optimized for communication systems. The
PowerPC combines a PowerPC processor core with a CPM (communications processor module)
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that offloads traditional communications tasks, giving the core more cycles for the actual
processing requirements. The CPM also permits a variety of serial communication controllers
(SCCs) to be programmed with a particular personality chosen from the set available from the
core (such as Ethernet, SDLC, IDA or standard serial).

The other driving force behind PowerPC is its power consumption. For applications that require
high performance with low-power consumption, PowerPC is a great choice. Tie this altogether
with wide Linux and tool support, and you have a very capable solution.

32-bit and 64-bit PowerPC processors have been a favorite of embedded computer designers. To
keep costs low on high-volume competitive products, the CPU core is usually bundled into a
system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the
processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral
(network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM also offers an
open bus architecture (called CoreConnect) to facilitate connection of the processor core to
memory and peripherals in a SOC design. IBM and Motorola have competed along parallel
development lines in overlapping markets. A recent development is the BookE PowerPC
Specification, implemented by both IBM and Freescale Semiconductor, which defines embedded
extensions to the PowerPC programming model.

Real time Applications:

Microprocessors belonging to the PowerPC architecture family have been used in numerous
embedded systems’ applications.

a) Game consoles

All three major seventh-generation game consoles contain PowerPC-based processors. Sony's
PlayStation 3 console, released in November 2006, contains a Cell processor, including a
3.2 GHz PowerPC control processor and eight closely threaded DSP-like accelerator processors,
seven active and one spare; Microsoft's Xbox 360 console, released in 2005, includes a 3.2 GHz
custom IBM PowerPC chip with three symmetrical cores, each core SMP-capable at two threads,
and Nintendo's Wii console, also released in November 2006, contains an extension of the
PowerPC architecture found in their previous system, the GameCube.

b) TV Set Top Boxes/Digital Recorder

IBM, Sony, and Zarlink Semiconductor had released several Set Top Box (STB) reference
platforms based on IBM PowerPC 405 cores and IBM Set Top Box (STB) System-On-Chip
(SOC)

 Sony Set top box (STB).

 Motorola Set top box.
 Dreambox Set Top Box.
 TiVo (Series1) personal TV/video digital recorder (VDR).
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c) Printers/Graphics

 Global Graphics, YARC Raster Image Processing (RIP) system for professional printers.
 Hewlett-Packard, Kyocera, Konica-Minolta, Lexmark, Xerox laser and inkjet printers.

d) Network/USB Devices

 Buffalo Technology
o Kuro Box/LinkStation/TeraStation network-attached storage devices
 Cisco routers
 Culturecom - VoIP in China.
 Realm Systems
o BlackDog Plug-in USB mobile Linux Server

e) Automotive

 Ford, Daimler Benz cars and other car manufacturers.

f) Medical Equipments

 Horatio - patient simulator for training doctor and nurse.

 Matrox image processing subsystem for medical equipment: MRI, CAT, PET, USG

g) Military and Aerospace

 The RAD750 (234A510, 234A511, 244A325) radiation-hardened processors, used in

several spacecraft.
 Maxwell radiation hardened Single-board computer (SBC) for space and military
projects.
 U.S. Navy submarine sonar systems.
 Canadarm for International Space Station (ISS) created by MacDonald, Detwiller &
Associates (MDA).
 Leclerc main battle tank fire control

h) Point of Sales

 Culturecom - Tax Point of Sales terminal in China.

List of Embedded PowerPC processors:

a) Xilinx

 Virtex-II Pro and Virtex-4 FPGA have up to two embedded PowerPC 405 cores.
 Virtex-5 FXT has up to two embedded PowerPC 440 cores.
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b) AMCC

 440SP: 533-667 MHz, 10/100/1G Ethernet, (2) 64bit PCI-X, 32bit PCI-X, XOR engine, 32k L1
Cache.
 440SPe: 533-667 MHz, 10/100/1G Ethernet, (3) 64bit PCI-Express, 64bit PCI-X, XOR engine,
32k L1 Cache.
 440EPx: 333-667 MHz, (2) 10/100/1G Ethernet, Hardware Security, PCI, DDR-II, FPU, USB 1.1
or USB 2.0, 32k L1 Cache.
 440GR: 333-667 MHz, (2) 10/100 Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, 32k L1 Cache.
 440GRx: 333-667 MHz, (2) 10/100/1G Ethernet, (4) UART, (2) IIC, 53 GPIO, SPI, DDR-II,
Hardware Security, 32k L1 Cache.
 PowerPC Titan, 32-bit, dual core, 2 GHz. Announced, planned release in 2008

c) Broad Reach Engineering

 BRE440 radiation hardened CPU based on PowerPC 440 core with 256 kB L2 Cache, PCI, (2)
10/100 Ethernet, 4-CH DMA, (2) UART, extensive on chip memory control. Designed
specifically for radiation environments and extreme temperature environments (such as space).

d) BAE Systems

 RAD750 radiation hardened CPU based on PowerPC 750 core.

e) Culturecom

 V-Dragon based on PowerPC 405 core.

f) Cray

 SeaStar, SeaStar2 and SeaStar2+, PowerPC 440 based communications processors for their
Opteron based XT3, XT4 and XT5 supercomputers.

g) Freescale (former Motorola)

 MPC8xx PowerQUICC - networking & telecom card controllers with embedded communications
module, up to 80 MHz
 MPC5xx - automotive & industrial controllers
 MPC51xx/MPC52xx - e300 core, automotive & industrial system on a chip (SoC) controllers, up
to 466 MHz
 MPC55xx - e200 core, automotive & industrial controllers, up to 144 MHz
 MPC56xx - e200 core, automotive & industrial controllers, up to 264 MHz
 MPC82xx PowerQUICC II - 603e core, networking & telecom SoC controllers with high-
capacity on-chip switched bus and communications module, up to 450 MHz
 MPC83xx PowerQUICC II Pro - e300 core, networking & telecom SoC controllers with high-
capacity on-chip switched bus and communications module, up to 667 MHz
 MPC85xx PowerQUICC III - e500 core, high end networking & telecom SoC controllers with
high-capacity on-chip switched bus and communications module. D Dual core versions
supporting both symmetric and asymmetric multiprocessing, up to 1.5 GHz.
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 MPC864x - e600 core, 1 MB L2 cache, improved AltiVec (out of order instructions), an

embedded memory controller, Ethernet controllers, a RapidIO fabric interface, a PCI Express
interface, and MPX bus. Dual core versions supporting both symmetric and asymmetric
multiprocessing, up to 1.5 GHz.

h) IBM (now from AMCC):

 403: MMU added in most advanced version 403GCX

 405: MMU, Ethernet, serial, PCI, SRAM, SDRAM; NPe405 adds more network devices
 440: A range of processors based on the Book E core.
 440EP: 333-667 MHz, (2) 10/100 Ethernet, PCI, DDR, FPU, USB 1.1 or USB 2.0, 32k L1 Cache.
 440GP: 400-500 MHz, (2) 10/100 Ethernet, PCI-X, DDR, 32k L1 Cache.
 440GX: 533-800 MHz, (2) 10/100 Ethernet, (2) 10/100/1G Ethernet with TCP/IP hardware
acceleration, PCI-X, DDR, 32k L1 Cache

i) Microsoft

 Xenon (Microsoft Xbox 360) - Three core PPE based, 1 MB shared L2 cache, VMX128, 3.2 GHz

j) Nintendo

 Gekko (Nintendo GameCube) - 750CXe core with special enhancements, 485 MHz
 Broadway (Nintendo Wii) - unknown configuration

k) P.A. Semi

 PWRficient PA6T-1682M: a dual core PPC running at 2 GHz

l) Rapport

 Kilocore 1025: a CPU with a single PowerPC core and 1024 processing element (8 bit, 125 MHz)
cores (unreleased). This CPU is designed for running security and multimedia applications (with
parallel processing) on portable game devices and media players.
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References:
[1] en.wikipedia.org/wiki/PowerPC

[2] http://searchservervirtualization.techtarget.com/sDefinition/0,,sid94_gci212818,00.html

[3] http://www.learnthat.com/define/view.asp?id=1940

[4] en.wikipedia.org/wiki/PowerPC_applications

[5] PowerPCTM Microprocessor Family: The Programmer’s Reference Guide

[6] http://www.linuxjournal.com/article/4624

[7] http://en.wikipedia.org/wiki/Power_Architecture

[8] "PowerPC Architecture Book". IBM. 2003-12-10. Archived from the original on 2007-03-04.

[9] http://en.wikipedia.org/wiki/List_of_PowerPC_processors

[10] Virtex-4 family overview

[11] http://www.ibm.com/developerworks/wikis/display/virtualization/POWER5+Hypervisor

[12] http://en.wikipedia.org/wiki/Supervisor_mode

[13] http://en.wikipedia.org/wiki/CPU_modes