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Power Semiconductor Devices
for Smart Grid and Renewable
Energy Systems
By A l e x Q. H ua ng , Fellow IEEE
ABSTRACT  |  Modern civilization is related to the increased use
of electric energy for industry production, human mobility,
and comfortable living. Highly efficient and reliable power
electronic systems, which convert and process electric energy
from one form to the other, are critical for smart grid and
renewable energy systems. The power semiconductor device,
as the cornerstone technology in a power electronics system,
plays a pivotal role in determining the system efficiency, size,
and cost. Starting from the invention and commercialization
of silicon bipolar junction transistor 60 years ago, a whole
array of silicon power semiconductor devices have been
developed and commercialized. These devices enable
power electronics systems to reach ultrahigh efficiency
and high-power capacity needed for various smart grid and
renewable energy system applications such as photovoltaic
(PV), wind, energy storage, electric vehicle (EV), flexible ac
transmission system (FACTS), and high voltage dc (HVDC)
transmission. In the last two decades, newer generations of power
semiconductor devices based on wide bandgap (WBG) materials,
such as SiC and GaN, were developed and commercialized further
pushing the boundary of power semiconductor devices to higher
voltages, higher frequencies, and higher temperatures. This
paper reviews some of the major power semiconductor devices
technologies and their potential impacts and roadmaps.
KEYWORDS  | Emitter turnoff (ETO) thyristor; gallium nitride;
gate turnoff (GTO) thyristor; insulated gate bipolar transistor
(IGBT); integrated gate commutated thyristor (IGCT); power
electronics; power MOSFET; power semiconductor device;
Schottky diodes; silicon carbide; silicon-controlled rectifier
(SCR); superjunction MOSFET; thyristor; wide bandgap (WBG)
Manuscript received January 29, 2017; revised March 19, 2017; accepted
March 20, 2017.
A. Q. Huang is with the Electrical and Computer Engineering Department, North
Carolina State University, Raleigh, NC 27696-7571 USA (e-mail: pma4all@gmail.com).
Digital Object Identifier: 10.1109/JPROC.2017.2687701
0018-9219 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
I.   I N T RODUC T ION
Human civilization depends on energy for industry pro-
duction, human mobility, and comfortable living envi-
ronment. Unfortunately, there are two major energy
related grand challenges facing the mankind. On one
hand, economic and population growth will drive more
and more demand for energy which must be harvested,
processed, and delivered for the final use. According to
the Energy Information Agency [1], world energy con-
sumption is projected to increase by 48% from 2012 to
2040. Unfortunately, fossil fuels will still account for
three-fourths of this in 2040. On the other hand, global
warming and climate change is directly related to human
usage of energy that results in CO​​​2​​​ emissions into the
climate. Addressing both grand challenges requires the
accelerated development and adoption of renewable
energy technologies.
Today, clean renewable energy is the world’s fastest
growing energy source, growing at a rate of 2.6% per year,
but its overall percentage in the energy mix is still low.
In addition to needing more renewable energy, increas-
ing energy efficiency in every aspect of power consump-
tion, power delivery, and power conversion is extremely
important. Among all forms of energy carriers, electricity
is the preferred one due to its advantage in long distance
delivery and management. The push toward renewable
solar and wind energy integration, zero emission electric
vehicle, proliferation of mobile devices, and cloud com-
puting will drive up the demand for more electric energy.
In the United States, electricity accounts for 40% of pri-
mary energy consumption [2], and it will reach more than
50% of the total energy by the middle of 21st century [1].
Many of these electricity producing mechanisms have to
go through power electronic converters before they can
be used. Therefore, power electronics plays a critical role
in the efficient conversion, control, and conditioning of
Proceedings of the IEEE   1
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 1. Key power semiconductor development events in the last six decades. Red color represents commercialization events.
electric energy from the source to the load. Today, power
converters are designed to cover a wide range of power levels
from gigawatt level in high-voltage direct current (HVDC)
power transmission system to a few watts needed to oper-
ate a mobile phone. Since electricity is processed multiple
times by power electronics converters before the end use,
it is extremely important to achieve high energy conversion
efficiency in power electronics converters.
The efficiency advancement can be related to the reduc-
tion in the conduction and switching losses in power semi-
conductor devices. Over the last several decades, the power
conversion efficiency has been steadily increased through
the advancement of several generations of power semicon-
ductor device technology. Efficiency approaching 99% is
widely achieved in PV inverters and large industry motor
drives. Moving the efficiency from 99% to 99.5%, a seem-
ingly very small step, will require the reduction of the losses
by 50%. So future development focusing on power density,
reliability, and cost reduction are also being considered as
other major drivers for power electronics technology. The
need to cover a large range of power levels also necessitates
the development of power devices from a few volts to more
than ten thousand volts and from a few hundred milliam-
peres to several thousand amperes. In addition to the power
level, the switching frequency of these power devices also
ranges from sixty hertz to more than one megahertz, driven
by the system requirement as well as the need to improve
the power density. To meet these demands, power devices
based on various current conduction mechanisms have been
invented and manufactured in the last six decades. The main
driver behind these innovations is to obtain power devices
that can conduct more current for a given chip area and
breakdown voltage. This requires the improvement of the
conductivity of the device when it is in the on-state or con-
ducting state. Improving the controllability of these devices
from on-state to off-state and vice versa is another major
driver behind many of the device innovations.
A historical view of the modern power semiconductor
development is shown in Fig. 1. It started with the invention
2  Proceedings of the IEEE
of the first point contact transistor at Bell Lab on Germanium
material in 1948 [3]. Practical silicon bipolar junction tran-
sistor (BJT) and silicon-controlled rectifier (SCR), or thyris-
tor, were commercialized in 1958. This can be considered
the starting point of modern solid state power electronics
due to the practical power rating achieved by the SCR at
that time. Controlled three terminal switches like BJT and
the gate turnoff (GTO) thyristor [17] were introduced in the
1960s and 1970s for power supply and motor drive applica-
tions. In the 1980s, BJT was displaced by the power metal–
oxide–semiconductor field-effect transistor (MOSFET) [5]
which has better static and dynamic performance as well
as a simple metal–oxide–semiconductor (MOS) gate con-
trol interface. The second most important invention in the
1980s was the invention and development of the insulated
gate bipolar transistor (IGBT) [6] which capitalized on the
power MOSFET fabrication process but relied on a very
different device physics in which both electrons and holes
contribute to the current conduction. IGBT has since pretty
much replaced the GTO in most high-power applications.
Another major innovation was the invention and devel-
opment of superjunction MOSFET in mid-1990s which
reduced the conduction loss of the power MOSFET beyond
the so-called “silicon limit” [8]. High-power GTOs received
a much needed lift in the late 1990s by the hard-riven GTO
technology in the form of the integrated gate commutated
thyristor (IGCT) and emitter turnoff (ETO) thyristor which
made them viable solutions in ultrahigh-power converters
[17], [23], [85]. The next wave of major innovations were
the commercial introduction of Schottky barrier diode
[9], the power MOSFET [16] based on SiC material, and
the heterojunction field effect transistor (HFET) based on
GaN/AlGaN heterojunction material [21]–[22]. This paper
intends to provide a comprehensive and comparative dis-
cussion of these important power device technologies that
are critical for industrial, smart grid, and renewable energy
applications.
According to IHS Markit [24], the overall power semi-
conductor market including power management integrated
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 2. (a) Progress in wafer technology that supports today's power semiconductor manufacturing [25]. (b) A 150-mm Si IGBT wafer with a
thickness of only 70 ​μ​m [26].
circuits (ICs) reached $34 billion in 2015. To meet these
increasing demands, power semiconductor devices are and
should be manufactured on large semiconductor wafers in
order to improve the productivity. These devices are then
packaged in different power packages including power
modules for final system applications. The earliest semicon-
ductor material, germanium (Ge), had a narrow bandgap
(bandgap​=​0.66 eV). This was soon replaced by a wider band-
gap material silicon (Si, bandgap​=​1.1 eV) in the 1960s. The
following five decades saw significant advancements in Si
very large scale integration (VLSI) technology in which the
wafer size increased steadily while the feature size of transis-
tor decreased. Today, 300-mm diameter Si wafer is widely
used in VLSI microprocessor and memory chip manufactur-
ing as shown in Fig. 2(a) [25], and 450-mm wafer is expected
to be in production by 2019. Feature size has been reduced
from tens of micrometers to today’s 20 nm. The development
of Si material growth technology, fabrication process, and
associated equipment also enabled the dominance of Si-based
power devices since the 1960s. Today, mainstream Si power
semiconductor devices are fabricated on 200-mm diameter
Si wafers while some are now fabricated on 300-mm wafers.
Clearly, there is a delay in power device’s adoption of larger
wafer size due to the need to keep power device cost low.
Another reason behind this delay in adoption is that power
devices are less feature size dependent since device operation
depends on a very complex carrier physics that is not follow-
ing the scaling law (Moore’s law) in the digital VLSI. As a
comparison, the most advanced SiC power devices are now
commercially fabricated on 150-mm diameter SiC wafers.
Another compound semiconductor material, GaN, grown on
Si substrate, is currently being used to manufacture advanced
GaN power devices. Since the substrate is based on Si mate-
rial, the commercial production of GaN power devices is
already using 200-mm diameter wafers. Prior to SiC and GaN,
another compound semiconductor material, GaAs, has also
been researched widely for power device and RF applications.
GaAs RF devices are widely produced now, but there has
been no major commercial success in switching power device
applications. To summarize, the increased wafer size is criti-
cal to enhance the manufacturability of power devices since
many devices can then be fabricated simultaneously. Fig. 2(b)
also shows an advanced 150-mm 600-V IGBT wafer with a
thickness of 70 ​μ​m [26]. As can be seen in this picture, many
IGBT chips are populated on the 150-mm (diameter) wafer.
Reducing the wafer thickness to such a thin level is needed
to enhance the IGBT performance, while this is not required
for VLSI chip.
II.  STAT E- OF-T H E-A RT P OW ER
SE M ICON DUC T OR S: A COM PA R ISON
A modern power semiconductor device is defined as a power
switch that operates between on-state and off-state at a high
switching frequency. An ideal switch has zero on-state and
off-state power losses, and can switch at any frequency.
Practical devices do have losses, mostly during the on-state
and during the switching transitions. To achieve the con-
trolled on and off transitions, three terminal switches
are needed where the third terminal controls the on/off
transition by applying either a voltage or a current signal.
Examples of current controlled devices are BJT, thyristor,
and GTO thyristor, and example voltage controlled switches
are the MOSFET and IGBT. The insulating gate in the
MOSFET and IGBT substantially reduces the driving power
needed during the switching and is therefore preferred from
a user point of view. Two terminal switches with unidirec-
tional current flow capability such as a diode are also needed
in modern power electronics converters. A combination of
a three-terminal switch together with an antiparallel diode
creates a functional device with bidirectional current con-
duction capability and unidirectional voltage blocking capa-
bility. This configuration is needed in almost all voltage
source converters such as those used in PV, wind inverters,
Proceedings of the IEEE   3
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
and EV motor drives. Advanced devices, such as the reverse
conducting IGBTs (RC-IGBT), have an internally integrated
diode; therefore, no external antiparallel diode is needed.
A series connection of a three-terminal switch and a diode
allows voltage to be blocked in both directions, and this is
frequently used in current source converters. Advanced
devices, such as the reverse blocking IGBTs (RB-IGBT),
can block the voltage in both directions hence the external
series connected diode is not needed.
Generally speaking, the most important specifications
for any power device are its voltage and current ratings.
Switching speed is another major specification that can
be used to compare device capability. Devices with vari-
ous voltage ratings (breakdown voltage) are developed for
applications with varying voltage levels. For critical industry
and renewable energy applications, such as PV, wind, EV
and industry motor drives, power devices with breakdown
voltage higher than 600 V are typically required. For power
supplies applications used in computers, mobile computing
devices, and data centers, power devices with a voltage rat-
ing from 20 to 600 V are typically used. Different devices
are only comparable when they are designed for the same
breakdown voltage since the performance depends strongly
on the voltage rating of the device.
A. Voltage Rating
Modern power semiconductor devices are constructed
on the substrate crystal wafer vertically using several P​ ​-type
and ​N​-type semiconductor layers. Main electrical termi-
nals are at the two sides of the chip. The switch function
can be achieved by changing the conductivity of the device
from high in on-state to low in off-state. In the off-state,
the device’s conductivity is very low since all conducting
Fig. 3. The pentagon diagram showing the critical material properties important to power semiconductor devices. A larger pentagon is
preferred [40].
4  Proceedings of the IEEE
carriers are blocked by a barrier from conducting. The
device supports the high voltage within a depletion region
exhibiting very low conductivity. High electric field will be
generated in the depletion region as well as the associated
surface and edge areas during the off-state. The voltage rat-
ing is typically defined as the breakdown voltage which is
reached when the maximum electric field reaches a critical
breakdown field ​​E​c​​​.
​​E​c​​​is determined by the semiconductor material in ques-
tion. Electrically, a large off-state leakage current will be
observed if the breakdown is reached. The operation voltage
is typically selected much lower than the breakdown volt-
age, and this derating is based on the need to tolerate tran-
sient overvoltage spikes as well as the long term reliability
of the converter.
For Si material, the critical field ​​E​c​​​ is about 20V/​μ​m
while for wider bandgap material, such as SiC and GaN, ​​E​c​​​
is close to 300V/​μ​m. This is graphically illustrated in Fig. 3
for the three mentioned materials. A chief advantage of
using a wider bandgap power devices such as SiC and GaN is
their higher E ​​ ​c​​​as well as other preferred material properties
such as higher thermal conductivity. From the device design
point of view, allowing the electric field to be distributed
over a larger distance is the most frequently used method
to achieve a specific breakdown voltage for a given material
since the integration of the electric field is the applied volt-
age. In order to reduce the surface electric field to be below​​
E​c​​​, a technology called junction termination [27]–[35] has
to be used in power devices which aims at extending the
electric field supporting area at the edge of the device to be
even larger than that in the inner region of the device. A sili-
con thyristor with a breakdown voltage of 8000 V requires
a surface depletion region of more than 1.3 mm in order
to keep the surface peak electric field below 10V/​μ​m [36].
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

As a comparison, the same breakdown can be achieved in

SiC material with an inner depletion thickness of less than
70 ​μ​m and a surface termination region of around 200 ​μ​m.
It is, therefore, a much easier task for SiC power devices
to achieve extremely high breakdown voltage. 27-kV SiC
IGBT [37] and 22-kV SiC GTO/ETO [20] have been reported
in the literature. These blocking voltages are far higher than
the 13-kV Si power devices ever reported [38]–[39].

B. Current Rating
The current rating is selected so that when the device
conducts current in the on-state, the generated heat is rea-
sonable and does not cause the device to exceed its maxi-
mum operation temperature. The motivation of device
innovation is to increase the current density for a given
breakdown voltage. For devices exhibiting an ohmic on-
Fig. 4. State-of-the-art commercial Si power devices in terms of
state voltage–current relationship such as the MOSFET, the the upper boundary of the voltage and current ratings achieved in a
current density of the device is expressed in single-packaged device. The current rating shown is the dc rating at
__________

√ ​T​j,max​​  − ​T​case​​ a case temperature of 85 C.

J  = ​ __________
​ ​  ​R​ ​​  ∗ ​R​  
 ​ ​​​​  
  (1a)
jc−sp on−sp

while for devices exhibiting nonlinear I-V characteristics manufacturing and packaging technology. Fig. 4 clearly
such as a diode, thyristor or IGBT, it is expressed in shows that the Si thyristor and Si diode have achieved
​T​j,max​​  − ​T​case​​ the highest voltage and current ratings due to the excel-
J  = ​ _________
​ ​R​ ​​  ∗ ​V​ ​​
 ​ ​ 
  (1b)
jc−sp F lent bipolar conduction mechanism in these two devices.
Here, ​​Rjc−sp
​ ​​​is the specific thermal resistance from junction These two devices are also manufactured in a single wafer
to case, expressed in ​​​ ​​°​  C  ∗​cm2/W, and ​​R​on−sp​​​ is the specific using a bevel edge termination technology [34]–[36] and
on-resistance, expressed in ohm-cm . Both quantities are
2 packaged in a so-called press-pak package, as shown in
not related to the chip area. ​​T​j,max​​​is the maximum junction Fig. 6. Connected in series, high-power Si thyristors are
temperature of the device and T​ ​​ case​​​is the case temperature the key device enabling ultrahigh-voltage high-power
of the packaged device. In (1b), ​​V​F​​​ is the on-state forward HVDC power stations, and the largest one has a power
voltage drop of the device expressed in Volts. From (1a), it handling capability of 8 GW operating at ±800 kV [41].
is clear that a 100 times reduction in the ​​R​on−sp​​​ could result
in tenfold improvement in the current density of the device.
On the other hand, a reduction in the forward voltage drop​​
V​F​​​will directly result in an increase of the current density
according to (1b). Higher current density ​J​results in smaller
chip area, and hence, lower cost since ​I  = ​ J​​  ∗​ ​A​chip​​​. Many
device innovations that will be discussed below are related
to leapfrog reduction in ​​R​on−sp​​​ or V ​​ F​ ​​​. For a given generation
of technology (​J​ is fixed), increasing the chip area ​​A​chip​​​ or
parallel many devices in a module is needed in order to scale
the current rating into thousands of amperes. Taking into
account the manufacturing yield, the maximum chip size is
typically less than 1 cm2.
One way to compare the state-of-the-art power device,
especially their commercial readiness, is to compare
their absolute voltage and current ratings. This is shown
in Fig. 4 for commercially available Si power devices and
Fig. 5 for SiC and GaN power devices. Since the current Fig. 5. State-of-the-art commercial WBG power devices in terms of
rating is determined by the underline device technology the upper boundary of the voltage and current ratings achieved in a
[as suggested by (1a) or (1b)] as well as the total pack- single-packaged device. The current rating shown is the dc rating at
aged chip area, it also represents the state of the art in a case temperature of 25 C.

Proceedings of the IEEE   5

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

Fig. 6. (a) ABB 150-mm/8.5-kV thyristor wafer and its press-pak packaging. (b) Infineon wire bond type IGBT module. (c) ABB press pak IGBT.

For three-terminal devices that have controlled turnon R​on−sp​​​of a vertical, unipolar power devices’ resistance as
and turnoff, the IGBT, GTO, IGCT, as well as ETO have expressed in [48]
also achieved excellent power handling capability suit- 2
4B ​V​​   ​ .​​ 
​​R​on−sp​​  = ​ _____ (2)
able for ultrahigh-power applications. The IGBT is typi- 3
με ​E​  c​  ​
cally packaged in a multichip module as shown in Fig. 6
although there is an increasing interest in press-pak IGBT The denominator of this equation is only determined by the
[42]–[45] due to the improved reliability in critical appli- material properties of the semiconductor. It clearly shows
cations such as VSC-based HVDC power stations [43]. that a large critical electric field ​​E​c​​​will result in lower ​​R​on−sp​​​.
Voltage source converter (VSC)-based HVDC, which This is the major reason in developing unipolar devices on
typically uses IGBT as the switching device, has reached SiC and GaN since there is more than one thousand times
a power rating of 3 GW operating at ±500 kV [41]. reduction potential for the SiC or GaN unipolar power
Although only introduced to the market in the last dec- devices due to the ten times increase in the critical elec-
ade, SiC and GaN power devices have also made significant tric field. Commercial and reported SiC and GaN devices
progress in terms of commercially available voltage and cur- shown in Fig. 7 have yet to reach this full potential due to
rent ratings as shown in Fig. 5. Clearly, there is still a big the limitation in device structure [which is mostly 2-D or
gap in matching Si power devices’ current ratings shown in 3-D, instead of the 1-D assumption in (2)], design, chan-
Fig. 4. To fill this gap, hybrid devices formed by Si IGBT nel mobility, and other resistances that are not taken into
and SiC diode are being offered [46]–[47] as shown in Fig. 5 account in (2). The channel mobility in SiC, for example, is
for device at 1700- and 1200-V levels. High-power WBG
devices above 1700 V have yet to be introduced to the mar-
ket although some low current devices are already avail-
able at very high voltages. Compared with SiC, GaN power
devices are only available at relatively low voltage (<650 V)
and current levels (<100 A).
Another way to compare the devices is to compare the
underlying device technology which can be represented
by the specific on-resistance ​​Ron−sp ​ ​​​value at a given break-
down voltage. Since R​ ​​ on−sp​​​is independent of the chip area,
it represents the intrinsic device capability or the figure-of-
merit (FOM) from the conduction loss point of view. Fig. 7
summarizes many commercial and reported power devices​​
R​on−sp​​​as a function of the breakdown voltage. For bipolar
devices such as IGBT and GTO, its current–voltage relation-
ship during the on-state exhibits a nonlinear relationship,
so the differential on-resistance is plotted. Several theoreti-
cal lines are also plotted to indicate the theoretical ​​R​on−sp​​​
values for the corresponding devices. For example, the Si Fig. 7. Specific on-resistance ​​R​on�sp​​​versus breakdown voltage
1-D, SiC 1-D, and GaN 1-D limits represent the theoretical​​ achieved by modern power devices.

6  Proceedings of the IEEE

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
still much lower than Si; thus, (2) is less accurate in predict-
ing the actual device’s ​​R​on−sp​​​.
The on-resistance of Si superjunction (SJ) MOSFET [8]
also does not follow (2). For the SJ MOSFET, the theoretical
limit is expressed as
B ​V​​  ∗​ ​Cp​ ​​
​​R​on−sp​​  = ​ ______
2 ​​  (3)
2με ​E​  c​  ​
where ​​C​p​​​ is the cell pitch of the SJ device cell (discussed in
detail later). The SJ MOSFET resistance is linearly depend-
ent on the breakdown voltage instead of ​B ​V​2​​​ for a conven-
tional device. Smaller cell pitch ​​C​p​​​ will also help to lower​​
R​on−sp​​​. Therefore, SJ MOSFET resistance can be much
lower than the Si limit given in (2). Several generations of
SJ MOSFET have been commercially introduced, and the
data shown in Fig. 7 clearly show the amazing achievement
in commercial SJ MOSFET in breaking the Si 1-D limit.
Currently, the SJ MSOFETs are produced in the range of
500–900 V where they have the advantages of being low loss
(low ​​Ron ​ ​​​) and fast in speed.
The bipolar Si IGBT also does not follow the Si 1-D limit
because two carriers conduct the current which results in
much higher conductivity, and hence, lower R​ ​​ on−sp​​​. For Si
IGBT, a theoretical prediction of the forward drop/on-resist-
ance is conducted in [49] based on the assumption of an
“ideal carrier profile.” It shows that even if comparing the
Si IGBT with the new SiC MOSFET, the IGBT is still supe-
rior in the voltage range above 1.5 kV from the conduction
point of view. Today’s commercial IGBTs have not reached
the full performance potentials predicted by this and is the
motivation behind many IGBT device innovations discussed
in Section III. SiC IGBT, GTO, and PIN diode, due to the
strong conductivity modulation, have clearly surpassed even
the SiC 1-D limit by an order of magnitude in terms of the
differential resistance. At least another order of magnitude
reduction is possible with improved carrier profile and life-
time enhancement in these devices.
C. Switching Frequency
Modern power converters require the power device to
switch at high frequencies. Benefits of switching at higher
frequencies include improved dynamic response capability
and reduced passive component size and weight. Reducing
passive component size is critical for high density power
electronics. Therefore, the switching frequency is another
important parameter that can be used to compare power
devices. The upper limit of the switching frequency is lim-
ited by the device’s switching losses during turnon and
turnoff. Hence, the switching frequency is not a theoretical
limit of how fast the device can switch but a compromise
between the conduction and switching loss. Sound design
requires these two losses to be about the same, each equaling
to about half of the allowed maximum power dissipation. In
soft-switching converters, the switching loss is reduced to
almost zero, therefore the upper limit of the switching fre-
quency is determined by other considerations, such as the
magnetic components performance at high frequency.
Generally speaking, unipolar power devices can switch
at much higher frequencies since the switching losses are
only related to the charge and discharge of the parasitic
capacitance. For bipolar devices, however, it is related
to the build-up and removal of the stored excess carriers.
As more stored carriers are needed in high-voltage bipo-
lar devices, they are also much slower than low-voltage
devices; hence, they will have to switch at a lower fre-
quency. Fig. 8 shows the switching frequency versus the
converter power handling capability surveyed for many
state-of-the-art power electronics systems. Very high-power
thyristor-based converters, such as those used in HVDC,
require the device to switch at the line frequency (50 or 60
Hz) since it does not have the gate controlled turnoff capa-
bility. Silicon thyristors are manufactured as bidirectional
voltage blocking devices, so voltage reversing in an ac circuit
is used to achieve the turnoff (this is also known as line com-
mutation). For this reason, the gate controlled turnoff is also
called forced commutation. High-power GTO/IGCT/ETO/
IGBT all have the forced commutation capability, and they
switch between 60 Hz to a few hundred hertz. In medium
power industry applications, such as PV, wind, and motor
drives, 600–1700-V IGBTs are the dominant devices of
choice and they typically switch from 10 to 20 kHz. Faster
IGBTs with lower turnoff energy loss ​​E​off​​​can be designed by
reducing the stored charge inside the device at the expense
of increased forward voltage drop V​ ​​ F​​​. Therefore, there is
typically a tradeoff between the turnoff loss ​​E​off​​​ and the ​​VF​ ​​​.
Each generation of IGBT typically has a constant ​​E​off​​  ~ ​VF​ ​​​
curve [59]–[60], but different products can be tailored to
situate along the ​​E​off​​  ~ ​VF​ ​​​tradeoff curve, as shown in Fig. 9.
Fig. 8. Switching frequency verses power level for many surveyed
power electronics systems.
Proceedings of the IEEE   7
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 9. Performance of a 1700-V seventh-generation IGBT versus sixth-generation IGBT. The forward I-V curve is shown on the left, and the ​​
E​off​​  ~ ​V​F​​​tradeoff curve is shown on the right [59].
Fig. 8 clearly shows that SiC-based power electronics
system have increased the switching frequency by about an
order of magnitude compared with the IGBT systems at the
same power level. With soft-switching technique, another
order of magnitude increase in switching frequency has
been clearly demonstrated. These SiC devices, such as SiC
MOSFET and JFET, are all unipolar devices, so they are
inherently faster than Si IGBT. Many literatures have exper-
imentally compared the switching loss advantage of SiC
MOSFETs over Si IGBTs [61]–[62] and have demonstrated
the clear advantage of as much as tenfold switching loss
reduction in hard-switching converters. Fig. 10 [61] shows
an efficiency comparison of a SiC MOSFET converter with
IGBT/SiC diode hybrid module. The efficiency is nearly
independent of the switching frequency which indicates the
switching loss is very low in the SiC converter. The upper
limit of the SiC MOSFET in terms of switching frequency
Fig. 10. Calculated converter efficiency for a 1200-V SiC MOSFET
system versus that based on IGBT/SiC diode hybrid power module [61].
8  Proceedings of the IEEE
is, therefore, significantly higher than 50 kHz. This creates
the expectation that many future WBG power electronics
system for renewable energy and clean transportation could
take advantage of this feature in achieving higher power
density.
The upper frequency limit of unipolar power devices
can be theoretically calculated since the switching loss of
a unipolar device such as the SiC MOSFET is dominated by
the gate-drain charge ​​Q​gd​​​. From the material property point
of view, a high critical electric field ​​E​c​​​will result in higher
unit area charge since ​Q~ε ​E​c​​​; hence, higher ​​Qgd ​ ​​​ per unit
area is expected in WBG devices. Therefore, the capaci-
tance in WBG power devices will actually be higher on a
per-area basis. However, due to the reduction in ​​R​on−sp​​​, the
overall chip size is significantly smaller, so the net charge/or
capacitance can be smaller. Several material figure of merits
(FOMs) have been derived by Huang [63] and are updated
in Table 1 with recent material data [40], [89]–[90] for a
number of important WBG materials with the higher FOMs
being better. The HMFOM represents the total loss reduc-
tion potential when circuit conditions, including switch-
ing frequency are fixed. HCAFOM represents the chip size
reduction potential, and HTFOM represents the thermal
performance. From Table 1, the 4H–SiC MOSFET will the-
oretically have five times lower loss than silicon MOSFET,
31 times smaller chip area, and about 50% higher junction
to case temperature rise if both are designed to operate
under similar conditions. For vertical GaN unipolar power
devices, more reductions in loss and chip size are expected,
but thermal performance in GaN vertical power devices is
much worse (higher temperature rise). A diamond vertical
power device, on the other hand, is predicted to have a 2700
times smaller chip area.
The HTFOM in Table 1 can also be used as the switch-
ing frequency FOM. It indicates that hard-switching WBG
switches will be limited in its frequency by the poor thermal
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Table 1  Figure-of-Merit Comparison of Si, SIC, GaN, and Diamond Materials
conductivity and/or small chip size. This is compared with Si
unipolar devices and not bipolar devices, such as the IGBT.
This theoretical predication also does not apply to devices
operating under the so called soft-switching condition. A
soft-switched SiC converter at 3.36 MHz has recently been
reported [56]. All data shown in Table 1 are also normal-
ized against a standard Si vertical MOSFET and, there-
fore, do not apply to lateral power devices such as lateral
GaN HFET. Commercially available WBG power devices,
as shown in Fig. 6, have not reached the ​​R​on−sp​​​ reduction
potential predicted by (2). Their chip size reductions have
also not achieved the one predicted by the HCAFOM in
Table 1. Table 2 has more data on the current state of die
size shrinking.
Another simpler way to compare real-world unipolar
power device’s switching performance can be made by using
information from the device datasheet. A comparison of four
state-of-the-art power devices, a 600-V Si MOSFET, a 650-V
SJ MOSFET, a 900-V SiC MOSFET, and a 600-V GaN HFET
are compared in Table 2. In this case, several device-level
FOMs (DFOMs), are used to judge the device performance
and their capability for high-frequency operation. The ther-
mal performance and cost are also compared. In Table 2, a
lower DFOM is better. DFOM1 defines the gate drive loop
speed, and DFOM2 is directly related to the hard-switching
loss hence can be used to judge the device capability in
hard-switching converters. DFOM3 is useful to compare the
device in soft-switching converters. Finally, DFOM4 is used
to compare the reverse recovery performance of the body
diode. Table 2 clearly shows that there is a substantial die size
reduction when technology progresses from conventional Si
MOSFET to SJ MOSFET to SiC. The SiC MOSFET is about
20 times smaller than the Si device. The size reduction in
Table 2  A Device Level Comparison Among Three Unipolar Power Transistors. Si MOSFET = IXTH30N60P, SJ MOSFET = IPD65R225C7,
SJ MOSFET = C3M0280090D, GaN HFET = GS66504B *** Estimated Die Size
GaN is less significant compared to the case of SiC because
the GaN device is a lateral power device instead of the verti-
cal one, and its ​​R​on−sp​​​reduction is less. On the other hand,
the larger die size benefits a better thermal performance.
The lateral GaN also has a clear advantage in offering even
lower capacitance/gate charge. This is the result of the lat-
eral structure. Substantial reduction in DFOM1, DFOM2,
and DFOM3 suggests the SiC and GaN power devices are
well positioned to operate at higher frequencies in hard-
switching or soft-switching converters. The more than two
orders of magnitude reduction in DFOM4 is directly related
to the almost zero reverse recovery charge in the SiC and
GaN power devices. In SiC MOSFET, the Qrr is also close
to zero due to very poor minority carrier injection in the
body PN junction diode. In the case of GaN, there is no ​P​
region in the device, and reverse recovery charge is simply
the charge needed to charge the output capacitance. Hence,
lateral GaN HFET has additional advantage in applications
where higher switching frequency is desired. However, the
lateral structure limits the GaN device breakdown voltage to
below 1200 V. It is expected that lower power system could
see a competition between SJ MOSFET, SiC MOSFET, and
GaN HFET, while, in medium to higher power system, the
competition is between IGBT and SiC MOSFET. Since most
IGBT systems are operating at relatively low frequencies,
there is a need to explore new applications that can benefit
from the SiC MOSFET’s higher switching speed.
D. Maximum Junction Temperature
From (1a) and (1b), it is also clear that there is a ben-
efit if the device can operate at higher temperatures. The
maximum operating temperature is typically limited by
Proceedings of the IEEE   9
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 11. ​​R​on​​​as a function of the temperature. (a) 900-V Si CoolMOS [64], ​α =​2.4. (b) 1200-V commercial SiC MOSFET [65], α
(c) Measured Rds-on for a prototype 15-kV SiC MOSFET from Wolfspeed [66], α
the material property since the leakage current during the
off-state increases exponentially with the increase of the
temperature. This limitation, plus other factors such as the
associated packaging technology as well as thermal cycling
determined reliability, result in a typical temperature of
125 °C in silicon power devices. Advanced Si power devices
are being developed and rated at 150 °C and 175 °C. WBG
materials can operate at much higher temperature from
the leakage current point of view since the intrinsic carrier
concentration in these materials is inversely proportional to
the exponent of the bandgap n​ ​​ i​​  ~exp( − ​E​g​​ / 2kT  )​. However,
there is another limitation on increasing the junction tem-
perature because of the temperature dependence of R​ ​​ on−sp​​​
or ​​VF​ ​​​. Devices like MOSFETs tend to have a positive tem-
perature coefficient ​α​expressed in
​​  ( ​T0​ ​​  ) ​​(__
​  ​TT​  ​​​  )​​​  ​​
α
​​R​on−sp​​  (T )   = ​
Ron−sp
​ (4a)
0
while devices like IGBT (see Fig. 9), and PN junction diode
typically have a small positive temperature coefficient β​ ​
expressed in
​​V​F​​  (T )   = ​
VF​ ​​  ( ​T0​ ​​ ) (1 + β(T − ​T​0​​  )  ). ​ 
Different device technology tends to have different tem-
perature coefficients​ α​and ​β​. For unipolar power devices
such as MOSFET,​α​ is in the range of 1.5–4. Fig. 11 shows
examples for a 900-V Si CoolMOS, 1200-V SiC MOSFET,
Fig. 12. (a) Impact of maximum junction temperature ​​T​j,max​​​on the thermal cycling capability of the IGBT [59]. (b) A critical thermal
runaway temperature calculated for a SiC Schottky barrier diode (SBD) [67].
10  Proceedings of the IEEE
​  =​ 1.54.
​  =​ 3.5.
as well as a research prototype 15-kV SiC MOSFET. Higher​​
R​on−sp​​​at high temperature is a direct result of the decreased
electron mobility since electron mobility ​​μn​  ​​  ~ ​(T  )​​  −n​​, where​
n =​ 1.5 and 2.8, respectively, for Si and SiC. Such an
increase in the on-resistance results in a diminished return
in increasing the junction temperature as suggested by (1a).
Hence, an optimal maximum junction temperature exists
and can be expressed as
α
​​T​jmax,opt​​  = ​  ____
   ​ ​T​ ​​ ​ 
α − 1 a
(5)
where ​​T​a​​​is the ambient temperature. For the three example
devices shown in Fig. 11, the optimal junction temperatures
are limited to 227 °C, 500 °C, and 120 °C, respectively.
Some devices have negative temperature coefficient or
very small positive temperature coefficient; hence, they are
more suitable for high-temperature operation provided that
the packaging technology, reliability, and leakage current are
also passing the qualification tests. Modern IGBTs exhibit a
very small positive temperature coefficient ​β​, as clearly seen
in Fig. 9. Therefore, the leakage current limitation or other
(4b) considerations, such as the device thermal cycling capabil-
ity, dominate the criteria in selecting the maximum junction
temperature. For example, the thermal cycling capability of
the IGBT module typically degrades when ​​T​j,max​​​ is higher as
clearly shown in Fig. 12(a). Improved packaging techniques
need to be introduced to obtain adequate thermal cycling
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 13. Conventional and SJ MOSFET structures. 50-​μm
​ -thick epi layer is the typically epi thickness needed for a 600-V device.
capability. Similarly, IGBT switching losses tend to increase
as a function of the temperature; therefore, the thermal
runaway, defined in
∂ ​P​ ​​
​​R​ja​​  ∗ ​ ____
loss
 ​  ≤  1​
∂ T
could present another limitation on the selection of
the maximum operation temperature of power devices.
Fig. 12(b) shows the thermal runaway temperature for a
SiC SBD under the test conduction. In this case, thermal
runaway temperature happens above 450 °C; therefore,
it is not the dominating factor. Due to the limitation in
the conduction current, leakage current, packaging reli-
ability, as well as the thermal runaway limitation, today’s
Si power devices are generally rated for 125 °C–175 °C
operation. Commercial SiC and GaN are also currently
limited to 175 °C. The pace in increasing ​​T​j,max​​​ is rela-
tively slow. When using Si driver chips to drive WBG
power devices, another limitation may be imposed by the
temperature limit of the Si driver chips. This depends on
the placement of the driver chip and its thermal coupling
with the WBG devices.
III.   R EC E N T I N NOVAT IONS I N
SI P OW ER DE V IC E S
The above discussion makes it clear that Si power devices
are still the workhorse device in power electronics appli-
cation, although they are being increasingly challenged
by WBG power devices. Additional innovations are still
expected in Si power devices to maintain or expand their
current market leadership position. Several important
innovations in Si power devices in the last decade are
reviewed in this section.
A. Silicon Superjunction MOSFET
The SJ concept for vertical power devices was introduced
in the mid-1990s [8], [68]–[69] to break the Si 1-D limit shown
in (2). The SJ MOSFET cell structure is shown in Fig. 13. A
(6)
vertical P​ ​layer or ​P​column is introduced to compensate for
the charges in the ​N​drift layer when the device is in the off-
state. This concept is very similar to a much earlier RESURF
concept [70] which has been applied to many lateral power
devices. As a result, the electric field in an SJ device has been
shaped from the triangle distribution to the blue rectangular
shape, while the ​N​drift layer doping has been increased. Both
effects lead to the decrease of the on-resistance as predicated
by (3). The concept has quickly become a commercial suc-
cess, and many generations of device have been introduced
by Infineon, ST Microelectronics, and Toshiba, for example,
among many other vendors. Today, it is the device structure
of choice for Si power MOSFETs in the range of 500–900 V,
and the SJ MOSFET market is expected to reach $2.2 billion
by 2020 [71].
The most challenging aspect of fabricating SJ MOSFET
is to form the vertical ​P​column. Two popular method exists,
and both are commercially used. Fig. 14(a) shows the multi-
epitaxial growth method used by Infineon’s CoolMOS.
This method implants the ​P​column on a thin ​N​ drift
layer. The wafer then grows another ​N​layer, and the pro-
cess is repeated until the total thickness of about 50 μ​ ​m is
obtained. In contrast, the deep trench etch and refill method
relies on a single deep trench etch in the range of 45 ​μ​m
and, then, growing a ​P​ layer to fill the trench to form the
compensation ​P​columns. There are pros and cons for each
method. The multi-epitaxial has more degrees of freedom in
controlling the ​P​layer doping which is a critical parameter
in achieving the intended static breakdown voltage. On the
Proceedings of the IEEE   11
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 14. Two popular implementation strategies of forming the ​P​compensation layer. (a) Multi-epitaxial growth used by Infineon, etc.
(b) Deep trench etch and regrowth method for forming the SJ.
other hand, this would be harder in the deep trench method
since a single regrowth is used to form the entire ​P​ column.
The imperfection interface caused by deep RIE etch could
cause additional issues in the reliability of the device. The
advantage of deep trench method is that the process is sim-
pler and has the potential to lower cost.
Due to the increased PN junction area, the minority
carrier injection in SJ MOSFET is substantially enhanced
which results in a very large stored charge when the device
is operating in the third quadrant. This creates a very poor
reverse recovery characteristic (see Table 2 for a compari-
son). For this reason, SJ MOSFET is typically not suitable
for applications where third quadrant operation is needed,
such as in a voltage source inverter. Today, due to the intro-
duction of 600-V SiC MOSFET and GaN HFET, these three
devices are competing for the power supply market where SJ
MOSFET is currently the device of choice. A comparison is
made in Table 2. SJ MOSFET cost is still the lowest at about
a quarter of the cost of a GaN HFET or SiC MOSFET.
B. Thin Wafer Field Stop IGBT (FS-IGBT)
IGBT technology was the most important concept intro-
duced almost immediately after the planar power MOSFET
was introduced [6]. The introduction of two carriers in the
current conduction allows the current density be increased
much higher than the MOSFET. Early issues related to para-
sitic thyristor latch up were very quickly suppressed through
design and process optimization, and full gate controlled
current saturation allowed the device to operate under high-
voltage short circuit condition. A short circuit safe operation
area (SCSOA) measured by the short circuit time in excess
of 10 ​μ​s has been established as a new IGBT device stand-
ard. This capability, plus large snubberless turnoff SOA
(RBSOA), allows the device ruggedness be significantly bet-
ter than other Si devices, such as GTO and BJT. Overcurrent
protection also becomes simpler. Together with a very
low forward drop due to the conductivity modulation,
12  Proceedings of the IEEE
the device’s ratings were quickly expanded from 600 to
6500 V. They have therefore quickly replaced MOSFET,
GTO and BJT in medium to high-power applications. As
clearly shown in Figs. 4 and 8, the IGBT dominates the
industry power electronics applications.
To increase the current rating further, the IGBT mod-
ule was introduced with paralleled IGBT and free wheel-
ing diode (FWD) chips (see Fig. 6). High current rating
devices of more than 3600 A [72] have been achieved by
paralleling many chips. Fig. 15 shows a tested RBSOA
and SCSOA of a 3300-V/1800-A IGBT module [73]. The
turnoff current is 5.6 times the nominal current, and the
resulting peak power reached 26.8 MW. Traditional limi-
tation in terms of dynamic avalanche is no longer limiting
the RBSOA of the IGBT. Similarly, the same module also
exhibits extremely robust SCSOA as shown in Fig. 15(b).
The power stress under this condition also reached 15 MW
for more than 10 μ​ ​s.
From the technology point of view, several generations
of IGBT technology have been introduced through three
decades of innovation and industrialization. As mentioned
before, the major driver of the innovation is to improve
the performance which is governed by the ​​E​off​​  ~ ​VF​ ​​​ trade-
off. Other factors that must also be considered include
SCSOA and RBSOA. Some vendors call the latest IGBT the
seventh-generation IGBT [59], but a much simpler classi-
fication is offered in Fig. 16(a). The earliest IGBT is based
on the planar gate structure with a double-diffusion MOS
channel (DMOS) and the so-called punchthrough vertical
PNP structure. The drift layer that supports the breakdown
voltage is epitaxially grown, and the depletion region will
reach the heavily doped P​ +​ substrate. An ​N​buffer layer is
introduced to prevent the high punchthrough leakage cur-
rent. The electric field distribution and the stored charge in
a PT-IGBT are illustrated also in Fig. 16(a). The device has
a poor E​
​​ off​​  ~ ​VF​ ​​​tradeoff because large amount of carriers
exist at the collector side which results in a large current
tail during the turnoff. Epitaxial growth is also expensive,
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 15. ABB 3.3-kV IGBT module [73]. (a) Turnoff under extreme SOA conditions. (b) Short circuit under nominal SOA conditions.
and this approach is hard to scale the breakdown voltage
higher because a much thicker layer will be needed. An
improvement was introduced in the 1990s in the nonpunch
through NPT-IGBT which no longer uses an epitaxially
grown N ​ ​drift layer. Instead, high resistivity single crystal
wafer is used. The depletion region no longer reaches the
implanted ​P​collector. The implanted collector allows the
control of minority carrier injection; hence, E​ ​​ off​​​ can be
tailored. However, the NPT has a longer drift layer which
increases ​​VF​ ​​​ again.
Major innovations to simultaneously achieve V​ ​​ F​​​ and ​​Eoff
​ ​​​
reduction is realized in the so-called trench field stop (FS)
IGBT structure. The major innovations are as follows.
• Introduction of the trench structure to increase the
channel density thereby reducing the resistance in
the channel region. Cell pitch Cp is decreased to
increase the channel density.
• The narrow trench pitch together with other IE
techniques [74]–[75] are used to increase the
stored charge near the emitter side during on-state.
Another way to understand this concept is to view
IGBT conduction as a PiN diode instead of a PNP
transistor. The PNP transistor gain should be sup-
pressed as much as possible. This results in a much
stronger conductivity modulation; hence, reduc-
ing the forward drop ​​V​F​​​. The equivalent circuit
model for a modern IGBT is more accurately repre-
sented by the PIN+MOS equivalent model shown
in Fig. 16(a), instead of the one used in literatures
which incorrectly includes a PNP transistor.
• High resistivity single crystal wafer is used to reduce
the wafer cost, and the wafer thinning technology is
developed to thin the wafer to the thickness needed
for a given breakdown voltage, such as 70 μ​ ​m for
600-V devices. This reduces ​​V​F​​​.
• A very thin lightly doped buffer and lightly doped ​P​
are all implanted at the backside of the wafer. They
form the so-called transparent collector, allowing
the stored charge near the collector side to be small,
and the majority of the current conduction is the
electron current. During the turnoff, large back side
injection (electron into the collector) is available to
reduce the current tail further. The modern IGBT
has very small tail current based on this concept, as
compared to a large one in NPT-IGBT. The overall​​
E​off​​​ is reduced.
Fig. 16(b) shows an example of the trench cell structure
of a 3.3-kV IGBT [128]. A reduction of the forward voltage
drop from 3.5 to 2.75 V is achieved when compared with the
planar structure. IGBT performance is expected to improve
continuously in the future based on the above design prin-
ciples. While there are increasing needs to develop WBG
power devices, “more silicon” or “more IGBT” remains a
very attractive and cost effective pathway to meet the needs
in industry, smart grid, and renewable energy products.
C. Reverse Conducting IGBT (RC-IGBT)
IGBTs, shown in Fig. 16(a), do not have a reverse con-
duction path; hence, an externally packaged FWD is always
needed to allow the current to conduct in the reverse direc-
tion. Design and optimization of the FWD has also seen sig-
nificantly progress in the last two decades by optimizing the
anode structure and the lifetime profile. Key design param-
eters are to reduce the reverse recover loss as well as to
improve the softness of the recovery. Recently, a new gener-
ation of IGBT with the embedded FWD has been introduced,
as shown in Fig. 17 [76]–[78]. The RC-IGBT takes advantage
of the thin wafer manufacturing technology developed for
FS-IGBT. The backside ​P​collector is interrupted to have
an ​N​ region. This allows the reverse current to flow from
the emitter to the collector. Design optimization requires
carefully placement of the inserted N​ ​regions so that the for-
ward conduction of the IGBT is not affected. For the reverse
Proceedings of the IEEE   13
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

Fig. 16. (a) Migration of IGBT device structure in the last three decades. Thin wafer trench field-stop (FS) IGBT with strong injection
enhancement (IE) effect is the dominant device structure in production. (b) IGBT cell structure used in ABB's 3.3-kV trench IGBT. IE is achieved
by placing of a number of dummy trenches next to the active ones as well as an enhancement N ​ ​layer below the P
​ ​channel region [128].

conducting diode, its freedom for optimization is limited
compared with a standalone FWD. In a RC-IGBT power
module, the whole module footprint can now be occupied
by the RC-IGBT chip. This will increase the IGBT and the
diode conduction area simultaneously; hence, higher power
modules can be realized for the same footprint. One new
opportunity in the RC-IGBT is that the MOS gate/channel
can be utilized to improve the diode reverse recovery [79].
This MOS control property has also been explored many
years ago in the MOS controlled diode [80]–[82].

14  Proceedings of the IEEE

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 17. Reverse conducting IGBT (RC-IGBT). Full chip area is utilized
for IGBT conduction in the forward direction and for the diode in
the reverse direction.
D. Reverse Blocking IGBT
Several important renewable energy converters, such
as the T-NPC three level converter [83], require the use
of an IGBT in series with a diode to block reverse voltage.
Therefore, the forward drop is the sum of the two devices.
Significant reduction of the loss can be achieved in an IGBT
with reverse blocking capability. The conventional IGBT
structure [Fig. 16(a)] inherently has a reverse blocking junc-
tion (the collector PN junction), but its blocking voltage is
typically less than 30 V. To increase the voltage, changes to
the collector junction doping concentration and the edge
termination must be made. One such RB-IGBT is shown
in Fig. 18 [84]. The ​N​buffer layer has to be removed to
increase the reverse breakdown voltage, so the IGBT opera-
tion is degraded to an NPT-IGBT. A new termination will
need to be introduced to reduce the surface/edge electric
field in the reverse direction. This is typically achieved by
a combination of planar field limiting rings and a deep ​P+​
region. The latter can be formed by deep diffusion or epi-
taxial regrowth after a deep etch.
E. Integrated Gate Commutated Thyristor (IGCT)
As clearly shown in Fig. 4, the silicon thyristor, or SCR,
has been and is still the most powerful semiconductor
switch ever produced due to the clear advantages in fab-
ricating a high-power device in a single device wafer and
the highly reliable press-pak packaging technology. In the
1960s, press-pak gate turnoff (GTO) was developed to pro-
vide forced commutation capability in applications such as
high-power motor drives. The difference in the GTO, shown
in Fig. 19, as compared with a traditional SCR (see Fig. 6), is
that more gate fingers are introduced between the cathode
Fig. 18. Reverse blocking IGBT (RB-IGBT) structure.
(emitter of the NPN transistor). This increased gate to
cathode area ratio improves the controllability of the NPN
transistor in the GTO. Megawatt GTO converters operating
with a few hundred hertz dominated the high-power mar-
ket until they were replaced by the high-power IGBTs. One
reason behind this is the poor turnoff safe operation area
(RBSOA) of the GTO. Typically, failure of the GTO is associ-
ated with the so-called dynamic avalanche limitation inside
the inherent PNP structure of the device. During inductive
turnoff, simultaneous high-voltage and high-current stress
will cause the initiation of the dynamic avalanche thereby
forcing a positive feedback in increasing the current den-
sity in a small area of the device (this is also known as cur-
rent filament) until a permanent short is developed inside
the device. GTO converter circuits had to add a capacitive​
dV / dt​snubber to the GTO device in order to reduce the peak
power stress on the device to avoid this failure. This added
snubber increased the overall system cost and overall loss.
When IGBTs with snubberless turnoff operation and large
RBSOA were demonstrated, the GTO’s market share started
to decrease.
One major innovation was introduced in the late 1990s
to reinvigorate the GTO technology. The innovation focused
on the gate drive circuit of the GTO. The traditional GTO
gate drive circuit (Fig. 19) is typically placed far away from
the device with a gate parasitic inductance in the range of
300 nH or higher. When a negative voltage bias is applied,
the negative gate current, which is the useful current to turn
off the GTO, linearly increases. The ramp rate is limited by
the voltage and the large loop inductance. When the current
reaches about a 1/3 of the anode current, the device starts
to turn off. At this moment, there is still about a 2/3 of cur-
rent in the cathode/emitter junction; therefore, the thyris-
tor operation is still in place. The ratio of the gate current
over the cathode current ​​IG​ ​​ /​IK​ ​​​is defined as the turnoff gain.
The poor RBSOA is directly related to the low turnoff gain
since thyristor regenerative current conduction mechanism
enhances the formation of the current filament. The IGCT
innovation introduced by ABB [85] reduced the loop induct-
ance to less than 3 nH. Such a dramatic reduction in the​
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

Fig. 19. GTO wafer and structure, as their traditional gate drive; 4500-V/4000-A IGCT gate drive/hardware; 4500-V/4000-A ETO gate
drive/hardware.

Lg​ results in a substantially higher ​​I​G​​​ramp rate during the
turnoff. The turnoff gain becomes unity during the turnoff.
This means the cathode current is completely reduced to
zero and the inductive load current is flowing from the
anode to the gate. This unity gain turnoff condition, also
known as hard-driven condition, forces the device to oper-
ate like a PNP transistor when the anode voltage starts to
rise. The device’s RBSOA is then significantly expanded
because a wide-base PNP transistor has less opportunity to
form current filament. IGBT’s large RBSOA is also due to
the wide-base PNP transistor. Snubberless turnoff is then
demonstrated and achieved in the IGCT. Recently, ABB has
expanded the capability of the IGCT by integrating an inte-
grated freewheeling diode into the same wafer, resulting in
a reverse conducting IGCT (RC-IGCT) [128]. The snubber-
less turnoff waveform shown in Fig. 20 demonstrates excel-
lent ruggedness of this 150-mm RC-IGCT.

Fig. 20. The 150-mm 4.5-kV RC-IGCT and its snubberless turnoff at 9.5 kA and a dc link voltage of 2800 V [128].

16  Proceedings of the IEEE

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
The ETO device [23], shown in Fig. 19, also focuses
on achieving the unity gain turnoff. An additional emit-
ter MOSFET switch is in series with the cathode (emitter
of NPN). Interruption of this emitter MOS will force the
cathode/emitter current to become zero; hence, achieving
unity-gain turnoff. Impressive 5000-A snubberless turnoff
is achieved [87]. An additional advantage of the ETO is the
lower gate drive power when compared to the IGCT because
the turnoff operation is a voltage controlled operation, simi-
lar to an IGBT. Built-in current sensing [86] can also be eas-
ily achieved in the ETO. On the other hand, the ETO is not
currently in commercial production.
I V.   R EC E N T I N NOVAT IONS I N W BG
P OW ER DE V IC E S
The most exciting development in power semiconductor
device in the last decade is the commercialization of a num-
ber of WBG power devices. This section reviews the most
promising commercial SiC and GaN power devices, as well
as research and future trends of WBG power devices.
A. SiC and GaN Diodes
There are two semiconductor mechanism that can
be used to develop a diode: one is based on the PN junc-
tion, and other one is based on the Schottky barrier diode
(SBD) junction. In the SBD, there is no conductivity mod-
ulation; hence, the theoretical on-resistance of the SBD is
determined by (1) plus the voltage needed to overcome the
Schottky barrier. Therefore, high-voltage Si SBD is very
rare because its forward voltage drop is much higher than
an equivalent Si PN junction diode where strong conduc-
tivity modulation is available and the PN junction turnon
voltage is around 0.7 V. The reverse leakage current of the
SBD also increases quickly with the increase of the tempera-
ture that makes it harder to justify a high-voltage Si SBD. Si
PN junction diodes, therefore, dominate the market from
Fig. 21. Three basic SiC diode structures (future GaN diodes will be similar).
600 V to 10 kV. Si PN junction diode, however, has a very
poor reverse recovery since large carrier is stored in the
device during the conduction. Although improved diode
performance can be incrementally achieved by optimizing
the anode injection efficiency and lifetime profile, the poor
reverse recovery performance has been a major bottleneck
for increasing the switching frequency in the power elec-
tronics converters.
In the case of the SBD on WBG material, such as the
SiC, the situation is completely reverse. The high critical
electric field ​​E​c​​​in SiC results in substantial reduction in
the resistance of an SBD. Therefore, conductivity modula-
tion is no longer needed or desirable. SBD has no charge
stored; therefore, almost zero reverse recovery loss can be
achieved. Hence, WBG diode based on Schottky mecha-
nism is almost an ideal diode. The high leakage current
can be reduced by using a higher Schottky barrier metal,
such as nickel, since the contribution from a higher bar-
rier height is still very small when the SBD is designed for
600 V or higher. To further reduce the leakage current,
the junction barrier Schottky (JBS) diode structure which
introduces a ​P​region to protect the Schottky region in
the reverse blocking state can be used. Another advantage
of the JBS diode is that the ​PN​junction can become con-
ductive at high forward bias and results in a better surge
capability than the SBD [88]. On the other hand, the SiC
PN junction diode will need to overcome a forward volt-
age drop of around 3 V across the ​PN​junction; this makes
it extremely unattractive from conduction loss point of
view even if the drift region resistance can be reduced by
the conductivity modulation. For this reason, there is cur-
rently no commercial SiC ​PN​junction diode. All commer-
cial solutions (600, 1200, and 1700 V) are all SiC SBD or
SiC JBS.
The three basic diode structures are shown in Fig. 21.
The blocking voltage of commercially available SiC SBDs is
limited to 600 V due to the increased reverse leakage cur-
rent, especially at elevated temperatures. SiC diodes above
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Fig. 22. (a) The 10-kV SiC JBS diode and PIN diode I-V curves at room temperature with the same chip size. (b) Reverse recovery current
​ 5 C) [93]. (c) Measured I-V curve of a large area 16-mm2 GaN PIN diode [139].
​ ​​ = ​7 kV for a 15-kV SiC PIN diode (​T = 2
tested at ​​VR

600 V mostly use the JBS structure. The off-state leakage
current in JBS is reduced, so devices can be rated at up to 175
°C. Because the device conduction is still via the majority
carrier electrons, the speed of the JBS is not compromised.
The JBS diode, therefore, provides excellent performance
over a wide range of voltages. A 15-kV JBS diode has also
been designed and tested for high-frequency applications
[91]. At voltages above 10 kV, there might be a need to
develop the SiC PN diode since it can effectively reduce the
drift region resistance via conductivity modulation [92]. In
Fig. 22(a), the I-V curve of a 10-kV SiC JBS diode and the I-V
curve of a 10-kV SiC PN diode with the same chip size are
compared. Although the PIN diode has a higher knee volt-
age, the differential resistance of the SiC PIN diode is much
smaller than that of the JBS diode due to the conductivity
modulation. The SiC PIN diode’s much lower leakage cur-
rent compared with JBS or SBD is another advantage that
makes it an ideal candidate for high-voltage and higher tem-
perature operation. However, the ~3-V ​PN​junction knee
voltage, which is determined by the SiC material, makes the
SiC PIN ineffective from the conduction point of view when
the blocking voltages are below 3.3 kV. SiC JBS diodes are
preferred in these voltage ranges. Because of the minority
carrier stored in the device, there is also a sizeable reverse
recovery current in the SiC PIN diode, as clearly shown in
Fig. 22(b) which results in large reverse recovery loss in
converter applications.
With the increasing availability of freestanding GaN
wafers [129], a number of R&D efforts are also underway
to develop vertical GaN PIN diode [131]–[141] as a
next-generation power rectifiers to compete with SiC-based
power rectifiers. The ​P​anode is typically formed by MOCVD
growth, although a strong interest exists in developing an
implanted anode. Compared with the ​P​implantation tech-
nique in SiC, ​P​implantation and activation remains a major
challenge in GaN due to the deep energy level of the accep-
tor, although some significant progress have been made
in this area [130]. ​P​implantation is needed to fabricate
the SBD/JBS cost effectively. Several epitaxial grown PIN
diodes and their measured FOM are shown in Table 3. Close
to ideal differential resistance R​
​​ on−sp​​​has been achieved in
these diodes. However, the P​ N​junction turnon voltage, also
around 3 V, makes these diode unattractive for commer-
cial introduction. Fig. 22(c) shows a measured forward I-V
results of a 700-V GaN PN junction diode at different tem-
peratures [139]. The high turnon voltage is clearly shown.
Future developments of GaN SBD/JBS diodes are expected
in order to compete effectively with SiC SBD/JBS diodes.
B. SiC MOSFET
Thanks to the well-established gate-driving technique
and user base in Si MOSFET and IGBT, SiC MOSFET is
the preferred SiC three terminal switch (compared with

Table 3  Reported FOM for Vertical GaN P

​  Ð N​Diodes With MOCVD Grown P
​ ​ Anode

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
SiC JFET and BJT). It has been introduced commercially
from 600 to 1700 V, including higher current modules as
shown in Fig. 8. It is expected that commercial products up
to 3.3 kV will be introduced in the near future while even
higher voltage devices are being researched [66], [91]–[92].
The 15-kV SiC MOSFETs have been prototyped and used
in developing high-voltage high-frequency solid state trans-
formers [97]–[98], [166]–[168] that take advantage of the
fast switching speed of the device even at such a voltage
level. The operation frequency of SiC MOSFET-based con-
verters has seen one or two orders of magnitude increase
as shown in Figs. 8 and 10 when compared with the IGBT
system. Under certain conditions, zero switching loss can
also be achieved in SiC MOSFET. An operation at 3.38 MHz
was recently demonstrated for a 1.2-kV SiC MOSFET mod-
ule [56]. Due to the low conduction loss in SiC MOSFET, it
can also operate in the third quadrant as a synchronous rec-
tifier by significantly reducing the third-quadrant conduc-
tion loss while offering almost zero reverse recovery loss.
The synchronous rectifier concept has been used for many
years in low-voltage Si MOSFET (<100 V), and it now can
be applied to SiC MOSFET even at voltages up to 3.3 kV.
This is because the body ​PN​junction diode in SiC will not
conduct until above 3 V; hence, the channel conduction is
the lower resistance path and should, therefore, be used.
The body PIN diode conducts only during the dead time.
Since the ​PN​junction injection efficiency with an implanted​
P​region is very poor and the minority carrier lifetime in the
SiC is generally very low unless special lifetime enhance
technique is used, the reverse recovery of the body diode in
SiC MOSFET exhibits very low reverse recovery charge and,
hence, very low loss (see Table 2 for an example).
There are two basic device structures used in commer-
cial SiC MOSFET products as shown in Fig. 23: a planar
structure and a trench structure. At higher voltages, the
reported ​​R​on−sp​​​has already reached the theoretical 1-D limit
because the resistance is well predicted by (3). At lower volt-
ages such as 1200 V, the channel resistance, the JFET resist-
ance between the two P​ ​regions, and the substrate resistance
are the three other components that cannot be ignored. This
is also one reason why 600-V SiC MOSFET is less competi-
tive at the moment because these three components are
becoming even higher percentages at 600 V. Wafer thinning
to ​<1​ 00 ​μ​m is very effective in reducing the substrate resist-
ance. Improvement of channel resistance can be achieved
by improved processing techniques that focus on improv-
ing the channel mobility. In the trench SiC MOSFET, the
cell pitch is further reduced to increase the channel density,
hence reducing the channel resistance. The JFET region is
also eliminated in the trench structure.
Due to the ten times higher electric field in SiC
MOSFET as compared with Si MOSFET, one key challenge
is to trade off the gate-oxide reliability for low specific on-
resistance. In the planar structure, the gate oxide is pro-
tected by the P​ ​ regions; hence, the peak electric field near
Fig. 23. Two typical SiC MOSFET structures: (a) planar and
(b) trench. Epi thickness is typical of a 1200-V device.
the oxide is reduced. Planar MOSFET’s gate-oxide stability
issue has been solved, and excellent reliability performance
is achieved [94]. The industry’s first reliable SiC MOSFET
with a 200 °C junction temperature was also demonstrated
by General Electric (GE) [95]–[96]. In the trench device,
this is harder. Many variations of the trench structures
exist [99]–[104] to protect the bottom of the trench gate.
Fig. 23(b) uses a deeper ​P​region so it provides some protec-
tions to the bottom of the trench gate. The first commercial
trench MOSFET was released by Rohm in 2010. A novel
double trench structure has been proposed to solve the
oxide breakdown at the bottom of the trench [105].
In addition to improving electrical performance, another
major driver for SiC MOSFET innovation is reliability.
High-temperature gate bias, high-temperature reverse bias,
and high-humidity, high-temperature reverse bias are the
three major criteria for evaluating reliability. Highly reli-
able SiC devices have been successfully demonstrated; for
instance, the reliability of the industry-leading 200 °C-rated
SiC MOSFET was reported by GE in 2014 [95]. Another
important parameter for power semiconductors is immu-
nity to cosmic rays. This is especially important in applica-
tions in aerospace and nuclear plants. This is a less explored
issue in SiC MOSFET and will become even more important
when higher voltage SiC devices are introduced.
In [106] and depicted in Fig. 24, 1200-V SiC MOSFET
and Si IGBT comparison shows a very favorable cosmic ray
immunity for the SiC MOSFETs. In [107], 1.2–3.3-kV SiC
MOSFETs with fewer than ten failures in time (FIT) were
demonstrated, as shown in Fig. 25(a). This FIT rate is simi-
lar to that of Si IGBT. The recommended derating curve is
also provided as a guideline [Fig. 25(b)]. A much higher der-
ating factor is proposed for SiC devices with higher blocking
voltages. Additional studies are needed to explain the phys-
ics behind this characteristic.
In addition to SiC MOSFET, SiC power BJT, JFET, and
SIT are also available commercially [142]–[146]. These
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

Fig. 24. Cosmic radiation related reliability of 1200-V SiC MOSFET when compared with Si IGBT [106].

devices do not have a MOS structure and are developed in
the early stage of the SiC power device development his-
tory due to the challenges in developing the SiC MOSFET
because of the low channel mobility and poor MOS reliabil-
ity. These challenges are largely resolved today due to more
than two decades of R&D. Hence, it is expected that these
devices will only be used in niche applications such as dc
circuit breaker [146]. SiC MOSFET and SiC superjunction
MOSFET (not commercially available yet) will dominate
the market place over a wide range of voltage ratings.
C.  Ultrahigh-Voltage SiC Power Devices
High-voltage SiC MOSFETs have also been reported to
replace high-voltage Si devices from 3.3 to 6.5 kV and even
higher voltages [107]–[111]. The highest blocking voltage
reported for SiC MOSFET is 15 kV [109] although it is cur-
rently not in commercial production. The high-voltage SiC
MOSFET can simplify the circuit topology for high-voltage
and high-frequency applications, such as solid-state trans-
formers [97]–[98], [166]–[168]. Although the high-voltage
SiC MOSFET shows a large reduction in switching losses
compared with the Si IGBT, the voltage drop becomes high
when the voltage levels are higher than 10 kV. Therefore,
scaling to higher current will be an issue. In this condition,
the combination of the SiC and bipolar device structure,
such as SiC IGBT, would be desirable. Several high-voltage
SiC IGBT designs have been reported [112]–[114]. The high-
est blocking voltage reported so far is a 27-kV SiC n-IGBT,
obtained by using a 230-​μ​m drift layer [118]. The design

Fig. 25. SiC MOSFET with a total active area of 7.2 cm2, room temperature, and sea level [107]. (a) Failure caused by terrestrial cosmic
radiation. (b) Voltage derating guideline for failure rate of 100.

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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 26. I-V curve comparison of 15-kV SiC ​P-​ GTO, IGBT, and MOSFET
at 25 C and 125 C.
also incorporated a lifetime enhancement process to reduce
the voltage drop. The highest blocking voltage reported for
a SiC ​P​-IGBT is 15 kV, as shown in [115]. The differential
specific on-resistance for most of the reported SiC IGBTs
is in the range of tens of m​Ω​-cm2. The SiC GTO transis-
tor has also been investigated. It achieves the best current
handling capability with a very low forward drop among all
reported high-voltage SiC power devices due to the double-
side carrier injection and strong conductivity modulation
[124]. This is clearly illustrated in Fig. 26 where the for-
ward conduction characteristics of the 15-kV ​P​-GTO, IGBT,
and MOSFET are measured and compared. All these high-
voltage devices are based on 4H-SiC material and fabricated
by Cree. To minimize the effects of different chip sizes,
the active chip areas are normalized to 0.32 cm2. The SiC
​P​-GTO shows the smallest voltage drop among all three types
of devices, followed by the SiC IGBT and SiC MOSFET. In
addition, instead of positive temperature coefficient shown
in SiC MOSFET and IGBT, the SiC GTO transistor has a slight
negative temperature coefficient of voltage drop. Based on
SiC P​ ​-GTO technology, 15- and 22-kV SiC ETOs have also
been demonstrated and utilized in circuit breaker applica-
tions [20], [126]–[127]. Fig. 27 shows the turnoff waveform
of the 15-kV SiC ​P-​ETO. It is noted that the voltage and
current are plotted in the negative region due to the ​P​-type
device. The peak power density reached 1.13 MW/cm2,
indicating a very large reverse bias safe operation area for
SiC bipolar devices. This characteristic is very important
for converter and circuit breaker applications. Currently,
none of above discussed ultrahigh-voltage SiC devices are
commercially available. Successful commercialization of
these devices with higher current ratings could have a major
impact to applications such as the HVDC MMC converter,
FACTS, dc circuit breaker, and medium-voltage drives. In
Fig. 27. Snubberless turnoff waveform of a 15-kV SiC p-ETO at 6.2 kV
and 123 A (power density ​=​1.13 MW/cm2).
HVDC MMC application, high switching frequency is not
needed; hence, SiC IGBT or GTO/ETO and PIN diode will
be the preferred devices of choice. Due to the strong con-
ductivity modulation in SiC GTO, blocking voltage as high
as 50 kV is also feasible in the future, as shown in the mod-
eling result in Fig. 28. An improvement in carrier lifetime
and packaging technology will be needed for this device to
be developed.
D. GaN Heterojunction Field-Effect Transistor
GaN is another important WBG material, and its prop-
erties, as shown in Fig. 5, are also very suitable for power
device applications. However, due to the difficulty in pro-
ducing low-cost GaN epitaxial wafer that is needed to con-
struct vertical power device, vertical power devices based
on GaN material are still in a very early research stage
[129]–[141], and no commercial vertical power devices
are currently available. Other major technical challenges
that must be overcome before vertical power device can be
readily made is the formation and activation of implanted​
P​-type layers in GaN. However, due to the success of epi-
taxial growth of GaN/AlGaN thin layers above a standard Si
substrate, a lateral GaN power transistor, the GaN hetero-
junction field-effect transistor (HFET), has been commer-
cially introduced for 600 V and lower voltage applications
[21]–[22]. This structure, shown in Fig. 29, can be produced
in many Si wafer factories. Multiple metal layers are used
to provide interconnect to the source and drain contacts.
Early GaN HFETs are depletion mode devices; a cascode
configuration with a Si MOSFET will be needed to obtain
an enhancement device [22]. Latest devices from several
vendors are enhancement devices using gate engineering
that involves a combination of recess etching, deposition
of a dielectric layer, and P​ -​ type GaN gate structure. Due
to the high critical electric field and high channel mobility
(1500 cm2/V-s versus 600 in Si inversion channel versus
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 28. Predicted device forward conduction capability of SiC p-GTO for a BV of 30�50 kV.
about 10 in the SiC inversion channel) in the GaN/AlGaN
quantum well as well as the lateral structure, the device
is particularly attractive for very high switching frequency
applications, as clearly shown in Table 2. To use the devices
at their full potential, their packaging must have both very
low parasitic inductance and high thermal performance.
New packaging approaches, such as embedding dies in
packages similar to a multilayer PCB, were developed by
GaN System as shown in Fig. 29. It is expected that 600-V
GaN HFET is a strong competitor with Si SJ MOSFET in
offline power supply applications and lower power (<5 kW)
PV inverters. Scaling GaN HFET to higher voltages is harder
due to the field crowding associated with the lateral struc-
ture, so higher voltage GaN will have to be developed based
on vertical structure. Currently, this is limited by the lack
of good epitaxial material and inability to achieve well
Fig. 29. (a) Lateral GaN HFET. (b) Advanced GaN HFET packaging from GaN System.
22  Proceedings of the IEEE
activated P​ ​doping region. The low thermal conductivity in
GaN material, as shown in Table 2, is another factor that
needs to be considered.
V.   SM A RT GR I D A N D R E N E WA BL E
E N ERGY S YST E M A PPL IC AT IONS
Power electronics systems for smart grid and renewable
energy system applications are typically grid connected
applications. For a three-phase system, the power device
breakdown voltage required are typically higher than 1200 V,
while for a single-phase system, 600-V device can be
used. For this reason, it is expected that 600-V GaN/SiC
power devices could potentially be used in single-phase
PV inverter applications as well as PV microinverters. The
driving force will be to utilize the high-frequency capability
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Table 4  Key Smart Grid and Renewable Energy System Applications and Their Future Power Device Needs (Devices Shown in Red Are Not
Currently Available Commercially)
to achieve compact and efficient solutions [147]–[149].
Another emerging application for 600-V GaN/SiC could
be the level-2 onboard charger (OBC) for electric vehicles
[150]–[156] or wireless power transformer (WPT) charger
[157]–[158]. In these cases, high-frequency soft-switching
operation enables very compact and efficient isolated bidi-
rectional charger implementation. For all other applica-
tions that are currently served by Si IGBT, the SiC power
devices are poised to compete effectively with the IGBT.
Hybrid power modules based on Si IGBT/SiC JBS diode is
also a popular option for early stage insertion of SiC power
devices. Several important existing and emerging smart grid
and renewable energy system applications are summarized
in Table 4 with the preferred future power devices. Also
summarized are perceived motivations for each application
when searching for better power device technology.
As discussed earlier, SiC MOSFETs and JBS diodes
provide superior dynamic performance compared with Si
IGBTs and PIN diodes; therefore, they can clearly improve
power efficiency and power density. However, wide-
spread adoption of SiC power conversion systems is still a
challenge. One reason is that SiC is by no means a plug-and-
play technology. Integrating SiC technology into the electri-
cal system requires a deep understanding of system design,
including EMI and thermal issues. Moreover, the relatively
higher cost of SiC devices is still a concern for end users.
The cost of SiC power device decreases with increased vol-
ume production. With larger volumes, better manufacturing
processes with larger wafers, the cost per amp of SiC devices
will continuously drop. Also the per-watt cost of the overall
system could potentially be reduced with a better balance-
of-plant system design. Fig. 30 shows the concept of system
cost saving as a major driver for insertions of SiC power
devices in existing applications. The savings may come from
developments such as smaller passive components, lower
cooling requirements, and a higher absolute power rating.
It is demonstrated in [159] that the cost of a 17-kW solar
inverter could be reduced by 20% with SiC JFETs and SiC
diodes. Additionally, the operational cost reduction gained
from efficiency improvements could justify the higher capi-
tal cost [160].
Due to their potentials to improve the power efficiency
while reducing the system cost, PV inverter could be the
first major insertion point for SiC power devices. The
required voltage ratings (1200–1700 V) are considered
pretty low for SiC material. In [161]–[162], SiC Schottky
diode–based solar micro-inverters were demonstrated with
reduced reverse recovery losses and improved efficiency.
For rooftop PV applications, a desirable weight density is
necessary, e.g., 1 kW/kg. Most commercialized products
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Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems
Fig. 30. Potential system cost benefit from SiC devices.
with Si IGBTs cannot fulfill this requirement; their weight
density is less than 0.38 kW/kg. To address this challenge,
Mookken et al. [163] present a 50-kW SiC MOSFET-based
photovoltaic string inverter with significantly increased
switching frequency and reduced weight that can achieve
the design target. High-power centralized inverters based
on SiC devices have also been developed. A 1-MW solar con-
verter system consisting of a boost converter with an all-SiC
power module and a Si-based three-level, T-type, neutral
point clamped (NPC) structure is presented in [164]. The
maximum achieved efficiency is 98.8% at 850 V, which
is the upper maximum power point range limit. The total
efficiency is about 0.5% higher than that of a traditional
Si-based single-stage inverter. Recently, GE announced a
full-SiC single-stage megawatt-level photovoltaic inverter
(Fig. 31) [165]. With an industry-leading SiC MOSFET mod-
ule, the reported California Energy Commission (CEC) effi-
ciency is close to 99% at 900-V dc input (see Fig. 31).
Higher voltage SiC power devices are expected to be
commercially available in the near future, perhaps ini-
tially at 3.3- and 4.5-kV level, in order to compete with
IGBTs in existing applications. In HVDC MMC applica-
tions, the desired voltage rating should be much higher
than 4.5 kV since the switching frequency is low [128], so
Fig. 31. GE 1-MW SiC PV inverter installed in Berlin and its efficiency curve [165].
24  Proceedings of the IEEE
the total number of MMC cells can be reduced. Therefore,
higher voltage devices based on SiC IGBT/GTO/PIN
operation should be developed in the future. This will
also have a dramatic impact on several other high-voltage
applications such as the STATCOM and HVDC circuit
breaker [125]–[127]. The switching frequency in these
applications does not need to be high due to large num-
ber of cascaded converter cells. High-voltage and high-
frequency capability is needed in applications where an
isolated topology is used, such as the emerging applica-
tion of solid-state transformers (SST) for the future smart
grid [91], [98], [166]–[168]. This is in order to reduce the
size of the medium frequency isolation transformer. GE
has developed a 1-MVA solid-state transformer based on
a 15-kV/120-A SiC MOSFET module operating at 20 kHz
[166]. Compared with a traditional transformer with the
same rating, it facilitates a 50% reduction in size and 75%
reduction in weight, while at the same time achieving
98% efficiency. Recently, a single-phase SST for 7.2-kV
distribution grid has been developed, as shown in Fig. 32
[167]–[168]. This SST, using a resonant ac/ac conversion
topology and 15-kV SiC MOSFET at 40 kHz, achieved an
efficiency of 97.5%. The steady state ac/ac waveforms are
also shown in Fig. 32.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

Huang: Power Semiconduc tor Devices for Smar t Grid and Renewable Energ y Systems

Fig. 32. A 20-kVA solid-state transformer based on 15-kV SiC MOSFET [167]�[168].

V I.  CONCLUSION and high-power handling capability will be needed; hence,

More and more energy is expected to be in the form of
clean electric energy. Efficient processing and delivering of
these energies will require more and more efficient power
semiconductor devices that are approaching the “ideal”
performance. Significant improvement in Si power device
technology has been made in the last six decades, and more
is expected from this cost-effective technology. Newer
power devices based on WBG materials (SiC and GaN)
are the most exciting developments in recent years. These
devices are becoming closer to “ideal” switches. For smart
grid and renewable energy applications, higher voltage
SiC MOSFET and SiC JBS diode are the preferred devices
for the future. Ultrahigh-voltage SiC power devices, such
as SiC MOSFET, IGBT, and GTO, could greatly simplify
existing high-voltage converter systems as well as enable
new applications, such as the solid-state transformer.
More progress is needed to commercialize these devices
and to increase their current ratings in order to challenge
Si power devices’ dominance in high-power applications.
In addition to SiC and GaN, research is also underway to
find other WBG materials and devices that can one day
challenge SiC and GaN. 

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ABOUT THE AUTHORS

Alex Q. Huang (Fellow, IEEE) was born in Zunyi,
Guizhou, China. He received the B.Sc. degree from
Zhejiang University, Hangzhou, China, in 1983,
the M.Sc. degree from Chengdu Institute of Radio
Engineering, Chengdu, China, in 1986, both in
electrical engineering, and the Ph.D. degree from
Cambridge University, Cambridge, U.K., in 1992.
From 1992 to 1994, he was a Research Fel-
low at Magdalene College, Cambridge University.
From 1994 to 2004, he was a Professor at the Bradley Department of
Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA.
Since 2004, he has been with North Carolina State University, Raleigh,
NC, USA and is currently the Progress Energy Distinguished Professor of
Electrical and Computer Engineering. At North Carolina State University,
he led and established the NSF FREEDM Systems ERC in 2008 and the
DOE PowerAmerica Institute in 2014. Since 1983, he has been active in
the development of modern power semiconductor devices and power
integrated circuits. He fabricated the first IGBT power device in China in
1985 and was one of the early pioneers in developing CMOS-compatible
high-voltage integrated circuit (HVIC) in the early 1990s. While at Virginia
Tech, he led one of the earliest development in integrated voltage regu-
lator (IVR) for microprocessor and POL applications. He is the inventor
and key developer of the emitter turnoff (ETO) thyristor technology that
received a prestigious R&D 100 Award in 2003. His group has also recently
demonstrated a world record 22-kV SiC ETO and the world's first symmet-
ric SiC GTO. In 2007, he proposed the concept of Energy Internet as a new
innovation engine for large-scale integration of renewable and distributed
energy resources. To support such a paradigm shift, he led the develop-
ment of the 15-kV SiC MOSFET-based smart transformers as a universal
interface for future grid. The smart transformer technology was named
by MIT Technology Review as one of most important technologies of 2011.
He has mentored and graduated more than 70 Ph.D. and master students,
and has published 500 papers in international conferences and journals.
He has also been granted more than 20 U.S. patents. His current research
interests are smart grid, power electronics, power management microsys-
tems and power semiconductor devices.
Dr. Huang is a recipient of the National Science Foundation (NSF)
CAREER Award and the 2013 Energy Leadership Award.

Proceedings of the IEEE   29