AMRITA VISHWA VIDYAPEETHAM

(University Established U/S 3 of the UGC Act 1956)

AMRITA SCHOOL OF ENGINEERING, BENGALURU

Practical Record
Academic Year July2018- Dec2018
Department of Electrical and Electronics Engineering

Semester: Fifth

Course Code/Title: 15EEE381/ Digital Systems and Signals Lab

Name :

Register No. :
 LIST OF EXPERIMENTS

DIGITAL SYSTEMS

1. Verification of logic gates and Boolean expression using logic gates.

2. Verification of Half Adder and Full Adder circuits.
3. Verification of 4x1 Multiplexer and De multiplexer circuits.
4. Asynchronous UP/DOWN counter using IC 7493.
5. Synchronous and Asynchronous UP/DOWN counters using JK flip-flop.

Evaluation Pattern

Component Weightage
( Marks)
Observation 20
Record 20
Viva 10
Mini Project 10
Lab Test 20
End sem lab Exam 20
Total 100
Exp. No: 1 Date:
VERIFICATION OF LOGIC GATES & REALIZATION OF BOOLEAN EXPRESSIONS
USING LOGIC GATES

Aim:

A) To study the operation of the following logic gates.

i) AND gate
ii) OR gate
iii) NOT gate
iv) EX-OR gate
v) NAND gate
vi) NOR gate

Basic Knowledge Required:

Logic gates, Truth table, Universal gates.

Apparatus Required:
Sl Component Specification Quantity
No
1 IC 7408,IC 7432,IC 7404,IC One each
7486, IC 7400, IC 7402
2 Patch chords As required
3 IC trainer kit 1

Theory:
AND GATE: An AND gate is a logic circuit with two or more than 2 inputs and one output.
The output of an AND gate is logic ‘1’ only when all of its inputs are in
logic‘1’state. In all other cases ,the output is logic ‘0’.
OR GATE : An OR gate is a logic circuit with 2 or more than two inputs and one output
The output of an OR gate is logic ‘0’ only when all of its inputs are at logic
‘0’.For all other possible input combinations, the output is logic ‘1’.
NOT GATE: A NOT gate circuit is one input and one output logic gate whose output is
always the compliment of the input.
EX–OR GATE: This means exclusive OR gate. This gate has a high output only when an
odd number of inputs is high .EX- OR gate produces a logic’1’ whenever either one of the
inputs is ‘1’, but not when both are ‘1’. The EX –OR operator is the sign +, as indicated in the
pin details.
NAND GATE: An AND gate followed by a Not circuit make it NAND gate .It is also a logic
circuit having two or more than two inputs and one output .The output of a
NAND gate is logic ‘0’ only when all of its inputs are in logic ‘1’ state .In all other cases ,the
output is logic ‘1’.
 NOR GATE: An OR gate followed by an NOT circuit make it as an NOR gate. It is also a
logic circuit having two or more than two inputs and one output. The output of a NOR gate is
logic ‘1’ only when all of its inputs are in logic ‘0’ state .In all other cases, the output is
logic’0’.

Procedure:

1. Check all the components and patch chords whether they are in good condition.
2. Insert the appropriate IC into IC base.
3. Make connection as shown in pin details.
4. Give supply to the trainer kit.
5. Verify the truth table and observe the outputs.

NAND GATES
IC 7400

Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
OR GATE
IC 7432
Logic Symbol

Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

AND GATE (IC 7408)

Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
NOR GATE

IC 7402

Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

NOT GATE
IC 7404
EX-OR GATE ( IC 7486)

b) Realization of Boolean Expression using logic gates:

Basic Knowledge Required:

Boolean algebra, simplification of any equations using Boolean algebra,

De-Morgan’s theorems, Karnaugh map.

Theory:

Boolean expression consists of variables, which can have one of the two possible
values, either one or zero .There are two methods to minimize Boolean expression.
a) Boolean algebra
b) Karnaugh map

Boolean algebra: This provides a means by which logic circuitry may be expressed
symbolically, manipulated and reduced. Use of Boolean algebra in logic circuits leads
to the following results.
a) Minimizes the number of logic gates in a circuit
b) Minimizes the cost of a circuit
c) A circuit which uses only one type of basic logic gate such as NAND gate
becomes possible.
d) A circuit having parallel, redundant gates with minimum propagation delay can be
designed.
 De-Morgan suggested two theorems that form an important part of Boolean algebra that is
(a) Sum of Product (SOP)
For ex: AB  A  B
(b) Product of Sum: (POS)
For ex: ( A  B  A.B )

Karnaugh Map: This is a pictorial technique for simplification of Boolean functions .It is
reliable method of reducing a sum of products algebraic expression to its minimal
form that is to form a minimum Sum of product or product of sum expressions,
commensurate with the desired output of a logic circuit.

Procedure:

1) Verify the components and patch chords whether they are in good condition or not .
2) Make connection as shown in circuit diagram
3) Give supply to trainer kit
4) Provide the input data to the circuit via switches
5) Verify the truth table sequence and observe the outputs.
Exp. No: 2 Date:

HALF/FULL AADDER

Aim: To realize half/full adder circuits using logic gates

Basic Knowledge Required:

Logic gates, half & full adder circuits using different gates.

Apparatus Required:

Sl No Apparatus Specification Quantity

1 IC Trainer kit 1
2 IC’s 7486,7408,7432,7404 1 each
3 Patch Chords 1 set

Theory:

The simplest binary adder is called a half adder. Half adder has two input bits and two
output bits .One bit is the sum and the other is carry .S and C represents these respectively in the
logic symbol.
A half adder has no provision to add a carry from the lower order bits when binary numbers
are added .When two input bits and a carry are to be added the number of input bits becomes three
and the input combination increases to eight. For this, a full adder is used .It also has a sum bit and
a carry bit. New carry generated is represented by Cn and the carry generated from the previous
addition is represented by Cn-1

Procedure:

1. Check all the components and patch chords whether they are in good condition.
2. Insert the appropriate IC into IC base.
3. Make connection as shown in pin details.
4. Give supply to the trainer kit.
5. Verify the truth table and observe the outputs.

Logic Diagram: Half Adder

Logic Diagram: Full Adder

Truth Table

Result:
Exp. No: 3 Date:

MULTIPLEXER & DEMULTIPLEXER

Aim:

Realization of 4:1 multiplexer & 1:4 Demultiplexer using logic gates/built in ICs.

Basic Knowledge Required:

Multiplexer-definition, ways of building a MUX, applications.

Demultiplexer- definition, ways of building a DEMUX, applications

Apparatus Required:

Sl No Component Specification Quantity

1 IC Trainer Kit 1
2 IC’s 7420 3
3 Patch cords 1set
4 IC’s 7400 2

Theory:

The multiplexer is a logic circuit that gives single output from several inputs. The input
selected is controlled by a set of select inputs.
Advantages:
i) Simplification of logic expression is not required.
ii) It minimizes the IC package count
iii) Logic of design is simplified.
The De multiplexer performs the reverse operation of a multiplexer .It accepts a single
input signal & gives several outputs .The selected input code determines to which output the data
input will be transmitted. IC’s 74X153 & 74X139 are the built in IC’s for multiplexing and de
multiplexing.

Procedure:

1. Connections are made as per the circuit diagram using pin details of gates.
2. Verify the truth table of MUX & DEMUX.
3. Verify the DEMUX using built in IC 74LS139
Logic diagram for 4:1 MUX using logic gates:

Truth table for 4:1 MUX

Enable Select I / O Data input Output

Comment
E S1 S0 A0 A1 A2 A3 Y
0 0 0 0 X X X 0 ‘A0’ selected
0 0 0 1 X X X 1 ‘A0’ selected
0 0 1 X 0 X X 0 ‘A1’ selected
0 0 1 X 1 X X 1 ‘A1’ selected
0 1 0 X X 0 X 0 ‘A2’ selected
0 1 0 X X 1 X 1 ‘A2’ selected
0 1 1 X X X 0 0 ‘A3’ selected
0 1 1 X X X 1 1 ‘A4’ selected
Logic Diagram for 1:4 DEMUX using logic gates :

Truth table for 1:4 DEMUX

Enable Select inputs Data I / P Outputs

E S1 S0 D0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 0 0
0 1 1 0 0 0 0 0
0 1 1 1 1 0 0 0

1:4 DEMUX using IC 14LS139 IC

Realize the 1:4 DEMUX using IC 74LS139 whose PIN diagram is shown and Truth table
are given below.
 PIN DIAGRAM

Result:
Exp. No: 4 Date:

UP-DOWN RIPPLE COUNTERS WITH ASYNCHRONOUS CLOCK USING IC 7493

Aim:
To realize and study UP and DOWN ripple counters using counter IC 7493.

Apparatus Required:

IC 74LS93, patch-chords, power-chord, IC trainer kit and CRO.

Theory:

The IC 7493 is a mod-16 ripple counter. This device actually consists of a single flip-flop
and a three bit asynchronous counter. It can be used as a divide by 2 devices using only the single
flip-flop or it can be used as a modulus-8 counter using only the three bit counter portion. This
device also provides gated reset inputs, R0 (1) and R0 (2). When both of these inputs are high, the
counter is RESET to 0000 states by CLR.
Additionally, the 7493 can be used as a four bit module 16 counter by connecting the QA
output to the CLK B input. It can also be configured as decade counter.

Procedure:

1. Verify all the components and patch chords whether they are in good condition.
2. Make connection as shown in circuit diagram.
3. Give supply to the trainer kit.
4. Apply manual pulses at input A [pin no. 14] and note down the binary count and
Verify that it’s function as mod-16 counter.
5. Apply [say 10 KHz] clock pulses at input A [pin no. 14] and observe output at QD.
6. What is the relation between input A and QD.
7. Verify the result.

TTL IC 7494 used as a Binary Counter.

Pin Details
INTERNAL DIAGRAM OF IC 74LS93

MOD-16 UP Counter:
Count Table

Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
0 0 0 0 0

Timing Diagrams:
MOD-12 UP COUNTER:

Count Table:
Down Counter:

Count Table:

Clock QD QC QB QA
15 1 1 1 1
14 1 1 1 0
13 1 1 0 1
12 1 1 0 0
11 1 0 1 1
10 1 0 1 0
9 1 0 0 1
8 1 0 0 0
7 0 1 1 1
6 0 1 1 0
5 0 1 0 1
4 0 1 0 0
3 0 0 1 1
2 0 0 1 0
1 0 0 0 1
0 0 0 0 0
15 1 1 1 1

Result:
Exp. No: 5 Date:

UP/DOWN RIPPLE COUNTERS WITH ASYNCHRONOUS/SYNCHRONOUS CLOCK

Aim:
To realize and study of up and down ripple counters using JK flip flops by giving an
asynchronous and synchronous clock..

Apparatus Required:

IC 74LS76, patch-chords, power-chord, IC trainer kit.

Theory:

Counters can be implemented using the adder/subtractor circuits and registers (or equivalently,
flip flops. Here we design the counters by using JK flip-flops.

JK -Flip Flop IC: 74LS76

The JK FF IC 74LS76 has two JK FFs in each IC. It has active low preset (PRE) and clear(CLR)
pins. Hence, when both PRE and CLR pins are deactivated (by feeding a 'HIGH' input), the FF acts
as a JK FF. It has a negative edge triggered clock input. The pin diagram, function table and the
internal logic diagram are shown below. If the inputs J and K are shorted, then the JK FF will act
as a T FF. This concept is used in building counters using JK FF.

PIN DIAGRAM
 Sl. INPUT OUTPUT
No.
SD CD J K Remarks
1 L H X X H L Set operation :Preset Pin
2 H L X X L H Clear operation : Clear Pin
3 L L X X H H Undefined state
4 H H L L No change from JK inputs
5 H H L H L H Reset operation
6 H H H L H L Set operation
7 H H H H Compliment operation/Toggle

Asynchronous Up-Counter with JK Flip-Flops. The figure below shows a 3-bit counter capable
of counting from 0 to 7 or 7 to 0. The clock inputs of the three flip-flops are connected in cascade.
The JK input of each flip-flop is connected to a constant 1, which means that the state of the flip-
flop will be toggled at each active edge (here, it is positive edge) of its clock.

Here, the purpose of this circuit is to count the number of pulses that occur on the primary input
called Clock. Thus the clock input of the first flip-flop is connected to the Clock line. The other
two flip-flops have their clock inputs driven by the Q output of the preceding flip-flop. Therefore,
they toggle their states whenever the preceding flip-flop changes its state from Q=1to Q = 0, which
results in a positive edge of the Q signal.

In a synchronous counter the clock signal is synchronized and fed by a common clock.
COUNTING TABLE FOR THE COUNTERS

UP COUNTER DOWN COUNTER

Clock
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 1 1 1
1 0 0 1 1 1 0
2 0 1 0 1 0 1
3 0 1 1 1 0 0
4 1 0 0 0 1 1
5 1 0 1 0 1 0
6 1 1 0 0 0 1
7 1 1 1 0 0 0

A 3−bit UP COUNTER ( MOD-8) using Asynchronous clock

Timing diagram for a 3−bit UP COUNTER.

A 3−bit DOWN COUNTER ( MOD-8) with Asynchronous clock.

Timing diagram for a 3−bit DOWN COUNTER

.
3−bit UP COUNTER ( MOD-8) with Synchronous clock
Procedure:

1. Verify all the components and patch chords whether they are in good condition.
2. Verify the JK FF characteristic table.
Connect the JK Flip-Flops to realize as the T-Flip flop.
3. Make connection for the asynchronous / synchronous counter as shown in circuit
diagrams.
4. Apply the clock pulse and check the result.
4. Verify the result at every clock pulse.

Result: