1

EXPERIMENT 01

RTL Circuits

Objectives
1. Examine the RTL characteristics.
2. Familiarize with the internal working of the RTL circuits.
3. Design and analyze an RTL inverter and determine its input-output
characteristics, Propagation delay, and noise margins.

Required Equipments
• Oscilloscope
• Power supply
• Function generator
• Digital Multimeter
• Bread-Board o Protoboard

Required Parts list

• 10 KΩ ¼-watt resistor.
• 0.1 μF capacitor
• 470 Ω ¼-watt resistor.
• 2N2222 NPN silicon transistor, or equivalent
• 1N4001 Diode semiconductor

Background
Resistor-Transistor Logic (RTL) refers to the obsolete technology for designing
and fabricating digital circuits that employ logic gates consisting of nothing but
transistors and resistors. RTL gates are now seldom used, if at all, in modern digital
electronics design because it has several drawbacks, such as bulkiness, low speed, limited
fan-out, and poor noise margin. A basic understanding of what RTL is, however, would
be helpful to any engineer who wishes to get familiarized with TTL, which for the past
many years has become widely used in digital devices such as logic gates, latches,
buffers, counters, and the like.

Basically, RTL replaces the diode switch with a transistor switch. If a +5V signal
(logic 1) is applied to the base of the transistor (through an appropriate resistor to limit
base-emitter forward voltage and current), the transistor turns fully on and grounds the
output signal. The output signal rise to +5 volts if the input is grounded (logic 0), the
transistor is off. In this way, the transistor does invert the logic sense of the signal, but it
 2

also ensures thaat the outpuut voltage will alwayss be a valiid logic levvel under all
a
circum
mstances.

RTL gatees also exhibbit limited 'faan-outs'. Thee fan-out off a gate is thee ability of itts
outpuut to drive seeveral other gates. The more gates it i can drive,, the higher is its fan-ouut.
The fan-out
f of a gate is limitted by the cuurrent that itss output can supply to thhe gate inputts
conneected to it when
w the outtput is at loggic '1', sincee at this statee it must be able to drivve
the coonnected inpput transistorrs into saturaation.

Another weakness
w off an RTL gatte is its poor noise margiin. The noise margin of a
logic gate for loggic level “0”,, Δ0, is definned as the difference betw
ween the maaximum inpuut
voltage that it will recognize as a “0” (VIL I ) and the m
maximum vo
oltage that may
m be applieed
to it as a “0” (V VOL of the driving
d gate connected to it). For logic level '1', the noisse
marggin Δ1 is the difference between
b the minimum innput voltage that may bee applied to it
as a '1'
' (VOH of the t driving gate
g conneccted to it) annd the minimmum input voltage
v that it
will recognize
r ass a '1' (VIH).
) Mathemaatically, Δ0 = VIL-VOL and a Δ1 = VOH-VIH. Anny
noisee that causess a noise maargin to be overcome
o w result in a “0” beingg erroneouslly
will
read as
a a '1' or vicce versa. Inn other wordss, noise marggin is a measure of the immmunity off a
gate from
f reading g an input loogic level inccorrectly.

In an RT TL circuit, the collectoor output of o the drivinng transistoor is directlly

conneected to the base resistorr of the driven transistorr. Circuit annalysis wouldd easily showw
that in
i such an arrrangement, the differennces betweenn VIL and VOL O , and betw
ween V OH an
nd
VIH, are
a not that large. This is why RTL L gates are known
k to haave poor noisse margins ini
compparison to DTTL and TTL L gates.

Some yeaars ago, whhen RTL ICss were the standard loggic devices used in botth
comm mercial and experimentaal digital cirrcuits, transisstors typicallly had a forrward currennt
gain of about 30 0. With impproved manuufacturing techniques,
t m
modern trannsistors show
w
curreent gains of 100 or morre. There is also far lesss variation between traansistors of a
givenn type. As a result, we can tolerate a much loweer input current to drive the transistoor
reliabbly into satturation. Thhe resistor values in the schemaatic diagram m reflect thhe
capabbilities of modern
m transiistors; they are significantly higherr than the vaalues used in i
RTL ICs, allowin ng working circuits
c to bee built that reequire far lesss operating current.

RTL
L Inverterr
The outp put signal of a NOT T logic gaate
(Inveerter) is the complementt of the inpuut signal. Thhat
is, whhen the inpuut signal is low
l “0”, thee output signnal
is higgh “1” and vice
v versa. A NOT gatee can be easily
obtainned by mean ns of an invverting ampllifier circuit as
showwn in Figure 1.
 3

Voltaage Transfeer Characterristic

The voltaage transfer characteristtic (VTC) iss nothing buut a sketch of o the outpuut
voltage as a functtion of the innput voltagee. In this casee, the input voltage
v is inccrease from 0
to its maximum value
v (VBB). When the innput voltagee is zero, the transistor iss OFF and thhe
outpuut voltage iss 5 V. This is the maxim mum outputt voltage thaat we can obtain for thiis
circuit. Let us lab
bel this voltaage as VOH. The
T transistoor remains inn its cutoff state
s (OFF) as
a
long as the input voltage is leess than 0.6 V.
V

Transsistor operation charactteristics

• Base-to-eemitter cut-inn (turn-ON) voltage VBEE(ON) = 0.6 V
• Base-to-eemitter voltagge in the acttive region VBE = 0.7 V
• Base-to-eemitter voltagge in the satuuration regioon VBE(sat) = 0.8 V
• Collector--to-emitter voltage
v in thee saturation region VCE(sat) = 0.2 V

As soon as the inputt voltage reaaches 0.6 V, V the transisstor is readyy to turn ON
N.
he maximum
Thus, 0.6 V is th m input voltagge that we can
c apply to the transistoor and keep it
in its cutoff modee. Let us label it as VIL. These
T wn in Figure 2.
voltagges are show

Figure 2: Transfer chaaracteristic of

o an RTL Innverter

When thee input volttage increasees above 0.6 V, the traansistor enters its activve
region. As soon as a the input voltage goees above 0.7 V, the base-to-emitter voltage
v in thhe
activee region is 0.7
0 V. The remainder of o the applieed voltage iss the voltagee drop acrosss
RB, which
w resultts in the basse current annd thereby thhe collector current. As the collectoor
 4

current begins to flow in the transistor, the output voltage begins its decline. As the input
voltage increases, the base current increases, the collector current increases, and the
collector-to-emitter voltage decreases. The operation in the active region continues until
the collector-to-emitter voltage becomes equal to its saturation voltage. The transistor is
now at the verge of saturation. The collector current is 10.21 mA. If β = 100, the base
current is 0.1021 mA. Let us denote the input voltage that forces the transistor to enter the
saturation region as VIH. Note that VIH is the minimum value of the high-input voltage
and is given as

If we denote the corresponding low output voltage as VOL, then VOL = VCE(sat) =
0.2 V. These voltages are also shown in Figure 2. As the input voltage increases above
1.82 V, the output remains at 0.2 V and the transistor goes into deep saturation. The
operation in the deep saturation region continues until the input voltage reaches its
maximum value.

SUMMARY: In the above discussion we have defined some terminology pertaining to

the RTL circuit. We will use this terminology for all types of gates. Therefore, let us
formally define it.

Voltage Transfer Characteristic

VOH = Nominal High Output Voltage

This is the output voltage that corresponds to logic 1 (high) and it may vary with the
loading and temperature. The manufacturers usually specify its minimum value in order
to compensate for the component tolerances and variations in the loading conditions.

VOL = Nominal Low Output Voltage

This is the gate output voltage that corresponds to logic 0 (low). The manufacturers
usually specify its maximum value.

VIH = High input voltage at which |dvo/dt| = 1

The minimum input voltage that is interpreted as logic 1 (high) by the gate.

VIL = Low input voltage at which |dvo/dt| = 0

The maximum input voltage that is interpreted as logic 0 (low) by the gate.

Transition Region: The region between VIL and VIH is called the transition region.

Transition region is mostly the active region and it is the forbidden region for the
logic circuit. The input voltage should either be low (less than or equal to VIL) or high
(greater than or equal to VIH). If there is a random noise in the system, it should be small
enough such that it does not drive the transistor into the forbidden region.

Transition Width: It is the difference between the two input voltages (VIH – VIL). For
RTL gate, the transition width is 1.22 V.
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Logic Swing: The difference between the two output voltages (VOH – VOL) is designated
as the logic swing. For the RTL under discussion, the logic swing is 4.8 V.

Noise Margins

The input signal to a gain can be corrupted by some unwanted and unexpected
signal. If the gate is not properly designed the unwanted signal can force the gate to
malfunction. A noise margin is the figure of merit for the gate. If the noise margin is high
the gate is less susceptible to malfunction. We define the noise margin for each level of
the input signal. Thus, we have the definitions for the lower- and upper-noise margins for
the low- and high-level of the input signal.

These margins are defined as follows:

The Lower Noise Margin: NML = VIL – VOL

By definition, it is the difference between the maximum allowed input voltage

that can be interpreted as low by the gate and the actual low output voltage of the
preceding stage driving the gate. For the RTL circuit we just analyzed, the maximum
input voltage that can be interpreted by the gate as low is 0.6 V. The gate usually receives
the input signal from the other gate whose minimum output is 0.2 V. Then the lower
noise margin is 0.4V=(0.6V – 0.2V). Keep in mind that each gate generates a random
noise voltage, however small it may be. For the RTL gate under discussion, the largest
random noise voltage that can corrupt the low input signal is 0.4 V. The reason, of
course, is that when the random noise voltage is added to the input voltage, the total
voltage should be less than or equal to the maximum input voltage that is interpreted as
low by the gate. Since the actual input signal voltage is 0.2 V, the maximum input
voltage that can be added to it is 0.4 V, which is simply the lower noise margin.

The Upper Noise Margin: NMH = VOH – VIH

By definition, it is the difference between the actual output voltage of the

preceding stage driving the gate and the minimum value of the input voltage that can be
interpreted as high by the gate. For the RTL gate under discussion, the maximum input
voltage is VBB=5 V. The minimum input voltage that the gate can interpret as high is 1.82
V. Then, the upper noise margin is 3.18 V = (5V – 1.82V). This simply means that the
largest random noise voltage that the gate can tolerate is 3.18 V. The logic circuit should
still be able to interpret the input voltage as high when the upper noise margin is
subtracted from the input signal. All our discussion pertains to a single RTL circuit.
When it is used as a driver for other gates, its noise margins are bound to change, as we
will show later.
 6

Dynamic Response of Logic Gates

An important figure of merit to describe logic gates is their response in the time
domain.

The rise and fall times, tf and tr, are measured at the 10% and 90% points on the
transitions between the two states as shown by the following expressions:

V10% = VL + 0.1ΔV

V90% = VL + 0.9ΔV = VH – 0.1ΔV

Where ΔV = VH – VL. Rise and fall times usually have unequal values; the characteristic
shapes of the input and the output waveforms also differ.

Propagation Delay

• Propagation delay describes the amount of time between a change at the 50%
point input to cause a change at the 50% point of the output described by the
following:
VH + VL
V50% =
2
 7

• The high-to-low propagation delay, τPHL, and the low-to-high propagation delay,
τPLH, are usually not equal, but can be described as an average value:
τ PLH + τ PHL
τP =
2
 8

Pre – Laboratory
RTL Inverter Propagation Delay

In this laboratory the concept of propagation delay is addressed for the RTL
inverter using PSPICE to simulate Transient behavior. The RTL inverter circuit is shown
in Figure 5.

Figure 5: RTL Inverter Schematic Circuit

Circuit description and specific parameters

The input voltage vin is a PULSE waveform with an amplitude of 5V, the rise time
(TR) and fall time (TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of
200 NS and a period (PER) of approximately 500 NS.

The transistor used in all simulations will be a 2N2222 with the following model
parameters for both Netlist and Schematic circuit.

.MODEL parameters for the npn transistor are:

IS=1E-14 A, BF=50, VAF=80 V, TF=0.45NS, TR=5NS, CJE=7.6PF, CJC=3PF, RB=13,
RC=6.2
 9

Pre – Laboratory Procedure

1. Use PSPICE 1 to get the transient response for the circuit shown in Figure 5.
2. Plot both Vin and VCE as outputs superimposed on the same plot.

3. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the
report's questions.
4. Determine τPHL and τPLH for the simulation and record the values in the report's
questions.
5. Print the plot.

Pre – Laboratory Report

1. What are the values for :

VIL =_____ VIH = _____

VOL = _____ VOH = _____

2. Calculate τPLH and τPHL for the simulation.

τPLH = __________________ τPHL = _________

3. What is the propagation delay of the gate?

τP = _________

1
First become familiar with the MicroSim PSPICE software installed on the PC Lab (INCADEL or

CRAY). Refer to the manual for PSPICE for getting started in the construction of a circuit, adding

Specific Parameters for Transient Analysis and for other tips for plots or visit

https://ece.uprm.edu/seminarios/.
 1
10

Labboratory Procedure
P e
RTL
L Inverter Voltage
V Trransfer Chaaracteristicc

1. Wire the
t circuit shhown in Figuure 6.

2. With your
y Multim
meter, measuure the base--emitter, base-collector, collector-em
mitter,

and collector
c DC
C voltages, with
w respectt to ground, and measuure the basee and

collecctor DC curreents, recordiing your valuues in table 1 of the repoort.

3. Use th
he Oscillosccope with thee Y-axis sennsitivity set to
t 1 Volt/divvision and thhe X-

axis sensitivity at 0.5 Volts/diivision.

4. Adjusst the X zeroo reference to the screeen center and the Y refe
ference below
w the

centerr.

5. The in
nput VS is a sine wave from
f a functiion generatoor with a peaak amplitudee of 5

Volts and frequenncy of 100 Hertz.

H

6. Draw a rough skketch of the characteristtic displayedd on the oscilloscope in the

hic 1(Indicatte the scaless that were used) of the report

Graph r and assk the question.

7. Determ
mine VIL, VIH, VOL, andd VOH for thee VTC displayed on the oscilloscope and

record
d the values in the reportt's questions.

Figure 6
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Laboratory Report

Table 1

Measured Measured
Valued Valued
DC Parameters Vin = 0V Vin = 5V
IC
IB
VC
VBC
VBE
VCE

Graphic 1
 12

1. Record the values of VS corresponding to the VC values given below from the
transfer curve displayed on the oscilloscope.

VC = 4V Vin =______V.

VC = 3V Vin =______V.

VC = 2V Vin =______V.

2. What are the values for :

VIL = _____ VIH = _____

VOL = _____ VOH = _____

3. What are the noise margins for the Gate?

NMH = ____________

NML = ____________
 13

EXPERIMENT 02

7400 Standard NAND Gate: Transient Analysis and Voltage Transfer

Characteristic.

Objectives
4. Examine the TTL characteristics.
5. Familiarize with electrical properties of logic gates built from bipolar transistors
(TTL).
6. Build and test logic gate networks for measure its voltage transfer characteristics,
Propagation delay, Fan-Out, and power dissipation of the 7400 TTL NAND.

Required Equipments
• Oscilloscope
• Power supply
• Function generator
• Digital Multimeter
• Bread-Board o Protoboard

Required Parts list

• 1 200 Ω ¼-watt resistor

• 1 510 Ω ¼-watt resistor
• 2 1 KΩ ¼-watt resistors
• 1 10 KΩ potentiometer
• 1 1N4148 Diode
• 1 7400 TTL NAND gate

Background
Now that we have studied the characteristics of the saturating transistor inverter,
we have the knowledge in place to understand the behavior of the transistor-transistor
logic or TTL. For years, TTL has been a workhorse technology for implementing digital
functions and for providing “glue logic” necessary in microprocessor system design. TTL
is interesting from another point of view since it is the only circuit that we shall encounter
that makes use of transistors operating in all four regions of operation—forward-active,
inverse-active, saturation, and cutoff.

The classical TTL inverter shown in Figure 1 solves is the typically circuit found
in TTL unit logic in which several identical gates are packaged together in a single dual-
in-line package, or DIP. Transistor Q1 controls the supply of base current to Q2. Input
voltage Vi causes the current iB1 to switch between either the base-emitter diode or the
base-collector diode of Q1. Q2 forces the output low to VCESAT2. The load resistor is an
 14

active pull-up circuit formed by transistor Q4 and diode D1. Q3 and D1 are required to
ensure that Q4 is turned off when Q2 is turned on and vice versa.

Figure 1

A complete standard Two-input TTL NAND gate is shown in the schematic in

Figure 2. If any one of the two input emitters is low, then the base current to transistor Q3
will be zero and the output will be high, yielding Y = AB .
 15

Figure 2

In this lab, you will know the electrical properties of logic gates built from bipolar
transistors (TTL)

Power Dissipation

Power dissipation is the power lost in the transistors of a logic gate. Since modern
integrated circuits involve millions of transistors, it is important to minimize this power
loss (the very first Pentium CPU had 3.2 million transistors).

y measuring the input characteristics and the transfer characteristics of all the
chips, we can assess the power loss of each chip. The current flowing into a gate at any
point is a good indication of power dissipation. To assess the amount of power dissipated
by a gate at a specific state, we simply measure the current flowing into the gate at that
state. A comparison of the output voltage to the input voltage during a change in state of
a logic gate can provide information on how much power is lost as the gate switches. In
the plot of output voltage versus input voltage, the slope indicates the amount of power
dissipation. A steeper slope indicates smaller power dissipation.

Pre-Laboratory Procedure

Perform the following simulations for the 7400 TTL NAND of the Figure 2.
1. DC transfer characteristics: Use the DC command to step Vin from 0 to 5V in
 16

0.1V increments. Obtain the plot of the DC transfer curve Vout versus Vin using
PROBE.

2. Transient response: Carry out a transient simulation and obtain the plot of Vin
and Vout using PROBE. Use Vin as a PULSE waveform with an amplitude of 5
Volts, rise and fall times equal to 2 NS and delay time equal to 0 NS, set the pulse
duration for 50 NS and pulse period for 100 NS.

Pre-Laboratory Report
1. For the 7400 TTL NAND gate, determine VIH, VOH, VIL, VOL and the break
points from the DC simulations.

2. From the transient simulations, determine τPHL and τPLH and calculate the average
propagation delays for TTL NAND gate.

3. Calculate the average power dissipation for the circuit.

Laboratory Procedure

Part A: Electric Characteristics

1. Assemble the circuit in Figure 3 using the 7400.

a. Mount the 7400 (TTL) carefully and firmly with the pins in the center rows of
your breadboard. Connect the 5-volt DC supply to VCC and connect ground
to GND of the 7400.

b. Connect pin 1 to the +5V supply via the 1kΩ resistor, connect pin 2 to one of
the probes of the digital Multimeter (DMM), and leave the other probe
unconnected. Use the DMM to measure the input current when the second
probe is connected to +5V via the 1kΩ resistor (pin 2 is pulled high), and
when the second probe is connect to ground via the 510Ω resistor (pin 2 is
pulled low). Use the DMM to measure the output voltage at pin 3 as the input
voltage is changed. Record the readings, indicating the polarities, in the Table
1 of the report.

c. Remove the 7400, and replace it with the 74LS00 and repeat step a and b. You
can use the same circuit configuration because the pin locations for all two
chips are exactly the same.
 1
17

Figure 3

2. Assemblee the circuit in

i Figure 4 using
u the 74000.
3. Vary the input
i voltage from zero to maximum m by adjustinng the potenttiometer.
4. Measure the
t indicatedd voltages, Vi and VO, ussing either thhe digital Muultimeter or
the oscillo
oscope. Recoord the readiings in Tablee 2 of the repport.
5. Remove thet 7400, andd replace it with
w the 74L LS00 and reppeat step 3 annd 4.

Figure 4

Note: For the dettails of the pin-outs

p and other devicee characteristtics, see the specificationn
sheetts at the back
k of your maanual, or the Motorola Web
W site.
 1
18

Part B: Dynamic Behavior

1. Assemblee the circuit in

i figure 5 using
u the 74000

2. Using thee function generator,

g prroduce a 5VV peak-to-peeak triangular wave at 1
KHz. Adjjust the DC Offset on thhe function generator
g to create a positive unipolaar
wave, wh
hich means thhe signal nevver drops below zero.

3. Use channnel 1 of the oscilloscope

o e to measure Vi and channnel 2 to measure VO. Seet
both chan
nnels of the oscilloscope
o to DC couppling.

4. Sketch the waveform m of VO versuus Vi on the graphic 1 provided

p in the
t laboratorry
report. Ind
dicate the sccales that weere used.

5. To display the outputt voltage (VO) versus thee input voltaage (Vi) wavveform on thhe
oscillosco
ope, Turn Time/divisionn button to XY. The waveform
w thaat you obtaiin
displays channel
c 2 (VVO) versus channel 1 (Vi). Channeel 2 is on thhe y-axis annd
channel 1 is on the x-axis.

6. Remove the
t 7400, andd replace it with
w the 74L
LS00 and reppeat step 2 too 5.

Figure 5

P
Part C: Fan--Out for thee 7400 TTL
L NAND

1. Connect the
t circuit ass shown in fiigure 6 usingg the 7400.

2. VS is a sine wave with amplittude of appproximately 5 Volts annd frequenccy

mately 100 Hzz. Set the osscilloscope in
approxim i the DC annd X-Y modees.

3. Plot the DC
D transfer curve
c displaayed on the oscilloscope
o for a fan-ouut of 6 on thhe
graphic 2 of the reporrt. Indicate thhe scales thaat were used.
 1
19

Figure 6

4. Connect the
t output of o one gate to the six innputs of thee remaining three NAND D
gates (as shown in Fiigure 7) andd plot the DC C transfer cuurve for a faan-out of 6 on
o
the graphiic 3 of the reeport. Indicaate the scaless that were used.
u

5. Determine the averagge power dissipation in thhe IC by meeasuring the current beinng
supplied by
b VCC. Use an analog DC Multim meter for the dc current measuremen
m nt.
Do NOT use
u the digittal Multimeteer for the current measuurement.

6. Remove the
t 7400, andd replace it with
w the 74L
LS00 and reppeat the step 1 to 5.

Figure 7
 20

Laboratory Report
Table 1
V-I Characteristic 7400 74LS00
Input current when pin 2 is high
Output voltage when pin 2 is high
Input current when pin 2 is low
Output voltage when pin 2 is low

Table 2
Voltage Characteristics
7400 74LS00
v i vO vO
0V
2V
4V
6V
8V
10V

Graphic 1(7400 and 74LS00)

 21

1. From the input current values that were measured in Part A-1, which is the power
dissipation for both chips? Explain your reasoning.

2. Using the table of measured values that you obtained in Part A-4 plot VO versus
Vi for the 7400 and 74LS00 in different colors.

3. Refer to the data sheet of the DM7400 to obtain the value of VIH. VIH is the
Manufacturer’s minimum level for an input 1. On the graph you just plotted, draw
a vertical line at Vi =VIH. Does the chip operate within this specification? Explain
your reasoning. You may want to look at the typical values for VOH and VOL.
 22

4. From the data sheet of the DM7400, find the value of VIL. This is the
manufacturer’s maximum level for and input 0. On the graph of the previous
page, draw a vertical line at Vi = VIL. Does the chip operate within this
specification? Explain your reasoning.

5. Compare the static and dynamic measurements of the transfer characteristics for
the 7400 and explain your conclusions.

Graphic 2(7400 and 74LS00)

 23

Graphic 3(7400 and 74LS00)

6. What are the noise margins (NML and NMH) for a fan-out of 2 and 6 for both
chips?

7. How much is average power dissipation in both chips?

 24

EXPERIMENT 03

Analysis of a Schottky RTL inverter

Objectives
7. Examine the Schottky RTL characteristics.
8. Familiarize with the internal working of the Schottky RTL circuits.
9. Design and analyze a Schottky RTL inverter and determine its input-output characteristics,
Propagation delay, and noise margins.

Required Equipments
• Oscilloscope
• Power supply
• Function generator
• Digital Multimeter
• Bread-Board o Protoboard

Required Parts list

• 10 KΩ ¼-watt resistor.
• 470 Ω ¼-watt resistor.
• 0.1uF capacitor.
• 1N4148 diode rectifier.
• 2N2222 NPN silicon transistor or equivalent.
• NTE583 or NTE584 Schottky diode.

Background
A serious problem that severely limits the switching speed of BJT inverter is the amount of time
required to remove the enormous stored charge from the base of a saturated BJT. The Schottky-clamped
transistor drawn in figure 1 was developed to solve this problem. The Schottky-clamped transistor consists
of a metal semiconductor Schottky barrier diode (SBD) in parallel with the collector-base junction of the
bipolar transistor.

When conducting, the forward voltage drop of the Schottky diode is designed to be approximately
0.30 to 0.45 V, so it will turn on before the collector-base diode of the bipolar transistor becomes strongly
forward-biased. Referring to Figure 1, we see that

v =v −v
CE BE SBD = 0.70V − 0.30V = 0.4 V
 25

Figure 1: Schottky-clamped transistor.

If the input current in increased, the SBD will begin to conduct at VSBD(ON) =
0.3V. Hence, the base-collector junction reaches the forward-bias of VBC = 0.3V. Any
further increase in current i’B entering this configuration will be diverted from the base of
the BJT, though the SBD, and turn into the collector of the BJT. Thus, VBC is limited to
VSBD(ON) = VBC(HARD)= 0.3V. This BJT – SBD combination is called a Schottky-
clamped BJT (SBJT) or Schottky transistor and the BJT cannot operate in saturation.
Hence, the time consuming saturation stored-charge removal (and insertion) for the base
is eliminated.

The mode of operation where the BJT is forward active and the Schottky diode is
conducting is referred to as the “on hard” mode. This mode is similar to saturation with
VBE increased to 0.8V, except VBC is only forward biased to 0.3V. An SBJT inverter is
shown in Figure 2.

Figure 2: Schottky RTL inverter

Invention of this circuit required a good understanding of the exponential dependence of the BJT
collector current on base-emitter voltage as well as knowledge of the differences between Schottky and PN
junction diodes. Successful manufacture of the circuit relies on tight process control to maintain the desired
difference between the forward drops of the base-emitter and Schottky diodes.
 26

Pre – Laboratory
Schottky RTL Inverter Propagation Delay

In this laboratory the concept of propagation delay is addressed for the Schottky RTL inverter
using PSPICE to simulate Transient behavior. The Schottky RTL inverter circuit is shown in Figure 3.

Figure 3: Schottky RTL Inverter

Circuit description and specific parameters

The input voltage VS is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time

(TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of 200 NS and a period (PER) of

approximately 500 NS. The transistor used in all simulations will be a 2N2222.

Pre – Laboratory Procedure

6. Use PSPICE to get the transient response for the circuit shown in Figure 3.

7. Plot both vin

and v
OUT
as outputs superimposed on the same plot.

8. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's

questions.
 27

9. Determine τPHL and τPLH for the simulation and record the values in the report's questions.

10. Print the plot.

Pre – Laboratory Report

4. What are the values for :

VIL =_____ VIH = _____

VOL = _____ VOH = _____

5. Calculate τPLH and τPHL for the simulation.

τPLH = __________________ τPHL = _________

6. What is the propagation delay of the gate?

τP = _________

Laboratory Procedure
Schottky RTL Inverter Voltage Transfer Characteristic
8. Wire the circuit shown in Figure 4, the input voltage VS = 0V.

9. With your Multimeter, measure the base-emitter, base-collector, collector-emitter, and collector

DC voltages, with respect to ground, and measure the DC currents and record your values in table

1 of the report.

10. Set the input voltage at 5V and repeat the step 2.

11. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at

0.5 Volts/division.

12. Adjust the X zero reference to the screen center and the Y reference below the center.
 28

Figure 4

13. Wire the circuit shown in Figure 5.

14. The input v S is a sine wave from a function generator with a peak amplitude of 5 Volts and

frequency of 100 Hertz.

15. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate

the scales that were used) of the report and ask the question.

16. Determine VIL, VIH, VOL, and VOH for the VTC displayed on the oscilloscope and record the values

in the report's questions.

Figure 5
 29

Laboratory Report
Table 1

Measured Measured
Valued Valued
DC Parameters Vs = 0V Vs = 5V
VC
VBC
VBE
VCE
I’B
IB
ISBD
I’C
IC
Graphic 1
 30

4. Record the values of VS corresponding to the VC values given below from the transfer curve

displayed on the oscilloscope.

VC = 4V VS =______V.

VC = 3V VS =______V.

VC = 2V VS =______V.

5. What are the values for :

VIL = _____ VIH = _____

VOL = _____ VOH = _____

6. What are the noise margins for the Gate?

NMH = ____________

NML = ____________

7. Compare this experiment’s results with experiment one’s result.

 3
31

EXP
PERIMEN
NT 04

NMO
OS Invertter

Objeectives
1.. Design and analyze an NMMOS Inverter.
2.. Determine the
t voltage traansfer characteeristic (VTC) ofo NMOS inverrter
3.. Calculate an
nd measure thee propagation delays
d of the NMOS
N inverter.

Required Equ
uipments
• Oscilloscop
pe
• Power suppply
• Function geenerator
• Digital Mulltimeter
• Bread-Boarrd o Protoboardd

Required Parts list

• 10 KΩ ¼-wwatt Potentiomeeter
• 100 nF capaacitor.
• NMOS

Back
kground
A MOSFE ET can be usedu to achieve logic
inversion in the sam me fashion as the BJT inveerter. The
generaalized NMOS inverter is shhown in Figurre 1. The
load device
d may be a resistor, likke that used inn the BJT
inverteer, but in an actual MOSFET inverter a better
choicee for a load is another MOS SFET. The inpuut to this
inverteer is applied directly
d to the gate. Hence, the input
voltagge is equal to th
he gate to sourcce voltage
VIN = VGS

No input resistor
r is needed to limit the t input
currennt since the gate
g current IGI of a MOSFET is
essenttially Zero. Thee output is takeen at the drain, and thus

VOUT = VDS

Note that the voltage VL across the load in

Figuree 1 can be dirrectly expresseed as a functioon of the
outputt as follows

VL = VL(VOUT) = VDD - VOUT

Also, since the input current is negligible, the current though the loaad is equal to the
t drain currennt
througgh the channel of the MOSFE ET

IL = ID
 3
32

These relatiions between thhe voltages andd currents of thhe inverting NM

MOS and the load device aree
used too determine the VTC and pow wer dissipationn for NMOS.

Figure 2 shhows the NMOS inverter withh resistive loadd, RL. The inpuut to the invertter is at the gaate
of the N-channel ou utput transistor NO and VIN= VGS. The outpuut is at the draain and VOUT = VDS = VDD - IL
RL. For VIN < VT, NO is cutoff andd does not condduct drain currrent. Since the resistor currennt is equal to thhe
drain current,
c with VIN < VT, IRL = ID (OFF) = 0 annd the output is
i VOUT = VDD.

As the inpuut in increased slightly above the threshold voltage, NO beegins to conducct. At this poinnt,
only a small current flows and the drain voltage is i slightly less than VDD. As long as VDS ≥ VGS – VT NO is
operatting in the satu
uration region. With
W further inncrease of the input,
i a larger drain current conducts
c and thhe
outputt voltage contin nues to fall. Thhe analytical foorm of the VTC C can be foundd by equating the
t drain currennt
with thhe resistor currrent to obtain

ID (sat) =IRL
R
or
k
(VGSS − VT )2 = VDD − VDS
2 RL

g VGS = VIN annd VDS = VOUT yields

Substituting y

D − VOUT
k
(VINN − VT )2 = VDD
2 RL
Solving for VOUT, we havee
kR L
VOUT = − (VIN − VT )2 + VDD
2
As VIN is fuurther increaseed, ID increasess and the voltaage drop acrosss RL can becoome sufficient to
t
reducee the drain voltage such that VDS ≤ VGS – VT. Under this condition NO operates in thhe linear regionn.
The VTC
V of the resisstor loaded NM
MOS inverter has
h the form shhown in Figure 3.
 33

Propagation Delay

MOS logic families have the lowest power dissipation per gate of any of the logic families. This is
because of the large values of MOSFET resistance and consequently small current levels.

An NMOS gate dissipates power in the same manner form as the BJT gates. That is, the power
dissipated is given by the product of the power supply voltage and average current for a NMOS inverter

I DD (OH ) + I DD (OL)
PDD = VDD
2
Significant additional power dissipation also occurs for NMOS families driving switching from
one logic state to another. An expression for the MOS power dissipation during transient switching, called
the dynamic power dissipation, is given by

PD = C L vVDD
2

where CL is the total capacitance at the output of the gate and v is the frequency at which the gate is
switched.

Since the gate terminal is always an input terminal and the gate sinks zero current for all input
voltages fan-out for MOS families is unlimited. This is true for all load devices including a P-channel
MOSFET as is the case for the CMOS inverter. Thus, the fan-out based upon current limitations is infinite
for all NMOS gates. The maximum fan-out is restricted, however, by the maximum propagation delay
tolerable.

Resistor Loaded NMOS Inverter Dynamic Response

 3
34

A capacitannce is present between

b every pair of terminnals for a MOS
SFET. The gatte capacitance is
the doominant capacittance and can be
b evaluated as
a the approxim mated sum of thhe gate-source,, gate-drain, annd
gate-bbody capacitancce.

The total gate

g capacitancce is the inputt capacitance between the gate
g and grounnd of a resistoor
loadedd NMOS inverrter. When the input logic staate to a resistorr loaded NMOOS inverter is switched
s low-too-
high or
o high-to-low w, this input (ggate) capacitannce must be charge or disccharged, depennding upon thhe
directiion of the input change.

Load Capacitancee on a Ressistor Loaded

d
NMOS Inverter

When onee resistor looaded NMOS S

inverteer drives othher resistor loaded
l NMOS S
inverteers, the inputt capacitance of each loadd
inverteer must bee charged or dischargee
simulttaneously. A lo
oad capacitancce on a resistor
loadedd NMOS invertter is shown inn Figure 4.

The dynam mic response of a resistor

loadedd NMOS inverrter is determinned consideringg
this caapacitance load
d.
 35

Output High-to-Low Transition

The transient characteristics of interest during the Output High-to-Low Transition are the fall time
τf and the High-to-Low propagation time τPHL.
The fall time τf and the High-to-Low propagation time τPHL are expressed as

C L ⎡ 2(VT + 0.1VOL − 0.1VDD ) 1 ⎛ 1.9VDD − 2VT − 0.9VOL ⎞⎤

τf = ⎢ + ' ln⎜⎜ ⎟⎟⎥
W ⎣ k (V DD − VT )
' 2
k (VDD − VT ) ⎝ 0.1VDD + 0.9VOL ⎠⎦
L
and

2C LVT CL ⎛ 1.5VDD − 2VT − 0.5VOL ⎞

τ PHL = + ln⎜⎜ ⎟⎟
k (VDD − VT ) k ' (VDD − VT ) ⎝ 0.5VDD − 0.5VOL
' 2
⎠

As with τf, τPHL is directly proportional to the load capacitance and inversely proportional to
W/L.

Output Low -to-High Transition

The analysis of the output low-to-high transition involves the charging of the output load
capacitance through the load resistor RL of the inverter. The transient characteristics of interest during the
output low-to-high transition are the rise time τr and the low-to-high propagation time τPLH.

The rise time τr and the low-to-High propagation time τPLH are expressed as

⎡ 0.9V DD − 0.9VOL ⎤
τ r = R L C L ln ⎢ ⎥
⎣ 0.1V DD − 0.1VOL ⎦

and

τ PLH = R L C L ln(2)
 3
36

Pre--Laboratory
NMO
OS Inverteer Propagationn Delay
Simulate th he NMOS invverters using PSPICE
P to determine the voltage transfeer characteristtic
(VTC)) and calculatee and measure the propagatioon delays. Thee NMOS invertters are shownn in Figures 5, 6
and 7.

Circuiit description and

a specific parameters
 37

The input voltage VIN is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time

(TF) equal to 2 ηS, delay time (TD) equal to 0 ηS, a duration (PW) of 500 ηS and a period (PER) of

approximately 1 μS. VGG = 10V.

The transistors used in the simulation will be a NMOS with the following model parameters for both

Netlist and Schematic circuit.

.MODEL parameters for the NMOS are:

(VTO=1 KP = 20u GAMMA = 0.37 PHI = 0.6 CBD = 3.1E-15 CBS=3.1E-15)
M1 (W=10u L =5u)
M2 (W=5u L =20u)

Pre – Laboratory Procedure

11. Use PSPICE to get the DC operating point for the circuits shown in Figures 5, 6, and 7 and

complete the Table 1 of the pre-laboratory report.

12. Use PSPICE to get the transient response for the circuit shown in Figure 5.

13. Plot both VIN and VDS as outputs superimposed on the same plot.

14. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's

questions.

15. Determine τPHL and τPLH for the simulation and record the values in the report's questions.

16. Print the plot.

17. Vary W/L ratio of the NMOS M1 for the circuit shown in Figure 5 and repeat step 2 to 5

18. Vary RL for the circuit shown in Figure 5 and repeat step 2 to 5
 38

Pre – Laboratory Report

Table 1

Measured Measured
NMOS Inverters DC Parameters Valued Valued
VIN=0V VIN=5V
ID
Resistor Load
VDS(OUT)

ID
Saturated Load
VDS(OUT)

ID
Linear Load
VDS(OUT)

7. What are the values for :

VIL =_____ VIH = _____

VOL = _____ VOH = _____

8. Calculate τPLH and τPHL for the simulation.

τPLH = __________________ τPHL = _________

9. What is the propagation delay of the gate?

τP = _________

10. Make a comparative analysis of the table 1 data and explain yours reasoning.
 3
39

Labboratory Procedure
P e
NMO
OS Inverteer Voltage Transfer
T C
Characteris
stic
1. Connecct the NMOS inverter shown in figure 5.

2. Using the DC poweer supply, varyy the input voltage

from 0 to 5 V andd use the diggital Multimeter to

determ
mine the voltagge at the outpuut, and measuure the

drain current,
c recordding your values in table 1 of the

report.

3. he 10 kΩ potenntiometer and record the vallues in

Vary th

Table 1 of the report.

4. Replace the DC input voltage VINN with a sine wave

from a function gennerator with peak amplitudee of 5

Volts and
a frequency of
o 100 Hertz.

5. Use thee Oscilloscope with the Y-axxis sensitivity set

s to 1 Volt/diivision and the X-axis sensitiivity at

0.5 Volts/division. Adjust the X zerro reference too the screen cennter and the Y reference beloow the

center.

6. Draw a rough sketch of the charactteristic displayyed on the osciilloscope in thee Graphic 1(Inndicate

ales that were used) of the report.

the sca r Commeent on the impportant points of
o the graph suuch as

VOH, VOL
O , VM, noise margins,
m etc.

7. Attach a load capacitaance of 100 nF

F to the output node.

8. Apply a 200 Hz 0 to 5 volt square wave to the innput of the inveerter. Set the DC
D offset to bee 2.5V.

Use thee oscilloscope to plot vIN andd vOUT. Determine the propaggation delays, τPHL and τPLH, of the

inverter.

9. Draw a rough sketch of the charactteristic displayyed on the osciilloscope in thee Graphic 2(Inndicate

the sca
ales that were used)
u t graph such as
of the repport. Commentt on the importtant points of the τf,
τr, τPHHL and τPLH.
 40

Laboratory Report

Table 1

Measured Measured
Potentiometer
DC Parameters Valued Valued
Position VIN=0V VIN=5V
ID
1KΩ
VDS
ID
5 KΩ
VDS
ID
10KΩ
VDS
Graphic 1
 41

Graphic 2

8. Record the values of VIN corresponding to the VDS values given below from the transfer curve

displayed on the oscilloscope.

VDS = 4V VIN =______V.

VDS = 3V VIN =______V.

VDS = 2V VIN =______V.

9. What are the values for :

VIL = _____ VIH = _____

VOL = _____ VOH = _____

10. What are the noise margins for the Gate?

NMH = ____________

NML = ____________
 42

EXPERIMENT 05

CMOS Technology

Objectives
4. Familiarize with the CMOS structure.
5. Design and analyze a CMOS Inverter.
6. Determine the voltage transfer characteristic (VTC) of CMOS inverter
7. Calculate and measure the propagation delays of the CMOS inverter.

Required Equipments
• Oscilloscope
• Power supply
• Function generator
• Digital Multimeter
• Bread-Board o Protoboard

Required Parts list

• .22 nF capacitor.
• 22 nF capacitor.
• NMOS and PMOS transistors

Background
A CMOS inverter is an ingenious circuit which is built forms a pair of NMOS and PMOS transistors
operating as complementary switches as illustrated in Figure3.2. The main advantage of a CMOS inverter
over many other solutions is that it is built exclusively out of transistors operating as switches, without any
other passive elements like resistors or capacitors.

From Figure 1 note that the PMOS (pull-up transistor) is connected between VDD and the output node,
VOUT, whereas the NMOS (pull - down
transistor) is connected between the
output node, VOUT, and the ground,
GND.

The principle of operation is as follows

(refer also to the right part of Figure 2).

• For small values of the input

voltage, VIN, the NMOS
transistor is switched off,
whereas the pull-up PMOS
transistor is switched on and
connects the output mode to
VDD.
• For large values of the input voltage, VIN, the PMOS transistor is switched off, whereas the pull-
down NMOS transistor is switched on and connects the output mode to GND = 0V.
 43

A better inside into the working of the CMOS inverter can be obtain by
looking at its transfer and current characteristics presented in Figure 2.

The transfer characteristic presents the output voltage vOUT versus the input voltage vIN. Note that when
the input voltage increases from 0V to 5V the output voltage decreases from 5V to 0V.

The current characteristic presents the current flowing through the transistors between VDD and GND
also versus the input voltage VIN.

From the above characteristics we can observe the existence of three basic regions of operations denoted 1,
2, 3 in Figure 2.

• In region 1 when 0 _ VIN < VTN

The NMOS transistor is cut off, the PMOS switch is closed and VOUT = VDD iD = 0

• In region 3 when VIN > VDD - VTN

The PMOS transistor is cut off, the NMOS switch is closed and VOUT = 0 and iD=0

The fact that in regions 1 and 3 no current flows between VDD and GND, is very attractive because there is
no power dissipation at this stages. This very fact is the reason that all digital circuitry is now build in the
CMOS technology.

In region 2 when VN < VIN < VP

ƒ The transistor remains only for a short period of time, when the input voltage switches between VL
and VH.

ƒ In this region there is non-zero current flowing between VDD and GND, and some power
dissipation, which is converted into heat.

Note that the same current flows through the PMOS and NMOS transistors, that is,
 44

IDp = IDn

Transient properties of the CMOS inverter

In this section we will investigate basic transient properties of the CMOS inverter, that is, its dynamic
behavior during switching the input signals from low-to-high or high-to-low voltages and associated power
dissipation.

Propagation delay
Let us consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in
Figure 3. Basic characterization of the dynamic behavior of an inverter is given by its two propagation
delay times, τHL and τLH as illustrated in Figure 3. Note that these propagation times are specified with
respect to the mid voltage V0.5:

Figure 3.7: Input/output waveforms for a CMOS inverter.

The propagation delay times, τHL (τLH) specifies the input-to-output time delay during the high-to-low (low-
to-high) transition of the output voltage.

Often, it is convenient to refer to the average propagation delay, τp which specifies the average time
required for the input signal to propagate through the inverter:

Similarly, we can define the fall time, τF , and the rise time, τR, as the time required for the output voltage
to change between V90% and V10% .

Where V10% = VL + 0.1(VH − VL) , and V90% = VL + 0.9(VH − VL)

 45

The physical reason for the propagation time delay is the existence of the parasitic capacitances
associated with a MOS transistor. We can combine all such capacitances into an equivalent load
capacitance, Cld, as illustrated in Figure 4.

As illustrated by the voltage and current characteristics from Figure 2, during transition between low and
high input voltages, there is a current flowing through the transistors forming the inverter. A part of this
current charges and discharges the load capacitance which is responsible for propagation delays.

If we approximate the current flowing through the load capacitance by its average value, Iavg, then the
propagation time can be estimated as:

where ΔV indicates the voltage change across the load capacitance, that is, the change of the output
voltage.

The value of the load capacitance of the inverter without the interconnecting lumped capacitance is in the
order of 0.01pF = 10fF. We can estimate that the propagation time is in the order of τp = 100ps = 0.1ns

Pre-Laboratory
CMOS Inverter Propagation Delay
Simulate the CMOS inverters using PSPICE to determine the voltage transfer characteristic
(VTC) and calculate and measure the propagation delays. The CMOS inverter is shown in Figure 5.
 4
46

Figurre 5: CMOS Invverter

Circuiit description and

a specific parameters

The input voltage

v VIN is a PULSE waveeform with an amplitude
a of 5V,
5 the rise tim
me (TR) and faall time

(TF) equal
e to 2 ηS
S, delay time (TD) equal too 0 ηS, a durration (PW) of 500 ηS andd a period (PE
ER) of

approxximately 1 μS.

The transisstors used in the simulation will be a NMOS

N and PMOS
P with thhe following model

param
meters for both Netlist
N and Schhematic circuitt.

Pre – Laborato
ory Proceduure

19. Use PS
SPICE to get the
t DC operatiing point for the
t circuits shoown in Figuress 5 and compleete the

Table 1 of the pre-labboratory reportt.

20. Use PS
SPICE to get thhe transient ressponse for the circuit
c shown in
i Figure 5.

21. Plot bo
oth VIN and VOUT
O
as outputs superimposed
s o the same ploot.
on

22. Determ
mine VIL, VIH, VOL, and VOH for the sim
mulation and record the vaalues in the report's

questio
ons.

mine τPHL and τPLH for the sim

23. Determ mulation and record
r the valuues in the reporrt's questions.

24. Print th
he plot.
 47

25. Vary W/L ratio of the MOSFETs for the circuit shown in Figure 5 and repeat step 2 to 5

26. Vary CL for the circuit shown in Figure 5 and repeat step 2 to 5
 48

Pre – Laboratory Report

Table 1

Measured Measured
Circuit DC Parameters Valued Valued
VIN=0V VIN=5V
ID

VOUT
CMOS Inverter
VOUT

11. What are the values for :

VIL =_____ VIH = _____

VOL = _____ VOH = _____

12. Calculate τPLH and τPHL for the simulation.

τPLH = __________________ τPHL = _________

13. What is the propagation delay of the gate?

τP = _________
 4
49

Labboratory Procedure
P e
CMO
OS Inverteer Voltage Transfer
T C
Characteris
stic
10. Connecct the CMOS innverter shown in
figure 6.
6

11. Using the

t DC power supply, vary the
t

input voltage
v from 0 to 5 V and use
u

gital Multimetter to determine

the dig

the vo
oltage at thhe output, annd

measurre the drain cuurrent, recordinng

your vaalues in table 1 of the report.

12. Replace the DC inpput voltage VIN

with a sine wave from

f a functioon

generattor with peak amplitude off 5

Volts and
a frequency of
o 100 Hertz.

13. Use thee Oscilloscope with the Y-axxis sensitivity set

s to 1 Volt/diivision and the X-axis sensitiivity at

0.5 Volts/division. Adjust the X zerro reference too the screen cennter and the Y reference beloow the

center.

14. Draw a rough sketch of the charactteristic displayyed on the osciilloscope in thee Graphic 1(Inndicate

ales that were used) of the report.

the sca r Commeent on the impportant points of
o the graph suuch as

VOH, VOL
O , VM, noise margins,
m etc.

15. Attach a load capacitaance of 22 nF to

t the output node.
n

16. Apply a 200 Hz 0 to 5 volt square wave to the innput of the inveerter. Set the DC
D offset to bee 2.5V.

Use thee oscilloscope to plot vIN andd vOUT. Determine the propaggation delays, τPHL and τPLH, of the

inverter.
 50

17. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 2(Indicate

the scales that were used) of the report. Comment on the important points of the graph such as τf,
τr, τPHL and τPLH.
 51

Laboratory Report

Table 1

Measured Measured
CL DC Parameters Valued Valued
VIN=0V VIN=5V
ID
.22nF
VOUT
ID
22nF
VOUT

Graphic 1
 52

Graphic 2

11. Record the values of VIN corresponding to the VOUT values given below from the transfer curve

displayed on the oscilloscope.

VOUT = 4V VIN =______V.

VOUT = 3V VIN =______V.

VOUT = 2V VIN =______V.

12. What are the values for :

VIL = _____ VIH = _____

VOL = _____ VOH = _____

13. What are the noise margins for the Gate?

NMH = ____________

NML = ____________
 53

EXPERIMENT 06

Logic Interfacing

Objectives
8. Familiarize with TTL open-collector devices, three state outputs and transceivers.
9. Design logic interface between different logic families.

Required Equipments
• Digital Multi-meter
• Digit-lab
• Bread-Board o Protoboard

Required Parts list

• 10 KΩ ¼-watt Potentiometer
• 470Ω
• TTL Open-collector NAND Gate 7401
• TTL NAND Gate 7400
• 74244 Three stage buffer gate
• 2 LEDs

Background
Situation often arise where many components in digital system must share a common path to be
able to transfer data to one another. To reduce the number of interconnections, a small set of shared lines
called bus may be used. In general, outputs from different devices cannot be simultaneously present on the
bus. Consequently, for proper operation, that is, to prevent bus contention, only one of the devices
connected to a shared bus can place information on the bus at any time. TTL open-collector devices permit
the simultaneous connection of the outputs of two or more devices to form a bus.

In many applications such as bus-organized digital systems where various outputs must be
ANDed, using TTL gates with totem-pole outputs would require an AND gate with as many input lines as
there are signals to be ANDed.

Additional logic is created when the outputs of two or more open-collector gates are tied together,
as in Figure 1. This scheme is called the wired-AND and is used to save logic gates in comparison with
other methods.
 54

It is not possible to interconnect

TTL gates with totem-pole output stages
in the configuration. Figure 2 depicts the
high level current path when the outputs
of totem-pole gates are tied together. Gate
A dissipate a large amount of power, and
Q3B is required to sink a current which
may exceed its guaranteed 16mA sink
capacity.

Although the main application of

the open collector gate is to allow the
formation of the wire-AND, it is also
useful for driving an individual load like
an LED or relay. The output stage for the
two-input open-collector NAND gate
7401 consists solely of the common-
emitter transistor without even a collector
resistance. This gate, when supplied with
a proper load resistor RL, may be
paralleled with other similar TTL gates.
At the same time, it will drive from one to
nine standard loads of its own series.
When no other open-collector gates are
tied, it may be used to drive ten loads.
Their main disadvantage is that these
gates are inherently slowly and more
subject to noise than their totem-pole
counterpart. The pull-up resistor bias can
be raised to any voltage within the
breakdown voltage of the driver transistor
 55

to enable interfacing to a system employing voltage swings, like a CMOS.

To determine the value of the external pull-up resistor, we should find the upper and lower limits
of the range of values the resistor can take. A maximum value is found which will ensure that sufficient
source current to the loads and off current through paralleled outputs will be available when the output is
logical 1. Therefore, the total leakage current determines the maximum value of RL when all driving
transistors are off, as shown in Figure 4. When Vo is high so that the drivers are off, the voltage drop across
RL must be less than

VRL(max) = VCC – VOH(min)

On the other hand, the total

current through RL is the sum of the
load current IIH and the leakage
current IOH through each driver.
Therefore,

IRL = ηIOH + NIIH

Where η is the number of gates

wired-AND connected, and N is the
number of standard loads. Note that
IOH is into the output terminal and
hence positive. Using equations 1
and 2, we find

RL(max) = VRL(max)/IRL

RL(max) = (VCC – VOH(min))/ (ηIOH +

NIIH)

A minimum value for the

pull-up resistor is established when
Vo is logical 0, so that the current
through RL and the total sinking
current from the load gates do not
cause the output voltage to rise
above VOL(max) even if only one driving gate is sinking all the current. Therefore, the current must be
limited to the recommended maximum IOL, which will ensure that the low-level output voltage will be
below VOL(max). Since part of IOL will be supplied from the loads, the amount of current that can be
allowed through RL will be reduced. Hence, neglecting the leakage currents of the turned-off drivers, we
have
RL(min) = VRL(min)/IRL

RL(min) = (VCC – VOL(max))/ (IOL(max) – N|IIL|)

Logical 0 circuit conditions to calculate RL(min) are illustrated in Figure 5. Table 1 provides the
electrical characteristics of the 7401 open-collector NAND gate.
 56

Table1: Electrical Characteristics of the two-Input NAND Gate 7401

VOH (min) IOH (min) τPLH

2.4V 250uA 35ns
VIH (min) IIH (min) τPHL
2V 40uA 8ns
VOL (max) IOL (max) CL
.4V 16mA 15pF
VIL (max) IIL (max) 4kΩ for τPLH
RL
.8V -1.6mA
400Ω for τPHL
 57

Three-State Outputs
Another useful variant of TTL that can solve the problem of driving a common bus line by two or
more logic circuits is the three-state output arrangement shown in Figure 6. The term tri-state is also used.
However, it is registered trademark of National Semiconductor Corporation, which introduced this design
concept in 1970.

Figure 6

By combining the high-speed advantage of the totem-pole output with the advantages of an open-
collector output, the three-state gates enable the connection of a number of gates to a common output line
or bus. In addition to a totem-pole output, these gates have another terminal, called the output enable,
which permits the device to function normally or the output signal to be disconnected from the rest of the
circuit by going into a third state in which both output transistors are turned off, resulting in an extremely
high output impedance. Therefore, a disabled gate can be assumed to have an open circuit in its output line,
so that the high impedance state may be equated to the voltage level of a conductor that has no sources
connected to it, that is, it is floating.

The two most frequently used three-state ICs in the standard TTL logic subfamily are the 74125
and 74126 quadruple-bus buffers with independent output controls. Both are non-inverting buffers, but the
former’s output for the 74125 is enabled by a logical 0 while the 74126 is enabled by an active high signal.

Three-State CMOS Buffers

The CMOS three-state output buffer

has logic elements in the gate connections to
each of the transistors in the final inverter, so
that both may be turned off under the control of
an enable function. Figure 7 illustrates the logic
diagram of such a buffer with active low-enable
input. Note that additional inverters are added as
buffers or to optimize timing. The truth table of
the CMOS Buffers is shown in table 2.
 58

G' A VGP VGN Y

0 0 0 0 1
0 1 1 1 0
1 0 1 0 Z
1 1 1 0 Z
Table 2: Truth table
 59

Pre-Laboratory
TTL Open-Collector Outputs
 60

Pre – Laboratory Procedure

27. Simulate the circuit shows in Figure 8 using PSPICE. Use 7401 and 7400 TTL Open-
Collector NAND and standard NAND respectively.
28. Sweep the value of the pull-up resistor and determine the value maximum and minimum for
optimum performance and complete the Table 1 of the pre-laboratory report.
29. Connect the circuit shows in Figure 9 using PSPICE and determine how many TTL inputs
can drive.
30. Simulate the circuit of Figure 10 using PSPICE and find the DC operating point and complete
the Table 2 of the pre-laboratory report.
31. Simulate the circuit shows in Figure 11 using PSPICE and prove the truth table of the circuit.

Pre – Laboratory Report

Table 1

TTL 7401
Figure 8
RL(Max) RL(Min) IRL(Max) IRL(Min)
DC parameters

How many TTL inputs can drive the circuit of Figure 7

Table 2

Figure 10 VRL
(High) VOL IOL
DC parameters
 61

Laboratory Procedure
Open-Collector TTL Outputs
18. Connect the circuit of Figure 12 with the 7401 and 7400 TTL Open-Collector NAND and standard
NAND respectively. Vcc = +5V

19. Add load to the output in order to

determine the fan-out of the gate. Use the digital

Multimeter to determine the output voltage and the

currents in the circuit when you are adding a gate and

record your values in table 1 of the report.

20. Co
nnect the circuit
of Figure 13
using 7401 and
7400 TTL NAND and AND gate respectively with high
input voltages and record your values in Table 1 of the
report. Vcc = +5V
21. Vary the 10 kΩ potentiometer and record the values in
Table 1 of the report.
22. Using the Digit lab DC switch to vary the input voltage
from 0 to 5 V and use the digital Multimeter to determine
the voltage at the output, and the currents in the circuit
recording your values in table 1 of the report.
23. Connect the circuit shown in Figure 14.
24. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter
to determine the voltage at the output, and the
currents in the circuit recording your values in table
3 of the report.
25. Change the 7401 TTL Open-Collector NAND by the
7400 standard NAND and repeat step 7.
 62

26. Connect the circuit shown in Figure 15.

27. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter to
determine the voltage at the output, and the currents in the
circuit recording your values in table 4 of the report.
 63

Laboratory Report

Table 1

Loads
VOL VOH IOH IIH IOL IIL
1
2
3
4
5
Table 2

DC RL
Parameters Value VOL VOH IOH IIH IOL IIL
IRL(OH)=
410Ω
IRL(OL)=
IRL(OH)=
1kΩ
IRL(OL)=
IRL(OH)=
2.3 kΩ
IRL(OL)=
IRL(OH)=
5 kΩ
IRL(OL)=
 64

Table 3

Figure 14 VRL
(High) VOL IOL VOH IOH
7401

7400
Table 4

Figure 15 VRL
(High) VOL IOL VOH IOH
7400

Compare the results obtain in table 3 and table 4 and explain your conclusions

Conclusions
 65

EXPERIMENT 07

Regenerative circuits
Objectives
1. Wire and observe the operation of an R-S flip-flop.
2. Wire and observe the operation of a Master-Slave J-K flip-flop level and edge triggered.
3. Compare the wave shaping action of a regular TTL IC with a Schmitt trigger IC.

Required Equipments
• Digit-lab
• Bread-Board o Protoboard
• Function Generator
• Oscilloscope

Required Parts list

• 7402 2-input NOR gate IC
• 7404 inverter TTL IC
• 7414 Schmitt trigger inverter TTL IC
• 74104 or 74105 J-K Master-Slave flip flop
• 74109 Dual J-K Positive-Edge-Triggered Flip-Flop with Clear and Preset
• 74112 Dual J-K Negative-Edge-Triggered Flip-Flop with Clear and Preset
• 74279 S-R flip flop with NAND
• 3 LEDs
• (2) 150Ohms resistors
Background

Multivibrators are regenerative circuits that are used used to implement a variety of
simple two-state systems such as oscillators, timers and flip-flops. The most common
form is the astable or oscillating type, which generates a square wave - the high level
of harmonics in its output is what gives the multivibrator its common name.

There are three types of multivibrator circuit:

• Astable, in which the circuit is not stable in either state - it continuously oscillates from one state
to the other.
• Monostable, in which one of the states is stable, but the other is not - the circuit will flip into the
unstable state for a determined period, but will eventually return to the stable state. Such a circuit
is useful for creating a timing period of fixed duration in response to some external event. This
circuit is also known as a one shot. A common application is in eliminating switch bounce.
• Bistable, in which the circuit will remain in either state indefinitely. The circuit can be flipped
from one state to the other by an external event or trigger. Such a circuit is important as the
fundamental building block of a register or memory device. This circuit is also known as a flip-
flop. A similar circuit is a Schmitt trigger.

In electronics and digital circuits, the flip-flop or bistable multivibrator is a pulsed digital circuit
capable of serving as a one-bit memory. A flip-flop typically includes zero, one, or two input signals;
a clock signal; and an output signal, though many commercial flip-flops additionally provide
 66

the complement of the output signal. Some flip-flops include a clear input signal, which resets the current
output. Because flip-flops are implemented as integrated circuit chips, they also require power and ground
connections.

Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based
upon the values of the input signals and the characteristic equation of the flip-flop. Strobing here means
changing the clock; some flip-flops change output on the rising edge of the clock, and other change on the
falling edge.

Flip-flops can be split into two main categories: level-triggered and edge-triggered. They can
further be divided into four types that have found common applicability in clocked sequential systems:
these are called the T ("toggle") flip-flop, the SR ("set-reset") flip-flop, the JK flip-flop, and the D ("Data")
flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which
derives the "next" (i.e., after the next clock pulse) output, Q(next), in terms of the input signal(s) and/or the
current output, Q.

Level-triggered flip-flops respond whenever a signal level changes.

Set-reset flip-flops (SR flip-flops)

The SR (set-reset) flip-flop has two inputs: S (set) and R (reset). If R is active, the output goes to
zero. If S is active, the output goes to one. If neither is activated, the previous state is maintained. Both
inputs should not be activated simultaneously; however, if they are, the typical response is for both the
inverted and non inverted outputs to have the same level.

The behavior of an SR flip-flop can be written in the form of a truth table:

NOR NAND
S R Q Q(next) S R Q Q(next)
0 0 Q Q(next) 0 0 undetermine
0 1 1 0 0 1 x 0
1 0 0 1 1 0 x 1
1 1 Undetermined 1 1 Latch Latch

Truth table for an SR flip flop with NOR and NAND gates

We can implement a SR flip-flop with a pair of either NAND or NOR gates. The NOR version is
conceptually easier as it has active high inputs. However, the NAND version is more widely known and
used, as NAND gates were cheaper in transistor-transistor logic.

We can also easily add an enable input. If this is implemented in the same gates as the flip-flop,
then it serves to further invert the inputs - meaning a NAND based device will now have active high inputs.
This input may be regarded as a clock but the flip-flop is still unsuitable for sequential design. When the
clock goes high, the signal will propagate through all flip-flops, not just from one to the next.
 6
67

SR
R flip-flops circcuit diagrams and
a the symbolls for an un-cloocked SR flip-fflop

A clocked SR fliip-flop and thee

ssymbol for a cllocked SR flip--
flop

Eddge-triggered
d flip-flops only
o change state on a particular
p edgge (rising, faalling, or verry
occassionally both
h directions) of a designaated clock siignal.

JK fllip-flop

Thhe JK flip-flop augmentss the behavior of the SR R flip-flop byy interpretingg the S = R =
1 conndition as a "flip"
" commaand. Specificcally, the coombination J = 1, K = 0 is i a commannd
to sett the flip-flop; the combbination J = 0,
0 K = 1 is a command to reset the flip-flop; annd
the coombination J = K = 1 iss a commandd to toggle the t flip-flop,, i.e., changee its output to
t
the loogical compllement of itss current valuue. Setting J = K = 0 ressults in a D-ttype flip-flopp.
The JKJ flip-flop is therefore a universal flip-flop,
f beccause it can be configured to work as a
an SRR flip-flop, a D flip-flop or a T flip-fflop.

The syymbol for a cloccked J-K flip-fflop

A circuit sy
ymbol for a JKK flip-flop, wheere > is the cloock input, J andd K
are datta inputs, Q is the stored dataa output, and Q'
Q is the inversee of Q.

The charaacteristic equuation of thee JK flip-flopp is:

and thhe correspon

nding truth table is:

J K Q Q(neext)
0 0 Latch Latcch
0 1 1 0
1 0 0 1
1 1 0 1
1 1 1 0
 68

SCHMITT TRIGGER

In electronics, a Schmitt (or Schmidt) trigger is a comparator circuit that incorporates positive
feedback.

When the input is higher than a certain chosen threshold, the output is high; when the input is
below another (lower) chosen threshold, the output is low; when the input is between the two, the output
retains its value. The trigger is so named because the output retains its value until the input changes
sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt
trigger has some memory.

The benefit of a Schmitt trigger over a circuit with an only single input threshold is greater
stability (noise immunity). With only one input threshold, a noisy input signal near that threshold could
cause the output to switch rapidly back and forth from noise alone. A noisy Schmitt Trigger input signal
near one threshold can cause only one switch in output value, after which it would have to move to the
other threshold in order to cause another switch.

The Schmitt trigger was invented by US scientist Otto H. Schmitt.

The symbol for Schmitt triggers in circuit diagrams is a triangle with a

hysteresis symbol.

Pre-Laboratory
Regenerative circuits
Wire and test one J-K flip flop from the CMOS 4027 dual J-K flip flop IC. Observe and record your
values in table 1.

Pre – Laboratory Report

Table 1

Inputs
Outputs
Mode of operation Asynchronous Synchronous
PS CLR CLK J K Q Q'
Asynchronous Set 0 1 x x x
Asynchronous reset 1 0 x x x
Prohibited 0 0 x x x 1 1
Hold 1 1 ↑ 0 0 No change
Reset 1 1 ↑ 0 1
Set 1 1 ↑ 1 0
Toggle 1 1 ↑ 1 1
Preset Clear Clock Data Data

Laboratory Procedure
Regenerative circuits
1. Wire the logic circuit of the R-S flip-flop shown in Figure. Wire outputs Q and Q’ to two LEDs.
 6
69

2.. Operate thee input switches R and S as shhown in the truuth table in Tabble 2. Observe and record thee
results in th
he Q and Q’ columns.
3.. In the right column of Tabble 1, write thee name of the condition
c of thee outputs. Use the term
“Hold,” “Seet,” or “reset.”
4.. Operate thee input switches R and S as shhown in the truuth table in Tabble 3 using the 74279 R-S flipp-
flop and reccord the resultss in the Q and Q’
Q columns. Wire
W outputs Q and Q’ to two LEDs.

5.. In the right column of Tabble 2, write thee name of the condition
c of thee outputs. Use the term
“Hold,” “Seet,” or “reset.”
6.. Construct th
he circuit of thhe clocked R-S flip flop with NAND.
N Wire outputs
o Q and Q’ to two
LEDs.

7.. Operate thee input switches R and S as shhown in the truuth table in Tabble 4. Observe and record thee
results in th
he Q and Q’ columns.
8.. Insert the 74
4LS112 IC intoo the mountingg board.
9.. Wire the sy
ynchronous inputs PS and CL
LR to two switcches. Wire the
asynchrono
ous inputs J andd K to switchess and the CLK input to a singgle-
pulse clock. Wire outputs Q and Q’ to tw
wo LEDs.
 70

10. Operate the asynchronous inputs PS and CLR and record the results in Table 5.
11. In the right-hand column of Table 5 write the condition of the output. Choices are listed.
12. Disable the asynchronous inputs (PS and CLR to 1).
13. Operate the synchronous inputs J, K and CLK of the 74LS112 IC according to the truth table in
Table 6. Observe and record the results in column Q and Q’.
14. In the right-hand column of Table 6 write the condition of the output. Choices are listed.
15. Insert the 7404 and 7414 ICs into the mounting board and wire the circuits shown in the Figure.

16. Set Vin with the function generator. Set the function generator to sine wave. Set the frequency
from 50 to 200 Hz. Adjust the function generator voltage to 2 to 4 V p-p.

17. Use the Oscilloscope to observe the output waveforms for the circuits. Draw a rough sketch of the

characteristic displayed on the oscilloscope in the Graphic 1 and 2(Indicate the scales that were used)

of the report.
 71

Laboratory Report
Table 2
NOR
Name of
S R Q Q(next) condition
0 0
0 1
1 0
1 1
Table 3
R-S flip-flop 74279
Name of
S R Q Q(next) condition
0 0
0 1
1 0
1 1
Table 4
Inputs Outputs
Clock Data Before clock pulse After clock pulse
Name of condition
CLK S R Q Q' Q Q'
0 0 0 1
0 1 0 1
1 0 0 1
1 1 0 1 Prohibited
0 0 1 0
0 1 1 0
1 0 1 0
1 1 1 0 Prohibited
Hold, reset, or set
 72

Table 5
Inputs Outputs
Clear Preset Q Q' Name of Condition
0 0 Prohibited
0 1
1 0
1 1
Clear Q to 0
Disable
Preset Q to 1

Table 6
Inputs Outputs
Before clock After clock
Clock Data pulse pulse Name of condition
CLK J K Q Q' Q Q'
↑ 0 0 0 1
↑ 0 1 0 1
↑ 1 0 0 1
↑ 1 1 0 1
↑ 0 0 1 0
↑ 0 1 1 0
↑ 1 0 1 0
↑ 1 1 1 0
PS and CLR=1 Hold, reset, set, or toggle
 73

Graphic 1(7404)

Graphic 2(7414)

Which IC seems to do the best job of converting the sine wave into a sharp square wave?
 7
74

EXP
PERIMEN
NT 08

D\A and A/D converters

Objeectives
4.. To connect an analog-to-ddigital (A/D) ciircuit and perfoorm an A/D coonversion
5.. To calculatee A/D accuracyy and resolutioon
6.. To connect an analog-to-ddigital (D/A) ciircuit and perfoorm an D/A coonversion
7.. To calculatee D/A accuracyy and resolutioon

Required Equ
uipments
• Digit-lab
• Bread-Boarrd o Protoboardd
• Function Generator
• pe
Oscilloscop
• Digital Mulltimeter

Required Parts list

Resistors Integratted Circuits Potenciom
meters Diodes Cappacitors
• 1 KΩ (3) • LM741
L • 10 KΩ
K (2) • Led (2)) • 15 pF
• 2 KΩ (6) • D
DAC0808
• 10 KΩ
• 30 KΩ
• 100 Ω
• 2.5kΩ

Back
kground
Anallog-to-Dig
gital Conveerter

The processs of convertingg an analog volltage to a digitaal coded signall is known as analog-to-digita
a al
converrsion. It is usuaally referred too as A-to-D (A//D) conversionn.

When an an nalog signal iss digitized, thee signal is

converrted to an eq quivalent digiital number at a regular
intervaals, called sam
mple intervals, as
a seen in Figure

Figuure 1: Analog signal

s is samplled at regular inntervals
 75

The typical A/D converter will have eight output lines. Each line is capable of being a logic 1 or 0.
Each binary digit is called a bit –an acronym for binary digit. Thus such an A/D device is called an 8 nit
A/D converter. Now assuming that each of the eight output lines could be a logic 1 or 0, there are 28, or
256, different binary codes which can be represented by the 8-bit A/D converter. Assume an input voltage
of 0V to the A/D converter; its output would be the binary equivalent, or 00000000. For each input voltage
level there will be a specific equivalent binary output on the eight output lines.

Resolution and accuracy

Resolution of an A/D converter is defined as the smallest increment input voltage that can be
determined by the converter. Resolution is primarily a function of the number of output bits. For example,
if the converter has 256 different outputs codes, the input signal is represented by binary numbers from
00000000 to 11111111. If the input ranges from 0 to 5 V, the resolution is
5V
= 0.0195V
256
Thus, the binary output of 00000001 represents 0.0195 V. Likewise, 00000010 represents 0.039
V, and so on. What would be the binary representation of, say, 3.042V? Clearly,
3.042V
= 156
0.0195
which, when converted to binary, is 10011100.

The accuracy of the A/D converter is determined by how closed the actual converter output is to
the theoretical output. For example, if the 8-bit A/D converter had an accuracy expressed as ± 1 least
significant bit (LSB), the accuracy could be expressed as
1 1
accuracy = 8
*100 = *100 = 0.4%
2 256
Digital-to-Analog converter
In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a digital
(usually binary) code to an analog signal (current, voltage or electric charge). Digital-to-analog converters
are the interface between the abstract digital world and the analog real life. Simple switches, a network of
resistors, current sources or capacitors may implement this conversion.

The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers)
into a physical quantity, usually an electrical voltage. Normally the output voltage is a linear function of the
input number. Usually these numbers are updated at uniform sampling intervals and can be thought of as
numbers obtained from a sampling process. These numbers are written to the DAC, sometimes along with a
clock signal that causes each number to be latched in sequence, at which time the DAC output voltage
changes rapidly from the previous value to the value represented by the currently latched number. The
effect of this is that the output voltage is held in time at the current value until the next input number is
latched resulting in a piecewise constant output (Figure 2). This is equivalently a zero-order hold operation
and has an effect on the frequency response of the reconstructed signal.

The fact that practical DACs do not output a sequence of dirac impulses (that, if ideally low-pass
filtered, result in the original signal before sampling) but instead output a sequence of piecewise constant
values or rectangular pulses, means that there is an inherent effect of the zero-order hold on the effective
frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (a 3.9224 dB
loss at the Nyquist frequency). This zero-order hold effect is a consequence of the hold action of the DAC
 7
76

and is not due to thee sample and hold

h that mighht precede a coonventional annalog to digitall converter as is
often misunderstood
m d.

Figure 2: Piecew
wise constant signal
s typical of
o a practical DAC
D output.
 77

Laboratory Procedure
D\A and A/D converters
1. Wire the circuit of the D/A converter as shown in Figure 1.

Figure 1: Digital-to-Analog Converter

2. Operate the input switches as shown in the Table 1. Observe and record the results of the
OPAMP output voltage. The output voltage can be calculated with the standard op-amp
theory.
3. Connect the circuit shown in Figure 2.
4. Apply the digital inputs shown in Table 2. For each input measure the analog output voltage
and record it in the table 2.
5. Wire the circuit of the D/A converter as shown in Figure 3.
6. Vary the potentiometers to change the comparator input voltage.
7. Determine the switches combination to set on the LED indicator. Observe and record the
results of the OPAMP output voltage.
8. Repeat steps 5 to complete the table 3.
78
 79

Laboratory Report
Table 1

Input Voltage Output Voltage

Calculated Measured % Error
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 2

Binary Inputs Measured analog output

00000001
00000010
00000011
00000100
00001000
00010000
00100000
01000000
10000000
11111111
Table 3
 80

Input Voltage Output Voltage

Calculated Measured % Error
1V
3V
5V
10V
12V
15V