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Design and implementation of BPSK transmitter and receiver for Software

Defined Radio on a Model Based Development Platform

Conference Paper · September 2011

DOI: 10.1109/ISIEA.2011.6108816

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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia
Design and Implementation of BPSK Transmitter
and Receiver for Software Defined Radio on a Model
Based Development Platform
Rehan Muzammil, M. Salim Beg
Dept. of Electronics Engineering,
Aligarh Muslim University,
Aligarh, India
rehan_muzammil@rediffmail.com, salim.beg@amu.ac.in
Abstract- This paper describes the design,
development and implementation of Binary Phase Shift
Keying Transmitter and Receiver for Software Defined
Radio on a Model Based Development Platform. Model
Based Development reduces the system design
considerably as compared to conventional method.
Advanced system design concepts including simulation,
code generation and implementation / testing is presented.
Software Defined Radio based framework which will be
performing data processing task at the baseband stage is
presented.
Keywords- SDR, FPGA, DSP, MBD.
I. INTRODUCTION
Software Defined Radio (SDR) or Software Radio is
a reconfigurable wireless system that can support multi-
communication standards [1-11]. The ever-growing interest in
software radio lies in the fact that it will provide multi-
standard terminals. The long term objective paves the way to
numerous technical challenges, namely, wide band antenna,
high frequency digital architecture, wide band analog to digital
conversion etc. [1]. Present technologies oblige their users to
buy a particular device for each type of communication
standard, and operators have to deploy base stations for each
system. Therefore, SDR can serve as the fundamental
technology. SDR allows system reconfiguration and
reprogramming by using only software commands using
FPGAs and DSP [2].
In response to myriad of communication standards
currently available, radio designers are architecting SDR
systems that have the ability to support any present and future
waveform specifications [3].
In a SDR, most radio receiver/processing functions
would be defined by user written software programs, to be run
on a general purpose (GP) programmable processor rather
than the functions being implemented strictly in non
programmable hardware. The functionality of a SDR
receiver/processor can be changed via software programming
[4].
978-1-4577-1417-7/11/$26.00 ©2011 IEEE
Mohsin M. Jamali
Dept. of Elect. Engg. & Comp. Sc.
The Univ. of Toledo,
Toledo, Ohio, USA
mjamali@utnet.utoledo.edu
The traditional SDR platform for digital processing is
mainly based on General Purpose Processors (GPPs) and
Digital Signal Processors (DSPs). In future Multiprocessor
System-On-Chip will be used which integrate heterogeneous
processing elements tailored for different processing tasks [5].
Wireless communication systems are rapidly
evolving through the incessant extension of the old standards
with the new generations. Every country has its own standard.
Therefore, SDR concept is emerging as a potential pragmatic
solution [6].
To avoid costly hardware upgrades or total
communications receiver/processor device replacement due to
sometimes rapidly changing wireless communication
protocols and standards, the concept of SDR was proposed [7].
This paper is divided into 10 sections. The sections to
follow are: section 2 describes the ideal SDR. Section 3
describes feasible SDR. Section 4 gives an overview of the
Model Based Design Concepts. Section 5 describes the
realization of the BPSK transceiver. Section 6 describes the
Front-end DSP model. Section 7 describes the Back-end
FPGA model. Section 8 gives a brief description of the
Simulation results. Section 9 gives a brief overview of the
Real Time Results. Section 10 gives the Conclusion.
II. IDEAL SOFTWARE RADIO ARCHITECTURE
The ideal Software Radio is given in Fig. 1. In this
architecture the digital part of the receiver is placed as close to
the antenna possible. The key problem with this type of
architecture is that the ADCs used in this design are not able
to cope with the very high frequency signals. The available
ADC samples at a rate of about 125 Million samples per
second (Msps) which is insufficient to sample signals of about
1 GHz at the receiver front-end.
III. FEASIBLE SOFTWARE RADIO ARCHITECTURE
The feasible SDR or practical SDR is the one in
which there is an IF stage between the RF and the base-band.
This is depicted in Fig. 2. The IF is responsible to bring down
the frequency which can be easily sampled by an ADC of
about 125 Msps. This receiver is divided into two parts,
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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia

Analog Front End (AFE) and Digital Front End (DFE). The the DSP and FPGA with MBDK tools, users can deploy and
AFE shifts the frequency from RF to IF with which the ADC validate algorithms on the hardware more rapidly.
has to act upon. The DFE is that part of the SDR which is used
to perform all the functions digitally which is done by
conventional Radio Receiver in analog form. For this to be
practical the DFE should be very high speed digital circuit.
Fortunately, DSPs and FPGAs now are commercially
available which can do the job quite effectively.

Fig. 3. The SFF SDR platform.

Fig. 1. Ideal Software Radio Architecture. Unlike the SDR development platforms on the
market, the SFF SDR development platform is a hybrid
hardware-software system that supplies the necessary full-
signal chain for multi-protocol software defined radios. By
separating the base-band, IF, and RF from one another as
distinct modules (rather than maintaining a single, fixed
architecture), developers can extend their radio development
capabilities and optimize costs and power consumption.
The SFF SDR development platforms can be used to
perform four types of development – FPGA, DSP, GPP, and
Model based (combination of the above three). This paper
describes model based development using this platform,
though only FPGA and DSP are exploited.

Fig. 2. Feasible Software Radio Receiver Architecture.

The conclusion we can draw from the above

discussion is that the Software Radio System able to be
realized today is half Digital and half Analog. This can be
realized only by high speed ADCs and Base-band section.

IV. MODEL BASED DEVELOPMENT

In this work, the authors have used a Model Based Fig. 4 Traditional System Design Methodology
Development platform. This is a Small Form factor (SFF)
SDR low power tunable equipment manufactured by Lyrtech,
Canada. This SFF SDR platform is conceived and designed to
be used in the development of applications in the field of
Software Defined Radio and is composed of three boards: RF
module, Data Conversion Module, Data Processing Module.
The board is illustrated in the Fig. 3.
The SFF SDR platform comes with two board support
packages – Board Software Development Kit (BSDK) and
Fig. 5 Model Based System Design Steps
Model Based Development kit (MBDK). The BSDK allows
users to quickly become fully functional developing C, C++, As can be seen from fig. 4 and 5 above [11], the
or assembly language codes for the DSP and GPP, or HDL traditional design involves 3 processes before production,
code for the FPGA by giving users an understanding of all the often performed by 3 distinct groups. These processes are
platform’s major interfaces such as VPSS, audio codec, data linked to each other as shown by arrows. Because of this it
conversion module, or RF module. takes much more time in the final outcome at the production
Similarly, the MBDK allows users to develop applications stage. On the other hand in the model based system design, all
for the platform with Simulink within MATLAB. By targeting these three processes are performed by a single group. Hence,

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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia

a substantial amount of the Design and Development time is
saved.
V. REALIZATION OF BPSK TRANSCEIVER
The Binary Phase Shift Keying (BPSK) is a digital
modulation scheme where the digital information is present in
the phase of the carrier. The phase of zero degrees is binary
‘0’ and a phase of 180 degrees is binary ‘1’. Hence, just by
observing the phase of the received waveform we can tell
whether the transmitted bit was ‘0’ or ‘1’. Here in this paper
the authors describe in detail the BPSK transceiver using SFF
SDR development boards. The circuit for this transceiver is
designed using the Simulink Tool which comes with
MATLAB 7.4. The other software installed are Code
Composer Studio, System Generator, Xilinx ISE 9.2i, and
MATLAB 7.4. All the above software is necessary for the
development of the transceiver. The design is model

Fig. 6. Front-End DSP Model

Fig. 7 Back-End FPGA Model.

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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia

based and hence authors will soon describe all the building to data words and passed on to the front-end. The FPGAs used
blocks used in the design. The design is done in two parts, in this kit are Virtex 4 SX35 in the Data Processing unit and
DSP front-end and FPGA back-end. The DSP model is given Virtex 4 LX25 in the Data Conversion block. The FPGA
in Fig. 6 and FPGA model is given in Fig. 7. model consists of the following blocks in order:

VI. FRONT-END DSP MODEL VPSS – VPBE RX is the Video Processing Back-End
Receiver (RX) block meant to receive a 32-bit word from
The Front-End DSP model is where all the control VPBE TX from the front end. This is a signed 32-bit word.
of the data conversion modules and the RF module resides. Reinterpret block is used to convert the signed 32-bit word
The DSP used in this design is TI C64x+ DSP. The DSP to unsigned 32-bit word. Block Coder block is the block
model consists of the following blocks in order: which is used for Channel Coding. The codes used here is (8,
DSP Options is the necessary block for DSP models. RFFE 4) block codes. The 32 bits here is divided into eight 4-bit
block is Radio Frequency Front End (RFFE) used for setting words. To these four bits three redundant parity bits are
the radio frequency for the design. Here it is set to 800 MHz. added according to the parity check matrix which is given as
The Receiver bandwidth is set using this block to 20 MHz. [10]:
The reference clock of the design is set to 10 MHz. The
sampling frequency is set which is 39062.5 Hz which is the 1 0 0 1 0 1 1
audio sampling frequency. Audio Codec Configuration block 0 1 0 1 1 1 0 (1)
is used to set the audio sampling frequency which is set to be 0 0 1 0 1 1 1
derived from back-end FPGA model. Here it is derived to be
39062.5Hz. Hence, the signal audio range is about 0 – 19.5
KHz. The second part of this block is the frame size which is 1 1 3 4 (2)
set to be 128. ADACMaster III block is used for enabling 2 1 2 3 (3)
and controlling the Analog-to-digital convertors (ADCs) and
Digital-to-analog converters (DACs). In this design only one 3 2 3 4 (4)
DAC and one ADC is used hence DAC A and ADC A are
enabled. Moreover the gain and attenuation of the ADC and Where, m1, m2, m3, and m4 are the 4-bits of data.
DACs are set using this block. The synchronizing method and The code word is given as:
the reference clock are also set which are PLL based and
external clock respectively (comes from RF board). The
1 2 3 1 2 3 4 (5)
sampling frequency is set to 39062.5 Hz which is the audio
sampling frequency. Audio Codec (In) is the audio codec
There is another parity bit calculated and is the parity
interface for the audio signal which is applied to the line-in of
of these 7 bits given as:
the data processing board. This block is responsible for the
digitization of the audio input. The word is 32-bit wide.
1 2 3 1 2 3 4 (6)
VPSS- VPBE TX block is called Video Processing Sub
System or Video Processing Back-End (VPBE) Transmitter
Hence, the code word now becomes:
(TX) which transmits the digital audio information to the back
end for coding, modulation and transmission. VPSS – VPFE
1 2 3 1 2 3 4 (7)
RX is the Video Processing Front-End (VPFE) Receiver (RX)
block used to receive the digital word from the back end after
Hence, for all the four 4-bit words this code word is
reception, demodulation and decoding. Audio Codec (Out)
calculated and we get a 64-bit word against the 32-bit word at
block receives the digital words from the VPSS VPFE RX
the input to the coder. 32 additional bits are the redundant bits
block and converts it back to analog form which can be
added. This 64-bit word is given to next block, which is the
monitored on the Headphone or Speakers. Hence, the real time
interleaver. Interleaver is used to rearrange the 64-bits added
audio signal is converted to digital form and passed to back-
to it by making a matrix of 8x8. Parallel-to-serial converter
end for processing and transmission and after the reception
block is used to convert to serial bit stream. Cosine TX block
back to the front end for converting it back to real time audio.
does the work of the Modulator. For bit ‘1’ the output cosine
The back-end is described in the next section.
wave is phase shifted by 1800 and for bit ‘0’ the output cosine
wave remains the same. The output is multiplied sample by
VII. BACK-END FPGA MODEL
sample with the cosine wave generated by Direct Digital
The Back-end FPGA model is where all the synthesizer (DDS). The frequency of the sine wave is
processing of the data is done. It is the section where the data calculated as:
word received from the front-end is converted into serial bit- f = 80000000/64 = 1.25 MHz, where 64 is the
stream, coded and modulated, transmitted and received, number of samples per cycle of the cosine wave and 80 MHz
demodulated, decoded and the serial bitstream converted back is the back-end sampling rate. The Numerator is the FPGA

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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia

sampling frequency. This cosine wave is the carrier which is function just the opposite of the Block Coder. It takes the 64
transmitted. The bit rate is calculated as: bit word, breaks it into eight 8-bit words and calculates the
parity and Syndrome for each. While the former signifies one
Rb = 39062.5*32 = 1.25 Mbps (8) bit or more bits in error, the latter signifies which bit is in
error. This can correct one bit error per 4 bits. Then it strips
where 39062.5 is the audio sampling frequency and off 4 redundant bits from the 8-bit words to get a final 32 bit
32 is the number of bits/sample. This is illustrated in the fig. 8 word. Hence, out of 32 bits theoretically 8 bit errors can be
below. Hence, for each bit-duration there is one cycle of the detected and corrected.
carrier.
DAC (digital-to-Analog converter) block is the next block
and is very essential as this converts the digitized cosine wave
into analog form which is up-converted to 800 MHz for
transmission by the RF section. The DAC used in the kit is 16-
bit Texas Instrument DAC5687.

Fig. 9. Cosine RX Subsystem.

VIII. SIMULATION RESULTS

The Simulation results of the bit stream before

Fig. 8. Cosine TX Subsystem. transmission and after the detection process is illustrated in
fig. 10 & 11 respectively. The simulation shows perfect
ADC (Analog-to-Digital converter) block is the next block. detection as can be seen by above figures except for some
From here onwards the receiver hardware starts. Though it is latency. These waveforms can be seen at Vector Scope 1
seen in the model as connected to the DAC block but in fact (cosine transmitter) and Vector Scope 1 (back-end model).
when the VHDL code is generated this connection is not
included in the design of the circuit. The VHDL code
generation is automatic with the help of System Generator
which invokes Xilinx ISE 9.2i for this. The data is transmitted
and received at the RF section and after the frequency down-
conversion at the IF stage, is analog to digital conversion by
the ADC which is the 14-bit Texas Instrument ADS5500.
Cosine RX is the next block and its purpose is to coherent
demodulation and detection. The detection is threshold
detection where the threshold is kept at ‘0’. Any value less
than ‘0’ is taken to be ‘1’ was transmitted otherwise ‘0’ was
transmitted. It is illustrated in fig. 9 below. MAC-FIR-LPF is
the block used in cosine RX which does the work of
integration as in coherent receiver. The cut-off frequency for
this is set to be 10 KHz. Its main purpose is to cut-off high
frequency signal and retain the DC component for the
detector. Detector is a block wherein the value of this DC
component determines the bit transmitted. If it is –ve then a
‘1’ was transmitted otherwise ‘0’ was transmitted. Serial-to-
Fig. 10. Simulation Result of bit stream at the Transmitter
parallel block collects 64 bits and gives it to the next block.
De-Interleaver is the next block and its function is opposite
to that of interleaver. Block Decoder block performs the

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 2011 IEEE Symposium on Industrial Electronics and Applications (ISIEA2011), September 25-28, 2011, Langkawi, Malaysia
Fig. 11. Simulation Result of bit stream at the Receiver
IX. REAL TIME RESULTS
After designing and testing the design by simulation
method, the circuit is made ready for the real time operation.
This can be done by generating the C and VHDL codes for
DSP and FPGAs respectively. The code for C language for
DSP is generated automatically by Code Composer Studio
invoked by Real Time Workshop. The code for VHDL for
FPGAs is generated automatically by System Generator. Both
these process is executed from Simulink Environment. After C
and VHDL code generation, they are build and compiled into
“.out” and “.bit” files respectively and then they are burned
onto the DSP and FPGAs respectively from the Simulink
Environment. As soon as this is done, the circuit is operational
and as an audio signal is given to the board at the “line-in”
from an mp3 player and the output is obtained at the “line-out”
which is connected to speakers. At the same time the
waveforms at the input and output to the system is monitored.
As can be seen by fig. 12 and 13, the audio transmitted
waveform in real time and audio received waveform in real
time are quite similar to each other, except for a small latency.
Both are taken at the same frame number. A good quality
output is observed.
Fig. 12 The Audio TX wave.
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Fig. 13 The Audio RX wave.
X. CONCLUSION
The BPSK transmitter and receiver is successfully
designed and developed. The circuit is tested both in
simulation mode and real time mode. The circuit gives perfect
result in the simulation mode. In the real time mode the circuit
seems to work satisfactorily. The whole design/development
process has taken considerably less time in case of model
based development method as compared to the traditional
design/development method.
ACKNOWLEDGMENT
This work is partially supported from the DRS
scheme of University Grants Commission, Govt. of India,
New Delhi (Ref. No. F.3-28/2004 SAP-II)
REFERENCES
[1] Ali Al Ghouwayel and Yves Louet, “FPGA Implementation of a
Reconfigurable FFT for Multi-standard Systems in Software Radio
Context”, IEEE Transactions on Consumer Electronics, VOL. 55,No. 2,
May 2009, pp. 950-958.
[2] Zlydareva, O.; Sacchi, C.; “Multi-Standard WIMAX/UMTS System
Framework Based on SDR”, Aerospace Conference, 2008 IEEE, pp. 1-13.
[3] Noseworthy, Joshua; Kulp, James, “Standard Interfaces for FPGA
Components”, IEEE Military Communications Conference, 2007,
MILCOM 2007, pp. 1-5.
[4] Alluri, V.B., Heath , J.R.; Lhamon, M., “A New Multichannel, Coherent
Amplitude Modulated, Time-Division Multiplexed, Software-Defined
Radio Receiver Architecture, and Field-Programmabale-Gate-Array
Technology Implementation”, IEEE Transactions on Signal Processing,
VOL. 58, Issue: 10, 2010, pp. 5369-5384.
[5] Qiwei Zhang; Kokkeler, A.B.J.; Smit, G.J.M., “A System-level Design
Method for Cognitive Radio on Reconfigurable Multi-processor
Architecture”, IEEE International Symposium on System-On-Chip, 2007,
pp. 1-4.
[6] Mohamed, K.E.; Ali, B.M.; Jamuar, S.S.; Khatun, S.; Ismail, A.,
“Implementation of CDMA Transmitter for a multi-standard SDR base
band platform”, Asia-Pacific Conference on Communications, 2007, APCC
2007, pp. 303-306.
[7] Bhargav Alluri, V.; Heath, J.R.; Lhamon, M., “A multi-channel coherent
Amplitude Modulated Time Division Multiplexed Software Defined Radio
Receiver architecture for Programmable-Logic-Device technology
implementation”, IEEE Radio and Wireless Symposium, 2009, RWS’09,
pp. 224-227.
[8] T. Jahan, R. Muzammil, M. Salim Beg, Izharuddin, “Software Defined
Radio based on 16-QAM for future mobile applications”, Proc. Nat. Conf.
Mobile Computing, New Delhi, 17-18 Oct. 2008, pp. 137-147.
[9] Xilinx website www.xilinx.com
[10] Simon Haykin, ”Digital Commuications”, John Wiley & Sons, 1988, pp
370-379.
[11] Ahmadian, M; Nazari, Z,J.; Nakhaee, N.; Kostic, Z.;
“Model Based Design and SDR”, DSP enabled Radio, 2005, the 2nd
IEE/EURASIP Conference on (Ref No. 2005/11086), pp 19/1 – 19/6.