4018

SEMICONDUCTOR TECHNICAL DATA

L SUFFIX
CERAMIC
The MC14018B contains five Johnson counter stages which are CASE 620
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on P SUFFIX
the Jam inputs will then be transferred to their respective Q outputs PLASTIC
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic CASE 648
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection D SUFFIX
table. Anti–lock gating is included in the MC14018B to assure proper SOIC
counting sequence. CASE 751B
• Fully Static Operation

ORDERING INFORMATION
• Schmitt Trigger on Clock Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCL Ceramic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range MC14XXXBD SOIC
• Pin–for–Pin Replacement for CD4018B
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
FUNCTIONAL TRUTH TABLE
VDD DC Supply Voltage – 0.5 to + 18.0 V
Preset Jam
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Clock Reset Enable Input Qn
lin, lout Input or Output Current (DC or Transient), ± 10 mA 0 0 X Qn
per Pin 0 0 X Dn*
X 0 1 0 1
PD Power Dissipation, per Package† 500 mW
X 0 1 1 0
_C
Tstg Storage Temperature – 65 to + 150 X 1 X X 1
TL Lead Temperature (8–Second Soldering) 260 _C * Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C PIN ASSIGNMENT
Din 1 16 VDD
JAM 1 2 15 R
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must JAM 2 3 14 C
be taken to avoid applications of any voltage higher than maximum rated
Q2 4 13 Q5
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q1 5 12 JAM 5
Unused inputs must always be tied to an appropriate logic voltage
Q3 6 11 Q4
level (e.g., either VSS or VDD). Unused outputs must be left open.
JAM 3 7 10 PE
VSS 8 9 JAM 4
REV 3
1/94
MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14018B
81
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 — 20 — 0.015 20 — 600
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.7 µA/kHz) f + IDD
Per Package) 15 IT = (1.0 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
MC14018B MOTOROLA CMOS LOGIC DATA

82
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ All Types
VDD
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise and Fall Time tTLH, tTHL ns
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80
Propagation Delay Time tPLH, ns
Clock to Q tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 265 ns 5.0 — 310 620
tPLH, tPHL = (0.36 ns/pF) CL + 102 ns 10 — 120 240
Reset to Q ns
tPLH = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740
tPLH = (0.36 ns/pF) CL + 132 ns 10 — 150 300
tPLH = (0.26 ns/pF) CL + 81 ns 15 — 100 200
Preset Enable to Q ns
tPLH, tPHL = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740
Setup Time tsu ns
Data (Pin 1) to Clock 5.0 200 0 —
10 100 0 —
15 80 0 —
Jam Inputs to Preset Enable 5.0 200 0 — ns
10 100 0 —
15 80 0 —
Data (Jam Inputs)–to–Preset th 5.0 540 270 — ns
Enable Hold Time 10 500 250 —
15 480 240 —
Clock Pulse Width tWH 5.0 400 200 — ns
10 200 100 —
15 160 80 —
Reset or Preset Enable tWH 5.0 290 145 — ns
Pulse Width 10 130 65 —
15 110 55 —
Clock Rise and Fall Time tTLH, tTHL 5.0 ns
10 No Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15
Clock Pulse Frequency fcl 5.0 — 2.5 1.25 MHz
10 — 6.5 3.25
15 — 8.0 4.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS
tPLH tPHL
VOH
90%
ANY OUTPUT 50%
10% VOL
tTLH tTHL
Figure 1. Switching Time Waveforms
MOTOROLA CMOS LOGIC DATA MC14018B

83
1
CLOCK
0
1
RESET
0
1
PRESET ENABLE
0
1
JAM 1
0
JAM 2 1
0
1
TIMING DIAGRAM JAM 3 DON’T CARE
UNTIL PRESET ENABLE 0
(Q5 Connected to Data Input) 1
GOES HIGH
JAM 4 0
1
JAM 5 0
1
Q1
0
1
Q2
0
1
Q3
0
1
Q4 0
1
Q5
0
FUNCTION SELECTION
Connect
Counter Data Input
Mode (Pin 1) to: Comments
Divide by 10 Q5
Divide by 8 Q4
No external
Divide by 6 Q3
components needed.
Divide by 4 Q2
Divide by 2 Q1
Divide by 9 Q5 • Q4 Gate package needed LOGIC DIAGRAM
Divide by 7 Q4 • Q3 to provide AND
Divide by 5 Q3 • Q2 function. Counter
JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
Divide by 3 Q2 • Q1 Skips all 1’s state 2 3 7 9 12
CLOCK
CLOCK 14
SHAPER
S S S S S
DATA 1 D Q D Q D Q D Q D Q
C C C C C
Q
R P R P R P R P R P
RESET 15
PRESET ENABLE 10
VDD = PIN 16
VSS = PIN 8
5 4 6 11 13
Q1 Q2 Q3 Q4 Q5
MC14018B MOTOROLA CMOS LOGIC DATA

84
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
1 8 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
–T– C ––– 0.200 ––– 5.08
N K D 0.015 0.020 0.39 0.50
SEATING
PLANE E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
E M H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
F G J 16 PL
L 0.300 BSC 7.62 BSC
D 16 PL 0.25 (0.010) M T B S M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
0.25 (0.010) M T A S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
MOTOROLA CMOS LOGIC DATA MC14018B

85
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
*MC14018B/D*
MC14018B ◊ MOTOROLA CMOS LOGIC DATA
MC14018B/D
86

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SEMICONDUCTOR TECHNICAL DATA

• Fully Static Operation

MOTOROLA CMOS LOGIC DATA

MC14018B MOTOROLA CMOS LOGIC DATA

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA MC14018B

MC14018B MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA MC14018B

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SEMICONDUCTOR TECHNICAL DATA

• Fully Static Operation

MOTOROLA CMOS LOGIC DATA

MC14018B MOTOROLA CMOS LOGIC DATA

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA MC14018B

MC14018B MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA MC14018B

How to reach us:

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