ENEE 3543 – Spring 2019 – Homework 2 – Solutions

1. Two amplifiers are placed in a cascade. The first (leftmost) has an input resistance of 10K, an output
resistance of 1K, and an open circuit gain (no load at the output) of A vo = 10V/V. The second (rightmost) has an
input resistance of 20K, an output resistance of 2K, and an open circuit gain of A vo = 20V/V. Also, assume that a
non-ideal source with internal resistance equal to 100 Ohms is placed at the input of the cascade. The input
source provides a sinusoidal input of 10V peak-to-peak. Also, assume that an 1K load is connected at the output
of the cascade. What is the peak-to-peak voltage at the output of the cascade (where the load is connected)?

Solution:

The overall amplifier, including the input source and the load can be modeled as the circuit above.

We have that the overall gain is:

Av = RL/(RL + Ro2) Avo2 Ri2/(Ri2 + Ro1) Avo1 Ri1/(Ri1 + RS) =

= (1K/(1K+2K) 20V/V) (20K/(20K+1K) 10V/V) 10K/(10K+0.1K) =
= (20/3) (200/21) (10/10.1) = 62.86 V/V

So, the peak-to-peak voltage at the output will be 10V 62.86 = 628.6 V

(Note: Of course, the purpose of this example was to practice finding the gain of a cascade of amplifiers. The
amplifiers which we are talking about in class would not be able to provide such a large output voltage.)
2. Design a common source amplifier which has an output resistance of 1K, and an open circuit gain (no load at
the output) of at least 20V/V. The voltage sources are 10V and -10V. You would like the DC voltage at the drain
to be 2V. It is also given that Kn = 50mA/V2, and VTN = 1V. Verify that your design is correct. What is the input
resistance of your amplifier?

Solution: We can use the common source amplifier circuit below:

Note: There is no unique solution for this problem, but the

values for ID, gm, RD, and VGS are unique.

We start from Ro = RD = 1k. So, ID = (10V – VD)/RD = 10V – 2V = 8mA.

From ID = ½ Kn(VGS – VTN)2 (needed for saturation)  1mA = ½ 50mA/V2(VGS – 1V)2  VGS = 1.2V. Notice that
this value is above VTN which is needed for the MOSFET to be in saturation.

Also, gm2 = 2 Kn ID = 800mA2/V2  gm = 10mA/V.

Therefore, Avo = -gmRD = 28.28 V/V, which is within the required specifications (it is more than 20V/V).

In order for the MOSFET to be in saturation, we need vD to be greater or equal to vG – VTN at all times. Nothing
has been specified for the output voltage swing, so we can assume that we want it to be 2V. So, vD can drop
down to 0V. There is a small signal at the gate, in addition to DC, but we can assume that it is almost 0 for the
purpose of checking this saturation condition. In other words, we can assume that vG (the total voltage at the
gate) is about equal to VG (the DC voltage at the gate). Then, we need VG – VTN to be less than 0V or VG to be less
than 1V. Lets assume that VG is 0V. Then, VS = -1.2V (because VGS = 1.2V, as we found above). Then, we can
find the value of the resistor at the source RS = (-1.2V – (-10V)/1mA = 8.2k.

For VG = 0, we just need RG1 = RG2 (due to symmetry in the voltage divider). We can choose 10M, for example,
so that Ri = RG1//RG2 = 5M.
3. Describe what voltage amplifier can probably achieve the following specifications. Provide some details such
as the type of amplifier, number of stages if more than one (and the order in which the different stages are
connected), and very importantly, explain why you would make these choices.

(a) Gain of 1000 V/V or higher, Rin = 10M or higher, Rout = 10K or lower: The gain is too large. For
example, considering a common emitter amplifier, and using the estimate for the gain: 10VCC, we can see that a
very large VCC would be needed. Moreover, the input resistance is very large, although the output resistance is
not too small. There may be several different solutions to this problem, but at least two stages are needed. One
possibility is two use two common source stages. If the 1st stage has a gain of 40 or 50, and the 2nd stage, again,
40 or 50 the amplifier could provide the gain necessary (it is assumed that connecting the first and second stages
will drop the gain somewhat, and this is why each individual stage has higher gain than 33.33 V/V). The 1st
common source amplifier stage can have a large input resistance which is controlled by the two resistors
connected at the gate (considering a four resistor biasing circuit). The output resistance will be the resistance of
the second stage, which could be 10K (it is not that small, which means that it is not too difficult to get).

(b) Gain of 0.8 V/V, Rin = 10M or higher, Rout = 1K or lower: A very large input resistance and a relatively
small output resistance are needed. At the same time, the gain is less than 1 V/V. A common collector or common
drain stage should be sufficient. The output resistance is 1/gm, and if gm = 1mA/V, which is reasonable, Rout =
1K. The gain should be gmRL/(1+gmRL) = 0.8. If gm = 1mA/V, then RL = 4K, which is a reasonable resistance.
If a common drain is chosen, the input resistance can be controlled by the two base resistors (considering a four
resistor biasing circuit).

(c) Gain of 10 V/V or higher, Rin = 100K or higher, Rout = 10K or lower: The gain is not very large, so a
single stage seems to be sufficient. The input resistance is somewhat large, but the output resistance is not too
small either. Therefore, a common source amplifier should work.

(d) Gain of 50 V/V or higher, Rin = 100 Ohms, Rout = 100K: A very small input resistance and a somewhat
large output resistance are needed. The gain is not huge, but it is not less than 1 V/V. This points to a common
gate or a common base amplifier. A single stage seems to be sufficient.
Problem from the book: 7.126

This problem refers to the circuit of Figure P7.125 in the book.

We can start with the DC design. Using the 15V voltage source we get that VB = 5V (because it has to be a third
of the source). Then, since VBE = 0.7V, we get that VE = 5V – 0.7V = 4.3V.

Then, it is given that IE = 2mA, and so we can find RE = (4.3V – 0V)/ 2mA = 2.15K.

The current at the base is IB = IE/(β+1) = 0.02mA (approximately).

The overall gain of the amplifier is Av = Rin/(Rin + Rsig) (-gm RC//RL) where Rin = R1//R2//rπ.

The book question is not very clear about where the current which feeds the base is. This current had to be a
tenth of the emitter current or 0.2mA. This is of course not the base current, because that has to be 0.02mA based
on the value of β. There are then two options:

1. If we assume that this is the current on R2, then the current on R1 is IB + 0.2mA = 0.22mA. Then, R2 =
5V/0.2mA = 25K, and R1 = (15V – 5V)/0.22mA = 45.45K.

2. If we assume that this is the current on R1, then the current on R2 is 0.2mA – IB = 0.18mA. Then R1 = (15V –
5V)/0.2mA = 50K, and R2 = 5V/0.18mA = 27.77K.

Lets consider both cases (only one of the two is needed for the solution to be correct, but I am showing both).

1. Choosing from the list of standard resistors, we can use those values which are as close as possible to the ones
that we found. Then, RE = 2.2K, R1 = 47K, R2 = 24K. Now, we have to recalculate everything for these new
values. So, this is like regular DC analysis of a BJT circuit.

First, we can find the Thevenin equivalent at the base: RTH = 47K//24K = 15.89K, and VTH = 15V
24K/(24K+47K) = 5.07V.

Then, we can use a KVL: -5.07V + 15.89K IB + 0.7V + (β+1) IB 2.2K = 0 → IB = 0.0184mA → Ic = 1.84mA.

We can then find the parameters: gm = IC/VT = 1.84mA/25mV = 73.6mA/V, rπ = β/gm = 1.36K, Rin =
47K//24K//1.36K = 1.25K.

Then, Avo = -40V/V =Rin/(Rin + Rsig) (-gm RC//RL) = 1.25K/(1.25K+2K) (-73.6mA/V RC//2K) →
RC//2K =1.41K → RC = 4.86K.

Again, using a standard resistor of 4.7K for RC, we get:

Av= Rin/(Rin + Rsig) (-gm RC//RL) = 1.25K/(1.25K+2K) (-73.6mA/V 4.7K//2K) = -39.6V/V which is just a little
smaller than what is required.

Finally, VC = 15 – 4.7K 1.84mA = 6.4V. Since, VB = 5.07V – RTH IB = 5.07V – 15.89K 0.0182mA = 4.78V, we can
have a negative swing at the output of 1.62V for the BJT to remain in active mode (it could be a little more so
that VC is just a little below VB).

2. Choosing from the list of standard resistors, we can use those which are as close as possible to the ones that
we found. Then, RE = 2.2K, R1 = 51K, R2 = 27K. Now, we have to recalculate everything for these new values.
So, this is like regular DC analysis of a BJT circuit.

First, we can find the Thevenin equivalent at the base: RTH = 51K//27K = 17.65K, and VTH = 15V
27K/(27K+51K) = 5.19V.
Then, we can use a KVL: -5.19V + 17.65K IB + 0.7V + (β+1) IB 2.2K = 0 → IB = 0.0187mA → Ic = 1.87mA.

We can then find the parameters: gm = IC/VT = 1.87mA/25mV = 74.8mA/V, rπ = β/gm = 1.34K, Rin =
51K//27K//1.34K = 1.25K.

Then, Avo = -40V/V =Rin/(Rin + Rsig) (-gm RC//RL) = 1.25K/(1.25K+2K) (-74.8mA/V RC//2K) →
RC//2K =1.39K → RC = 4.56K.

Again, using a standard resistor of 4.7K for RC, we get:

Av= Rin/(Rin + Rsig) (-gm RC//RL) = 1.25K/(1.25K+2K) (-74.8mA/V 4.7K//2K) = -40.363V/V which is just a little
higher than what is required.

Finally, VC = 15 – 4.7K 1.87mA = 6.2V. Since, VB = 5.19V – RTH IB = 5.19V – 17.65K 0.0187mA = 4.86V, we can
have a negative swing at the output of 1.34V for the BJT to remain in active mode (it could be a little more so
that VC is just a little below VB).