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ENEE 3543 – Homework 4 – Spring 2018

Solutions
1 In the following circuit, RD = 3K, VDD = 5V, VSS = -5V, Kn = 2mA/V2 and VTN = 1V for all transistors. Also,
consider that vG1 and vG2 are small signal voltage sources (i.e., their DC component is 0V). Remember
that when the NMOS is in saturation, ID = ½ Kn(VGS – VTN)2, and gm2 = 2KnID. Also, the expression for the
gains of the NMOS differential amplifier are:
Acd = 0 V/V, |Acc| = RD/(1 + gm 2 RS1) for the 1st and |Acc| = RD/(1 + gm 2 RS2) for the 2nd differential
amplifier, |Add| = gmRD, |Adc| = ½ gmRD.

(a) Find the DC drain current of Q1 and Q2, so that the DC component of vD1 & vD2 is 2V.

ID1 = (VDD – VD1)/RD = (5V – 2V)/3K = 1mA


(b) What is the maximum possible AC swing at vD2 in this case (explain)?

The maximum voltage at the drain cannot exceed the maximum voltage in the circuit, i.e.,
VDD = 5V. Moreover, the transistor has to remain in saturation. So, it has to satisfy the well-
known condition: VD1 > VG1 – VTN, or VD1 > 0 – 1V = -1V. Therefore, the voltage at the drain
should be between -1V and 5V. This is a swing of 6V (3V below and and 3V above the DC
voltage at the drain, VD1 = 2V)

(c) Using the DC drain current of part (a), find RS1.

ID1 = ½ Kn(VGS1 – VTN)2 → 1mA = ½ 2mA/V2(VGS1 – 1V)2 → VGS1 = 2V → VS1 = -2V (since VG1 = 0).
The current at RS1 is 2 x 1mA = 2mA. Finally, RS1 = (VS1 – VSS)/2mA = (-2V – (-5V))/2mA = 1.5K
(d) Find the DC drain current of Q3 and Q4 so that the DC component of vo is 3V.
ID3 = (VDD – VD3)/RD = (5V – 3V)/3K = 2/3 mA
(e) Using the DC drain current of part (d) find RS2.

ID3 = ½ Kn(VGS3 – VTN)2 → 2/3 mA = ½ 2mA/V2(VGS3 – 1V)2 → VGS3 = 1.816V → VS3 = -0.184V
(since VG3 = VD2 = 2V). The current at RS2 is 2 x 2/3 mA = 4/3 mA. Finally, the resistance can be
found as RS2 = (VS3 – VSS)/(4/3) mA = (-0.184V – (-5V))/2mA = 3.61 K
(f) Assuming that the common mode input is 0V, calculate the small signal voltage gain:
|vo/(vG1 – vG2)|.
Essentially, this is the single-ended output of the second stage over the differential input
of the first stage. The two stages are connected at the differential output of the first stage and
the differential input of the second stage. Since the input resistance of the second stage
is infinity, the overall gain is equal to simply the product of the first stage gain, |A dd1|, and
the second stage gain, |A dc2|. In other words, |vo/(vG1 – vG2)| = |Add1| x |Adc2| = gm1 RD ½ gm2RD.
We have that gm12 = 2KnID1 = 2 x 2mA/V2 x 1mA = 4 mA2/V2 → gm1 = 2mA/V, and also gm22 =
2KnID2 = 2 x 2mA/V2 x 2/3 mA = 8/3 mA2/V2 → gm2 = 1.63 mA/V. Finally, we have that the gain is
|vo/(vG1 – vG2)| = |Add1| x |Adc2|= 2 mA/V x 3K x ½ x 1.63 mA/V x 3K = 14.67 V/V
(g) Would the gain of part (f) be different if the common mode input was not zero?

Yes, because the common mode input at the first stage would be present (although
attenuated) at the single-ended outputs of the first stage, namely the inputs of the second
stage. This would essentially result in a common mode input at the second stage. Since the
overall output is taken single-endedly, the common mode at the input would affect the
output. Of course, the output of the amplifier due to the common mode would be
significantly small, since it would be attenuated by both stages.
(h) Confirm that all transistors are in saturation for large signal (DC) operation.

VGS > VTN is valid for all transistors, because (although not explicitly shown) the solutions of the
quadratic equations ID2 = ½ Kn(VGS2 – VTN)2 and ID2 = ½ Kn(VGS2 – VTN)2 were chosen to satisfy this
condition.
Then, VD3 = 5V – 2/3 mA 3K = 3V. This is larger than VG3 ( = VD2) – VTN = 3V – 1V = 2V
(the same holds for the Q4)
Also, VD1 = 2V. This is larger than VG1 – VTN = 0V – 1V = -1V
(the same holds for the Q2)
Therefore, all transistors are in saturation (for large signal).
2. Consider the differential amplifier shown next. V DD = 5V, VSS = -5V, Kn = 2mA/V, and VTN = 1V. The
small signal differential gain is equal to |Add| = gmRD.

(a) Assuming that RD and RS cannot be equal, choose values for R D and RS so that |Add| = 5V/V and I
= 10mA, and so that the two transistors are in saturation. Confirm that your design is valid or not
by checking the transistor conditions. Find the CMRR (differential output).

Since I = 10mA, the drain current for each transistor will be 5mA. Then, we can obtain gm2 = 2KnI = 2
0.002 A/V2 0.005 A → gm = 0.00447 A/V
We need gmRD = 5 → RD = 1.118 K
Also, we can find VGS – VT = 2ID /gm = 2 x 0.005/0.00447 = 2.237V → VGS = 3.237V → VS = -3.23V
So, RS = (-3.23 – (-5))/0.01 = 177 Ohms
To check the validity of the design, we can observe that V GS – VT > 0. Also, VD = 5V – 0.005 1,118 = -
0.59V > VG – VT = -1V. So, the transistors are in saturation. Finally, for differential output, considering
the symmetry of the amplifier, CMRR is infinity.
(b) Repeat part (a) by replacing R S with the following transistor (V SS is again -5V) that has an Early
Effect resistance of ro = 50K. Determine the VGG needed for |Add| = 5V/V and I = 10mA. Does this
circuit work out (explain)?

The VGG needed is the one that ensures that the current at the drain of this transistor is 10mA. So, we
need
0.01 = 1⁄2 0.002 (VGS – 1V)2 → VGS = 4.16V → VGG = 4.16V + VSS = 4.16V + (-5V) = -0.84V.
From part (a) we know that the voltage at the source node of Q1 and Q2 is V S= -3.23V. At the same
time, this is the voltage at the drain of this transistor. Since -3.23V < V GG – VT = -0.84 – 1V = -1.84V,
the transistor is not in saturation, so this does not work out.